mathu.inc 5.1 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 2005 by Thomas Schatzl
  4. member of the Free Pascal development team
  5. See the file COPYING.FPC, included in this distribution,
  6. for details about the copyright.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. **********************************************************************}
  11. const
  12. RoundModeMask = %00000011;
  13. NonIEEEModeMask = %00000100;
  14. InvalidOperationMask = %10000000;
  15. OverflowMask = %01000000;
  16. UnderflowMask = %00100000;
  17. ZeroDivideMask = %00010000;
  18. InexactMask = %00001000;
  19. AllExceptionsMask = %11111000;
  20. ExceptionsPendingMask = %11111111111111100000011100000000;
  21. ExceptionMask = InvalidOperationMask or OverflowMask or UnderflowMask or ZeroDivideMask or InexactMask;
  22. AllConfigBits = ExceptionMask or NonIEEEModeMask or RoundModeMask;
  23. function getFPSCR : DWord; assembler; nostackframe;
  24. asm
  25. mffs f0
  26. stfd f0, -12(r1)
  27. lwz r3, -8(r1)
  28. end;
  29. procedure setFPSCR(newFPSCR : DWord); assembler; nostackframe;
  30. asm
  31. stw r3, -8(r1)
  32. lfd f0, -12(r1)
  33. mtfsf 255, f0
  34. end;
  35. {$ifdef aix}
  36. const
  37. FP_RND_RZ = 0;
  38. FP_RND_RN = 1;
  39. FP_RND_RP = 2;
  40. FP_RND_RM = 3;
  41. function fp_is_enabled(Mask: DWord): boolean;cdecl;external;
  42. procedure fp_enable(Mask: DWord);cdecl;external;
  43. function feclearexcept(Mask: DWord):DWord;cdecl;external;
  44. procedure fp_disable(Mask: DWord);cdecl;external;
  45. function fp_read_rnd: word;cdecl;external;
  46. function fp_swap_rnd(RoundMode: word): word;cdecl;external;
  47. {$else aix}
  48. const
  49. FP_RND_RZ = 1;
  50. FP_RND_RN = 0;
  51. FP_RND_RP = 2;
  52. FP_RND_RM = 3;
  53. {$endif aix}
  54. function GetRoundMode: TFPURoundingMode;
  55. begin
  56. {$ifndef aix}
  57. case (getFPSCR and RoundModeMask) of
  58. {$else not aix}
  59. case fp_read_rnd of
  60. {$endif not aix}
  61. FP_RND_RN : result := rmNearest;
  62. FP_RND_RZ : result := rmTruncate;
  63. FP_RND_RP : result := rmUp;
  64. FP_RND_RM : result := rmDown;
  65. end;
  66. end;
  67. function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
  68. var
  69. mode : DWord;
  70. begin
  71. softfloat_rounding_mode:=RoundMode;
  72. case (RoundMode) of
  73. rmNearest :
  74. begin
  75. mode := FP_RND_RN;
  76. end;
  77. rmTruncate :
  78. begin
  79. mode := FP_RND_RZ;
  80. end;
  81. rmUp :
  82. begin
  83. mode := FP_RND_RP;
  84. end;
  85. rmDown :
  86. begin
  87. mode := FP_RND_RM;
  88. end;
  89. end;
  90. {$ifndef aix}
  91. setFPSCR((getFPSCR and (not RoundModeMask)) or mode);
  92. {$else not aix}
  93. fp_swap_rnd(mode);
  94. {$endif not aix}
  95. result := RoundMode;
  96. end;
  97. function GetPrecisionMode: TFPUPrecisionMode;
  98. begin
  99. result := pmDouble;
  100. end;
  101. function SetPrecisionMode(const Precision: TFPUPrecisionMode): TFPUPrecisionMode;
  102. begin
  103. { nothing to do, not supported }
  104. result := pmDouble;
  105. end;
  106. function GetExceptionMask: TFPUExceptionMask;
  107. begin
  108. result := [];
  109. {$ifndef aix}
  110. if ((getFPSCR and InvalidOperationMask) = 0) then
  111. result := result + [exInvalidOp];
  112. if ((getFPSCR and OverflowMask) = 0) then
  113. result := result + [exOverflow];
  114. if ((getFPSCR and UnderflowMask) = 0) then
  115. result := result + [exUnderflow];
  116. if ((getFPSCR and ZeroDivideMask) = 0) then
  117. result := result + [exZeroDivide];
  118. if ((getFPSCR and InexactMask) = 0) then
  119. result := result + [exPrecision];
  120. {$else not aix}
  121. if not fp_is_enabled(InvalidOperationMask) then
  122. result := result + [exInvalidOp];
  123. if not fp_is_enabled(OverflowMask) then
  124. result := result + [exOverflow];
  125. if not fp_is_enabled(UnderflowMask) then
  126. result := result + [exUnderflow];
  127. if not fp_is_enabled(ZeroDivideMask) then
  128. result := result + [exZeroDivide];
  129. if not fp_is_enabled(InexactMask) then
  130. result := result + [exPrecision];
  131. {$endif not aix}
  132. end;
  133. function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
  134. var
  135. mode : DWord;
  136. begin
  137. mode := 0;
  138. softfloat_exception_mask := mask;
  139. if (exInvalidOp in Mask) then
  140. begin
  141. mode := mode or InvalidOperationMask;
  142. end;
  143. if (exOverflow in Mask) then
  144. begin
  145. mode := mode or OverflowMask;
  146. end;
  147. if (exUnderflow in Mask) then
  148. begin
  149. mode := mode or UnderflowMask;
  150. end;
  151. if (exZeroDivide in Mask) then
  152. begin
  153. mode := mode or ZeroDivideMask;
  154. end;
  155. if (exPrecision in Mask) then
  156. begin
  157. mode := mode or InexactMask;
  158. end;
  159. setFPSCR((getFPSCR or ExceptionMask) and not mode and not ExceptionsPendingMask);
  160. softfloat_exception_flags := [];
  161. { also clear out pending exceptions on AIX }
  162. {$ifdef aix}
  163. { clear pending exceptions }
  164. feclearexcept(AllExceptionsMask);
  165. { enable the exceptions that are not disabled }
  166. fp_enable(mode xor AllExceptionsMask);
  167. { and disable the rest }
  168. fp_disable(mode);
  169. {$endif}
  170. result := Mask - [exDenormalized];
  171. end;
  172. procedure ClearExceptions(RaisePending: Boolean = true);
  173. begin
  174. {$ifdef aix}
  175. { clear pending exceptions }
  176. feclearexcept(AllExceptionsMask);
  177. {$endif}
  178. softfloat_exception_flags := [];
  179. { RaisePending has no effect on PPC, always raises them at the correct location }
  180. setFPSCR(getFPSCR and (not ExceptionsPendingMask));
  181. end;