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aasmcpu.pas
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4e2fb9d28b
* MIPS: fixed O_MOVE_SOURCE and O_MOVE_DEST constants (they were swapped, amazing that it ever worked with such a mistake).
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11 years ago |
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aoptcpu.pas
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a709a9b637
* MIPS peephole: check that operand is present before accessing its fields, also check that it's not a branch target. Mantis #27608.
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10 years ago |
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aoptcpub.pas
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93e0dd9c2f
* Patch from Fuxin Zhang: other mips and mipsel CPUs changes
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13 years ago |
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aoptcpud.pas
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0c8546f94c
* more MIPS code of David Zhang integrated
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15 years ago |
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cgcpu.pas
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06ee500352
* MIPS: improved code generation in make_simple_ref
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10 years ago |
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cpubase.pas
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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cpuelf.pas
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901275b4a1
Switch back to emitting BLX instructions and fix calculation of constant offsets(should rarely/never happen).
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10 years ago |
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cpugas.pas
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b46ce6b70e
* Fixed condition to output div/divu having R0 as first operand as non-macros.
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10 years ago |
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cpuinfo.pas
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5c67fcc43f
+ change always floating point divisions into multiplications if they are a power of two,
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10 years ago |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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11 years ago |
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cpupara.pas
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c3350d13f9
* MIPS: floating point parameters on stack should be loaded to/from FPU registers directly, without using temp.
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12 years ago |
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cpupi.pas
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96dd464bf2
* Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.
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11 years ago |
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cputarg.pas
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b2b26f84cf
* partially merged the mips-embedded branch of Michael Ring:
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11 years ago |
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hlcgcpu.pas
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b2b26f84cf
* partially merged the mips-embedded branch of Michael Ring:
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11 years ago |
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itcpugas.pas
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3d2a27c66c
* fix fpu register type
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13 years ago |
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mipsreg.dat
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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ncpuadd.pas
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57094d495b
+ MIPS: implement inline full 64-bit multiplication, for cases when overflow checking is off and CPU is set to mips32r2.
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10 years ago |
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ncpucall.pas
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87684e1cf1
* MIPS: clean up
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11 years ago |
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ncpucnv.pas
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5655baa23a
* MIPS: optimized conversion of unsigned 32-bit integers to float, now uses one integer register instead of two and does not generate redundant move.
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11 years ago |
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ncpuinln.pas
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4065483a50
* completed thlcgobj.location_force_fpureg(), use it everywhere and removed
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11 years ago |
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ncpuld.pas
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4b820a1ca5
- Removed tcgloadnode.generate_picvaraccess, it is never used and is not necessary because PIC stuff is handled at lower levels.
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12 years ago |
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ncpumat.pas
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cd27d64cd5
+ Support (as target-independent as possible) optimization of division by constants:
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11 years ago |
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ncpuset.pas
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e163a2c813
* MIPS and SPARC: determine whether case expression is in range using a single unsigned comparison (like it is done on other targets).
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11 years ago |
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opcode.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 years ago |
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racpugas.pas
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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rgcpu.pas
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3b06465322
+ MIPS: support replacement spilling for mov.s, mov.d and (partially) mtc1 instructions.
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11 years ago |
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rmipscon.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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rmipsdwf.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgas.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsgss.inc
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f58fcdf401
+ basic mips stuff
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20 years ago |
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rmipsnor.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsnum.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsrni.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssri.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssta.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipsstd.inc
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c260879439
* MIPS: updated registers, dropped special registers not recognized by GAS (actually, "pc" is recognized, but it is used only for MIPS16 mode, so it is easier to add back if/when this mode is supported), added FPU condition code registers ($fcc0..$fcc7).
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11 years ago |
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rmipssup.inc
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e367ccc0ee
* MIPS: changed superregister number for $fcc0..$fcc7 to start from 32, so that range 0..31 can be used without translating into symbolic names.
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11 years ago |
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strinst.inc
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4e7c908b0d
+ MIPS: added movn and movz instructions.
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11 years ago |
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symcpu.pas
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02495c17bd
Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".
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11 years ago |
Jeppe Johansen
914e9e7b49
Merged from trunk