cgcpu.pas 108 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getaddressregister(list:TAsmList):TRegister;override;
  35. function GetHigh(const r : TRegister) : TRegister;inline;
  36. function GetOffsetReg(const r: TRegister;ofs : shortint): TRegister;override;
  37. function GetOffsetReg64(const r,rhi: TRegister;ofs : shortint): TRegister;override;
  38. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  39. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  40. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  41. procedure a_load_reg_cgpara(list : TAsmList; size : tcgsize;r : tregister; const cgpara : tcgpara);override;
  42. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  43. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  44. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  45. procedure a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister); override;
  46. procedure a_op_const_reg_reg(list : TAsmList;op : TOpCg;size : tcgsize; a : tcgint;src,dst : tregister); override;
  47. procedure a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  48. procedure a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation); override;
  49. { move instructions }
  50. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  51. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  52. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  53. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  54. { fpu move instructions }
  55. procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
  56. procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
  57. procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
  58. { comparison operations }
  59. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  60. l : tasmlabel);override;
  61. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  62. procedure a_jmp_name(list : TAsmList;const s : string); override;
  63. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  64. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  65. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  66. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  67. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  68. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  69. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  70. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  71. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  72. procedure g_overflowCheck_loc(List: TAsmList; const Loc: TLocation; def: TDef; ovloc: tlocation); override;
  73. procedure g_save_registers(list : TAsmList);override;
  74. procedure g_restore_registers(list : TAsmList);override;
  75. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  76. procedure fixref(list : TAsmList;var ref : treference);
  77. function normalize_ref(list : TAsmList;ref : treference;
  78. tmpreg : tregister) : treference;
  79. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  80. procedure a_adjust_sp(list: TAsmList; value: longint);
  81. function GetLoad(const ref : treference) : tasmop;
  82. function GetStore(const ref: treference): tasmop;
  83. procedure gen_multiply(list: TAsmList; op: topcg; size: TCgSize; src2, src1, dst: tregister; check_overflow: boolean; var ovloc: tlocation);
  84. private
  85. procedure a_op_const_reg_reg_internal(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, srchi, dst, dsthi: tregister);
  86. protected
  87. procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  88. procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
  89. procedure maybegetcpuregister(list : tasmlist; reg : tregister);
  90. function addr_is_io_register(const addr: integer): boolean;
  91. end;
  92. tcg64favr = class(tcg64f32)
  93. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  94. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  95. procedure a_op64_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; value: int64;src,dst: tregister64);override;
  96. end;
  97. procedure create_codegen;
  98. const
  99. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  100. A_NONE,A_MULS,A_MUL,A_NEG,A_COM,A_OR,
  101. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  102. implementation
  103. uses
  104. globals,verbose,systems,cutils,
  105. fmodule,
  106. symconst,symsym,symtable,
  107. tgobj,rgobj,
  108. procinfo,cpupi,
  109. paramgr;
  110. procedure tcgavr.init_register_allocators;
  111. begin
  112. inherited init_register_allocators;
  113. if CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype] then
  114. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  115. [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25],first_int_imreg,[])
  116. else
  117. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  118. [RS_R18,RS_R19,RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  119. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,
  120. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17],first_int_imreg,[]);
  121. end;
  122. procedure tcgavr.done_register_allocators;
  123. begin
  124. rg[R_INTREGISTER].free;
  125. // rg[R_ADDRESSREGISTER].free;
  126. inherited done_register_allocators;
  127. end;
  128. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  129. begin
  130. Result:=getintregister(list,OS_ADDR);
  131. end;
  132. function tcgavr.GetHigh(const r : TRegister) : TRegister;
  133. begin
  134. result:=GetNextReg(r);
  135. end;
  136. function tcgavr.GetOffsetReg(const r: TRegister;ofs : shortint): TRegister;
  137. begin
  138. result:=TRegister(longint(r)+ofs);
  139. end;
  140. function tcgavr.GetOffsetReg64(const r,rhi: TRegister;ofs : shortint): TRegister;
  141. begin
  142. if ofs>3 then
  143. result:=TRegister(longint(rhi)+ofs-4)
  144. else
  145. result:=TRegister(longint(r)+ofs);
  146. end;
  147. procedure tcgavr.a_load_reg_cgpara(list : TAsmList;size : tcgsize;r : tregister;const cgpara : tcgpara);
  148. procedure load_para_loc(r : TRegister;paraloc : PCGParaLocation);
  149. var
  150. ref : treference;
  151. begin
  152. paramanager.allocparaloc(list,paraloc);
  153. case paraloc^.loc of
  154. LOC_REGISTER,LOC_CREGISTER:
  155. a_load_reg_reg(list,paraloc^.size,paraloc^.size,r,paraloc^.register);
  156. LOC_REFERENCE,LOC_CREFERENCE:
  157. begin
  158. reference_reset_base(ref,paraloc^.reference.index,paraloc^.reference.offset,ctempposinvalid,2,[]);
  159. if ref.base<>NR_STACK_POINTER_REG then
  160. Internalerror(2020011801);
  161. { as AVR allows no stack indirect addressing, everything else than a push makes no sense }
  162. list.concat(taicpu.op_reg(A_PUSH,r));
  163. end;
  164. else
  165. internalerror(2002071007);
  166. end;
  167. end;
  168. var
  169. i, i2 : longint;
  170. hp : PCGParaLocation;
  171. begin
  172. if not(tcgsize2size[cgpara.Size] in [1..4]) then
  173. internalerror(2014011106);
  174. hp:=cgpara.location;
  175. i:=0;
  176. while i<tcgsize2size[cgpara.Size] do
  177. begin
  178. if not(assigned(hp)) then
  179. internalerror(2014011102);
  180. inc(i, tcgsize2size[hp^.Size]);
  181. if hp^.Loc=LOC_REGISTER then
  182. begin
  183. load_para_loc(r,hp);
  184. hp:=hp^.Next;
  185. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  186. if i<tcgsize2size[cgpara.Size] then
  187. r:=GetNextReg(r);
  188. end
  189. else
  190. begin
  191. load_para_loc(r,hp);
  192. if i<tcgsize2size[cgpara.Size] then
  193. for i2:=1 to tcgsize2size[hp^.Size] do
  194. r:=GetNextReg(r);
  195. hp:=hp^.Next;
  196. end;
  197. end;
  198. if assigned(hp) then
  199. internalerror(2014011103);
  200. end;
  201. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  202. var
  203. i,j : longint;
  204. hp : PCGParaLocation;
  205. tmpreg: TRegister;
  206. begin
  207. if not(tcgsize2size[paraloc.Size] in [1..4]) then
  208. internalerror(2014011107);
  209. hp:=paraloc.location;
  210. i:=1;
  211. while i<=tcgsize2size[paraloc.Size] do
  212. begin
  213. if not(assigned(hp)) then
  214. internalerror(2014011105);
  215. paramanager.allocparaloc(list,hp);
  216. case hp^.loc of
  217. LOC_REGISTER,LOC_CREGISTER:
  218. begin
  219. if (tcgsize2size[hp^.size]<>1) or
  220. (hp^.shiftval<>0) then
  221. internalerror(2015041101);
  222. a_load_const_reg(list,hp^.size,(a shr (8*(i-1))) and $ff,hp^.register);
  223. inc(i,tcgsize2size[hp^.size]);
  224. hp:=hp^.Next;
  225. end;
  226. LOC_REFERENCE,LOC_CREFERENCE:
  227. begin
  228. for j:=1 to tcgsize2size[hp^.size] do
  229. begin
  230. tmpreg:=getintregister(list,OS_8);
  231. a_load_const_reg(list,OS_8,(a shr (8*(i-1+j-1))) and $ff,tmpreg);
  232. { as AVR allows no stack indirect addressing, everything else than a push makes no sense }
  233. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  234. end;
  235. inc(i,tcgsize2size[hp^.size]);
  236. hp:=hp^.Next;
  237. end;
  238. else
  239. internalerror(2002071008);
  240. end;
  241. end;
  242. end;
  243. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  244. var
  245. tmpref: treference;
  246. location: pcgparalocation;
  247. sizeleft: tcgint;
  248. i: Integer;
  249. tmpreg: TRegister;
  250. begin
  251. location := paraloc.location;
  252. tmpref := r;
  253. sizeleft := paraloc.intsize;
  254. while assigned(location) do
  255. begin
  256. paramanager.allocparaloc(list,location);
  257. case location^.loc of
  258. LOC_REGISTER,LOC_CREGISTER:
  259. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  260. LOC_REFERENCE:
  261. begin
  262. for i:=1 to sizeleft do
  263. begin
  264. tmpreg:=getintregister(list,OS_8);
  265. a_load_ref_reg(list,OS_8,OS_8,tmpref,tmpreg);
  266. { as AVR allows no stack indirect addressing, everything else than a push makes no sense }
  267. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  268. inc(tmpref.offset);
  269. end;
  270. end;
  271. LOC_VOID:
  272. begin
  273. // nothing to do
  274. end;
  275. else
  276. internalerror(2002081103);
  277. end;
  278. inc(tmpref.offset,tcgsize2size[location^.size]);
  279. dec(sizeleft,tcgsize2size[location^.size]);
  280. location := location^.next;
  281. end;
  282. end;
  283. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  284. var
  285. tmpreg: tregister;
  286. begin
  287. tmpreg:=getaddressregister(list);
  288. a_loadaddr_ref_reg(list,r,tmpreg);
  289. a_load_reg_cgpara(list,OS_ADDR,tmpreg,paraloc);
  290. end;
  291. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  292. var
  293. sym: TAsmSymbol;
  294. begin
  295. if weak then
  296. sym:=current_asmdata.WeakRefAsmSymbol(s,AT_FUNCTION)
  297. else
  298. sym:=current_asmdata.RefAsmSymbol(s,AT_FUNCTION);
  299. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  300. list.concat(taicpu.op_sym(A_CALL,sym))
  301. else
  302. list.concat(taicpu.op_sym(A_RCALL,sym));
  303. include(current_procinfo.flags,pi_do_call);
  304. end;
  305. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  306. begin
  307. a_reg_alloc(list,NR_ZLO);
  308. emit_mov(list,NR_ZLO,reg);
  309. a_reg_alloc(list,NR_ZHI);
  310. emit_mov(list,NR_ZHI,GetHigh(reg));
  311. list.concat(taicpu.op_none(A_ICALL));
  312. a_reg_dealloc(list,NR_ZHI);
  313. a_reg_dealloc(list,NR_ZLO);
  314. include(current_procinfo.flags,pi_do_call);
  315. end;
  316. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  317. begin
  318. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  319. internalerror(2012102403);
  320. a_op_const_reg_internal(list,Op,size,a,reg,NR_NO);
  321. end;
  322. procedure tcgavr.a_op_reg_reg(list: TAsmList; Op: TOpCG; size: TCGSize; src, dst : TRegister);
  323. begin
  324. if not(size in [OS_S8,OS_8,OS_S16,OS_16,OS_S32,OS_32]) then
  325. internalerror(2012102401);
  326. a_op_reg_reg_internal(list,Op,size,src,NR_NO,dst,NR_NO);
  327. end;
  328. procedure tcgavr.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
  329. begin
  330. a_op_const_reg_reg_internal(list,op,size,a,src,NR_NO,dst,NR_NO);
  331. end;
  332. procedure tcgavr.a_op_const_reg_reg_internal(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src,srchi,dst,dsthi: tregister);
  333. var
  334. countreg: TRegister;
  335. b, b2, i, j: byte;
  336. s1, s2, t1: integer;
  337. l1: TAsmLabel;
  338. oldexecutionweight: LongInt;
  339. begin
  340. if (op in [OP_MUL,OP_IMUL]) and (size in [OS_16,OS_S16]) and (a in [2,4,8]) then
  341. begin
  342. emit_mov(list,dst,src);
  343. emit_mov(list,GetNextReg(dst),GetNextReg(src));
  344. a:=a shr 1;
  345. while a>0 do
  346. begin
  347. list.concat(taicpu.op_reg(A_LSL,dst));
  348. list.concat(taicpu.op_reg(A_ROL,GetNextReg(dst)));
  349. a:=a shr 1;
  350. end;
  351. end
  352. else if (op in [OP_SHL,OP_SHR]) and
  353. { a=0 get eliminated later by tcg.optimize_op_const }
  354. (a>0) then
  355. begin
  356. { number of bytes to shift }
  357. b:=a div 8;
  358. { Ensure that b is never larger than base type }
  359. if b>tcgsize2size[size] then
  360. begin
  361. b:=tcgsize2size[size];
  362. b2:=0;
  363. end
  364. else
  365. b2:=a mod 8;
  366. if b < tcgsize2size[size] then
  367. { copy from src to dst accounting for shift offset }
  368. for i:=0 to (tcgsize2size[size]-b-1) do
  369. if op=OP_SHL then
  370. a_load_reg_reg(list,OS_8,OS_8,
  371. GetOffsetReg64(src,srchi,i),
  372. GetOffsetReg64(dst,dsthi,i+b))
  373. else
  374. a_load_reg_reg(list,OS_8,OS_8,
  375. GetOffsetReg64(src,srchi,i+b),
  376. GetOffsetReg64(dst,dsthi,i));
  377. { remaining bit shifts }
  378. if b2 > 0 then
  379. begin
  380. { Cost of loop }
  381. s1:=3+tcgsize2size[size]-b;
  382. t1:=b2*(tcgsize2size[size]-b+3);
  383. { Cost of loop unrolling,t2=s2 }
  384. s2:=b2*(tcgsize2size[size]-b);
  385. if ((cs_opt_size in current_settings.optimizerswitches) and (s1<s2)) or
  386. (((s2-s1)-t1/s2)>0) then
  387. begin
  388. { Shift non-moved bytes in loop }
  389. current_asmdata.getjumplabel(l1);
  390. countreg:=getintregister(list,OS_8);
  391. a_load_const_reg(list,OS_8,b2,countreg);
  392. cg.a_label(list,l1);
  393. oldexecutionweight:=executionweight;
  394. executionweight:=executionweight*b2;
  395. if op=OP_SHL then
  396. list.concat(taicpu.op_reg(A_LSL,GetOffsetReg64(dst,dsthi,b)))
  397. else
  398. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1-b)));
  399. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  400. begin
  401. for i:=2+b to tcgsize2size[size] do
  402. if op=OP_SHL then
  403. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)))
  404. else
  405. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  406. end;
  407. list.concat(taicpu.op_reg(A_DEC,countreg));
  408. a_jmp_flags(list,F_NE,l1);
  409. executionweight:=oldexecutionweight;
  410. { keep registers alive }
  411. a_reg_sync(list,countreg);
  412. end
  413. else
  414. begin
  415. { Unroll shift loop over non-moved bytes }
  416. for j:=1 to b2 do
  417. begin
  418. if op=OP_SHL then
  419. list.concat(taicpu.op_reg(A_LSL,
  420. GetOffsetReg64(dst,dsthi,b)))
  421. else
  422. list.concat(taicpu.op_reg(A_LSR,
  423. GetOffsetReg64(dst,dsthi,tcgsize2size[size]-b-1)));
  424. if not(size in [OS_8,OS_S8]) then
  425. for i:=2 to tcgsize2size[size]-b do
  426. if op=OP_SHL then
  427. list.concat(taicpu.op_reg(A_ROL,
  428. GetOffsetReg64(dst,dsthi,b+i-1)))
  429. else
  430. list.concat(taicpu.op_reg(A_ROR,
  431. GetOffsetReg64(dst,dsthi,tcgsize2size[size]-b-i)));
  432. end;
  433. end;
  434. end;
  435. { fill skipped destination registers with 0
  436. Do last,then optimizer can optimize register moves }
  437. for i:=1 to b do
  438. if op=OP_SHL then
  439. emit_mov(list,GetOffsetReg64(dst,dsthi,i-1),GetDefaultZeroReg)
  440. else
  441. emit_mov(list,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i),GetDefaultZeroReg);
  442. end
  443. else
  444. inherited a_op_const_reg_reg(list,op,size,a,src,dst);
  445. end;
  446. procedure tcgavr.a_op_const_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister; setflags: boolean; var ovloc: tlocation);
  447. var
  448. tmpreg: TRegister;
  449. begin
  450. if (op in [OP_MUL,OP_IMUL]) and
  451. setflags then
  452. begin
  453. tmpreg:=getintregister(list,size);
  454. a_load_const_reg(list,size,a,tmpreg);
  455. a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
  456. end
  457. else
  458. begin
  459. inherited a_op_const_reg_reg_checkoverflow(list, op, size, a, src, dst, setflags, ovloc);
  460. ovloc.loc:=LOC_FLAGS;
  461. end;
  462. end;
  463. procedure tcgavr.a_op_reg_reg_reg_checkoverflow(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister; setflags: boolean; var ovloc: tlocation);
  464. begin
  465. if (op in [OP_MUL,OP_IMUL]) and
  466. setflags then
  467. gen_multiply(list,op,size,src1,src2,dst,setflags,ovloc)
  468. else
  469. begin
  470. inherited a_op_reg_reg_reg_checkoverflow(list, op, size, src1, src2, dst, setflags, ovloc);
  471. ovloc.loc:=LOC_FLAGS;
  472. end;
  473. end;
  474. procedure tcgavr.a_op_reg_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
  475. var
  476. countreg,
  477. tmpreg: tregister;
  478. i : integer;
  479. l1,l2 : tasmlabel;
  480. hovloc: tlocation;
  481. { NextRegDst* is sometimes called before the register usage and sometimes afterwards }
  482. procedure NextSrcDstPreInc;
  483. begin
  484. if i=5 then
  485. begin
  486. dst:=dsthi;
  487. src:=srchi;
  488. end
  489. else
  490. begin
  491. dst:=GetNextReg(dst);
  492. src:=GetNextReg(src);
  493. end;
  494. end;
  495. procedure NextSrcDstPostInc;
  496. begin
  497. if i=4 then
  498. begin
  499. dst:=dsthi;
  500. src:=srchi;
  501. end
  502. else
  503. begin
  504. dst:=GetNextReg(dst);
  505. src:=GetNextReg(src);
  506. end;
  507. end;
  508. { iterates TmpReg through all registers of dst }
  509. procedure NextTmp;
  510. begin
  511. if i=4 then
  512. tmpreg:=dsthi
  513. else
  514. tmpreg:=GetNextReg(tmpreg);
  515. end;
  516. begin
  517. case op of
  518. OP_ADD:
  519. begin
  520. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  521. for i:=2 to tcgsize2size[size] do
  522. begin
  523. NextSrcDstPreInc;
  524. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  525. end;
  526. end;
  527. OP_SUB:
  528. begin
  529. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  530. for i:=2 to tcgsize2size[size] do
  531. begin
  532. NextSrcDstPreInc;
  533. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  534. end;
  535. end;
  536. OP_NEG:
  537. begin
  538. if src<>dst then
  539. begin
  540. if size in [OS_S64,OS_64] then
  541. begin
  542. a_load_reg_reg(list,OS_32,OS_32,src,dst);
  543. a_load_reg_reg(list,OS_32,OS_32,srchi,dsthi);
  544. end
  545. else
  546. a_load_reg_reg(list,size,size,src,dst);
  547. end;
  548. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  549. begin
  550. tmpreg:=GetNextReg(dst);
  551. for i:=2 to tcgsize2size[size] do
  552. begin
  553. list.concat(taicpu.op_reg(A_COM,tmpreg));
  554. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  555. if i<tcgsize2size[size] then
  556. NextTmp;
  557. end;
  558. list.concat(taicpu.op_reg(A_NEG,dst));
  559. tmpreg:=GetNextReg(dst);
  560. for i:=2 to tcgsize2size[size] do
  561. begin
  562. list.concat(taicpu.op_reg_const(A_SBCI,tmpreg,-1));
  563. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  564. if i<tcgsize2size[size] then
  565. NextTmp;
  566. end;
  567. end
  568. else if size in [OS_S8,OS_8] then
  569. list.concat(taicpu.op_reg(A_NEG,dst))
  570. else
  571. Internalerror(2018030401);
  572. end;
  573. OP_NOT:
  574. begin
  575. for i:=1 to tcgsize2size[size] do
  576. begin
  577. if src<>dst then
  578. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  579. list.concat(taicpu.op_reg(A_COM,dst));
  580. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  581. if i<tcgsize2size[size] then
  582. NextSrcDstPostInc;
  583. end;
  584. end;
  585. OP_MUL,OP_IMUL:
  586. begin
  587. tmpreg:=dst;
  588. if size in [OS_16,OS_S16] then
  589. begin
  590. tmpreg:=getintregister(list,size);
  591. a_load_reg_reg(list,size,size,dst,tmpreg);
  592. end;
  593. gen_multiply(list,op,size,src,tmpreg,dst,false,hovloc);
  594. end;
  595. OP_DIV,OP_IDIV:
  596. { special stuff, needs separate handling inside code }
  597. { generator }
  598. internalerror(2011022001);
  599. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  600. begin
  601. current_asmdata.getjumplabel(l1);
  602. current_asmdata.getjumplabel(l2);
  603. countreg:=getintregister(list,OS_8);
  604. a_load_reg_reg(list,size,OS_8,src,countreg);
  605. list.concat(taicpu.op_reg(A_TST,countreg));
  606. a_jmp_flags(list,F_EQ,l2);
  607. cg.a_label(list,l1);
  608. case op of
  609. OP_SHR:
  610. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  611. OP_SHL:
  612. list.concat(taicpu.op_reg(A_LSL,dst));
  613. OP_SAR:
  614. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  615. OP_ROR:
  616. begin
  617. { load carry? }
  618. if not(size in [OS_8,OS_S8]) then
  619. begin
  620. list.concat(taicpu.op_none(A_CLC));
  621. list.concat(taicpu.op_reg_const(A_SBRC,dst,0));
  622. list.concat(taicpu.op_none(A_SEC));
  623. end;
  624. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1)));
  625. end;
  626. OP_ROL:
  627. begin
  628. { load carry? }
  629. if not(size in [OS_8,OS_S8]) then
  630. begin
  631. list.concat(taicpu.op_none(A_CLC));
  632. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-1),7));
  633. list.concat(taicpu.op_none(A_SEC));
  634. end;
  635. list.concat(taicpu.op_reg(A_ROL,dst))
  636. end;
  637. else
  638. internalerror(2011030901);
  639. end;
  640. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  641. begin
  642. for i:=2 to tcgsize2size[size] do
  643. begin
  644. case op of
  645. OP_ROR,
  646. OP_SHR:
  647. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  648. OP_ROL,
  649. OP_SHL:
  650. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(dst,dsthi,i-1)));
  651. OP_SAR:
  652. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(dst,dsthi,tcgsize2size[size]-i)));
  653. else
  654. internalerror(2011030902);
  655. end;
  656. end;
  657. end;
  658. list.concat(taicpu.op_reg(A_DEC,countreg));
  659. a_jmp_flags(list,F_NE,l1);
  660. { keep registers alive }
  661. a_reg_sync(list,countreg);
  662. cg.a_label(list,l2);
  663. end;
  664. OP_AND,OP_OR,OP_XOR:
  665. begin
  666. for i:=1 to tcgsize2size[size] do
  667. begin
  668. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  669. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  670. if i<tcgsize2size[size] then
  671. NextSrcDstPostInc;
  672. end;
  673. end;
  674. else
  675. internalerror(2011022004);
  676. end;
  677. end;
  678. procedure tcgavr.a_op_const_reg_internal(list: TAsmList; Op: TOpCG;
  679. size: TCGSize; a: tcgint; reg, reghi: TRegister);
  680. var
  681. mask : qword;
  682. shift : byte;
  683. i,j : byte;
  684. tmpreg : tregister;
  685. tmpreg64 : tregister64;
  686. { NextReg* is sometimes called before the register usage and sometimes afterwards }
  687. procedure NextRegPreInc;
  688. begin
  689. if i=5 then
  690. reg:=reghi
  691. else
  692. reg:=GetNextReg(reg);
  693. end;
  694. procedure NextRegPostInc;
  695. begin
  696. if i=4 then
  697. reg:=reghi
  698. else
  699. reg:=GetNextReg(reg);
  700. end;
  701. var
  702. curvalue : byte;
  703. l1: TAsmLabel;
  704. begin
  705. optimize_op_const(size,op,a);
  706. mask:=$ff;
  707. shift:=0;
  708. case op of
  709. OP_NONE:
  710. begin
  711. { Opcode is optimized away }
  712. end;
  713. OP_MOVE:
  714. begin
  715. { Optimized, replaced with a simple load }
  716. a_load_const_reg(list,size,a,reg);
  717. end;
  718. OP_OR:
  719. begin
  720. for i:=1 to tcgsize2size[size] do
  721. begin
  722. if ((qword(a) and mask) shr shift)<>0 then
  723. list.concat(taicpu.op_reg_const(A_ORI,reg,(qword(a) and mask) shr shift));
  724. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  725. if i<tcgsize2size[size] then
  726. NextRegPostInc;
  727. mask:=mask shl 8;
  728. inc(shift,8);
  729. end;
  730. end;
  731. OP_AND:
  732. begin
  733. for i:=1 to tcgsize2size[size] do
  734. begin
  735. if ((qword(a) and mask) shr shift)=0 then
  736. list.concat(taicpu.op_reg_reg(A_MOV,reg,GetDefaultZeroReg))
  737. else if ((qword(a) and mask) shr shift)<>$ff then
  738. begin
  739. getcpuregister(list,NR_R26);
  740. list.concat(taicpu.op_reg_const(A_LDI,NR_R26,(qword(a) and mask) shr shift));
  741. list.concat(taicpu.op_reg_reg(A_AND,reg,NR_R26));
  742. ungetcpuregister(list,NR_R26);
  743. end;
  744. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  745. if i<tcgsize2size[size] then
  746. NextRegPostInc;
  747. mask:=mask shl 8;
  748. inc(shift,8);
  749. end;
  750. end;
  751. OP_SUB:
  752. begin
  753. if ((a and mask)=1) and (tcgsize2size[size]=1) then
  754. list.concat(taicpu.op_reg(A_DEC,reg))
  755. else
  756. begin
  757. getcpuregister(list,NR_R26);
  758. list.concat(taicpu.op_reg_const(A_LDI,NR_R26,a and mask));
  759. list.concat(taicpu.op_reg_reg(A_SUB,reg,NR_R26));
  760. ungetcpuregister(list,NR_R26);
  761. end;
  762. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  763. begin
  764. for i:=2 to tcgsize2size[size] do
  765. begin
  766. NextRegPreInc;
  767. mask:=mask shl 8;
  768. inc(shift,8);
  769. curvalue:=(qword(a) and mask) shr shift;
  770. { decrease pressure on upper half of registers by using SBC ...,R1 instead
  771. of SBCI ...,0 }
  772. if curvalue=0 then
  773. list.concat(taicpu.op_reg_reg(A_SBC,reg,GetDefaultZeroReg))
  774. else
  775. list.concat(taicpu.op_reg_const(A_SBCI,reg,curvalue));
  776. end;
  777. end;
  778. end;
  779. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  780. begin
  781. if (op=OP_SAR) and (a>=(tcgsize2size[size]*8-1)) then
  782. begin
  783. current_asmdata.getjumplabel(l1);
  784. list.concat(taicpu.op_reg(A_TST,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  785. a_load_const_reg(list,OS_8,0,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1));
  786. a_jmp_flags(list,F_PL,l1);
  787. list.concat(taicpu.op_reg(A_DEC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  788. cg.a_label(list,l1);
  789. for i:=2 to tcgsize2size[size] do
  790. a_load_reg_reg(list,OS_8,OS_8,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1),GetOffsetReg64(reg,reghi,tcgsize2size[size]-i));
  791. end
  792. else if (op=OP_SHR) and (a=(tcgsize2size[size]*8-1)) then
  793. begin
  794. current_asmdata.getjumplabel(l1);
  795. list.concat(taicpu.op_reg(A_TST,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  796. a_load_const_reg(list,OS_8,0,GetOffsetReg64(reg,reghi,0));
  797. a_jmp_flags(list,F_PL,l1);
  798. list.concat(taicpu.op_reg(A_INC,GetOffsetReg64(reg,reghi,0)));
  799. cg.a_label(list,l1);
  800. for i:=1 to tcgsize2size[size]-1 do
  801. a_load_const_reg(list,OS_8,0,GetOffsetReg64(reg,reghi,i));
  802. end
  803. else if a*tcgsize2size[size]<=8 then
  804. begin
  805. for j:=1 to a do
  806. begin
  807. case op of
  808. OP_SHR:
  809. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  810. OP_SHL:
  811. list.concat(taicpu.op_reg(A_LSL,reg));
  812. OP_SAR:
  813. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  814. OP_ROR:
  815. begin
  816. { load carry? }
  817. if not(size in [OS_8,OS_S8]) then
  818. begin
  819. list.concat(taicpu.op_none(A_CLC));
  820. list.concat(taicpu.op_reg_const(A_SBRC,reg,0));
  821. list.concat(taicpu.op_none(A_SEC));
  822. end;
  823. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1)));
  824. end;
  825. OP_ROL:
  826. begin
  827. { load carry? }
  828. if not(size in [OS_8,OS_S8]) then
  829. begin
  830. list.concat(taicpu.op_none(A_CLC));
  831. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg64(reg,reghi,tcgsize2size[size]-1),7));
  832. list.concat(taicpu.op_none(A_SEC));
  833. end;
  834. list.concat(taicpu.op_reg(A_ROL,reg))
  835. end;
  836. else
  837. internalerror(2011030903);
  838. end;
  839. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  840. begin
  841. for i:=2 to tcgsize2size[size] do
  842. begin
  843. case op of
  844. OP_ROR,
  845. OP_SHR:
  846. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i)));
  847. OP_ROL,
  848. OP_SHL:
  849. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg64(reg,reghi,i-1)));
  850. OP_SAR:
  851. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg64(reg,reghi,tcgsize2size[size]-i)));
  852. else
  853. internalerror(2011030904);
  854. end;
  855. end;
  856. end;
  857. end;
  858. end
  859. else
  860. begin
  861. tmpreg:=getintregister(list,size);
  862. a_load_const_reg(list,size,a,tmpreg);
  863. a_op_reg_reg(list,op,size,tmpreg,reg);
  864. end;
  865. end;
  866. OP_ADD:
  867. begin
  868. curvalue:=a and mask;
  869. if curvalue=0 then
  870. list.concat(taicpu.op_reg_reg(A_ADD,reg,GetDefaultZeroReg))
  871. else if (curvalue=1) and (tcgsize2size[size]=1) then
  872. list.concat(taicpu.op_reg(A_INC,reg))
  873. else
  874. begin
  875. tmpreg:=getintregister(list,OS_8);
  876. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  877. list.concat(taicpu.op_reg_reg(A_ADD,reg,tmpreg));
  878. end;
  879. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  880. begin
  881. for i:=2 to tcgsize2size[size] do
  882. begin
  883. NextRegPreInc;
  884. mask:=mask shl 8;
  885. inc(shift,8);
  886. curvalue:=(qword(a) and mask) shr shift;
  887. { decrease pressure on upper half of registers by using ADC ...,R1 instead
  888. of ADD ...,0 }
  889. if curvalue=0 then
  890. list.concat(taicpu.op_reg_reg(A_ADC,reg,GetDefaultZeroReg))
  891. else
  892. begin
  893. tmpreg:=getintregister(list,OS_8);
  894. a_load_const_reg(list,OS_8,curvalue,tmpreg);
  895. list.concat(taicpu.op_reg_reg(A_ADC,reg,tmpreg));
  896. end;
  897. end;
  898. end;
  899. end;
  900. else
  901. begin
  902. if size in [OS_64,OS_S64] then
  903. begin
  904. tmpreg64.reglo:=getintregister(list,OS_32);
  905. tmpreg64.reghi:=getintregister(list,OS_32);
  906. cg64.a_load64_const_reg(list,a,tmpreg64);
  907. cg64.a_op64_reg_reg(list,op,size,tmpreg64,joinreg64(reg,reghi));
  908. end
  909. else
  910. begin
  911. {$if 0}
  912. { code not working yet }
  913. if (op=OP_SAR) and (a=31) and (size in [OS_32,OS_S32]) then
  914. begin
  915. tmpreg:=reg;
  916. for i:=1 to 4 do
  917. begin
  918. list.concat(taicpu.op_reg_reg(A_MOV,tmpreg,GetDefaultZeroReg));
  919. tmpreg:=GetNextReg(tmpreg);
  920. end;
  921. end
  922. else
  923. {$endif}
  924. begin
  925. tmpreg:=getintregister(list,size);
  926. a_load_const_reg(list,size,a,tmpreg);
  927. a_op_reg_reg(list,op,size,tmpreg,reg);
  928. end;
  929. end;
  930. end;
  931. end;
  932. end;
  933. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  934. var
  935. mask : qword;
  936. shift : byte;
  937. i : byte;
  938. begin
  939. mask:=$ff;
  940. shift:=0;
  941. for i:=1 to tcgsize2size[size] do
  942. begin
  943. if ((qword(a) and mask) shr shift)=0 then
  944. emit_mov(list,reg,GetDefaultZeroReg)
  945. else
  946. begin
  947. getcpuregister(list,NR_R26);
  948. list.concat(taicpu.op_reg_const(A_LDI,NR_R26,(qword(a) and mask) shr shift));
  949. a_load_reg_reg(list,OS_8,OS_8,NR_R26,reg);
  950. ungetcpuregister(list,NR_R26);
  951. end;
  952. mask:=mask shl 8;
  953. inc(shift,8);
  954. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  955. if i<tcgsize2size[size] then
  956. reg:=GetNextReg(reg);
  957. end;
  958. end;
  959. procedure tcgavr.maybegetcpuregister(list:tasmlist;reg : tregister);
  960. begin
  961. { allocate the register only, if a cpu register is passed }
  962. if getsupreg(reg)<first_int_imreg then
  963. getcpuregister(list,reg);
  964. end;
  965. { Returns true if dataspace address falls in I/O register range }
  966. function tcgavr.addr_is_io_register(const addr: integer): boolean;
  967. begin
  968. result := (not(current_settings.cputype in [cpu_avrxmega3,cpu_avrtiny]) and (addr>31)) or
  969. ((current_settings.cputype in [cpu_avrxmega3,cpu_avrtiny]) and (addr>=0)) and
  970. (addr<cpuinfo.embedded_controllers[current_settings.controllertype].srambase);
  971. end;
  972. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  973. var
  974. tmpref : treference;
  975. begin
  976. Result:=ref;
  977. if ref.addressmode<>AM_UNCHANGED then
  978. internalerror(2011021705);
  979. { Be sure to have a base register }
  980. if (ref.base=NR_NO) then
  981. begin
  982. ref.base:=ref.index;
  983. ref.index:=NR_NO;
  984. end;
  985. { can we take advantage of adiw/sbiw? }
  986. if (current_settings.cputype>=cpu_avr2) and not(assigned(ref.symbol)) and (ref.offset<>0) and (ref.offset>=-63) and (ref.offset<=63) and
  987. ((tmpreg=NR_R24) or (tmpreg=NR_R26) or (tmpreg=NR_R28) or (tmpreg=NR_R30)) and (ref.base<>NR_NO) then
  988. begin
  989. maybegetcpuregister(list,tmpreg);
  990. emit_mov(list,tmpreg,ref.base);
  991. maybegetcpuregister(list,GetNextReg(tmpreg));
  992. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  993. if ref.index<>NR_NO then
  994. begin
  995. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  996. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  997. end;
  998. if ref.offset>0 then
  999. list.concat(taicpu.op_reg_const(A_ADIW,tmpreg,ref.offset))
  1000. else
  1001. list.concat(taicpu.op_reg_const(A_SBIW,tmpreg,-ref.offset));
  1002. ref.offset:=0;
  1003. ref.base:=tmpreg;
  1004. ref.index:=NR_NO;
  1005. end
  1006. else if assigned(ref.symbol) or (ref.offset<>0) then
  1007. begin
  1008. reference_reset(tmpref,0,[]);
  1009. tmpref.symbol:=ref.symbol;
  1010. tmpref.offset:=ref.offset;
  1011. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1012. tmpref.refaddr:=addr_lo8_gs
  1013. else
  1014. tmpref.refaddr:=addr_lo8;
  1015. maybegetcpuregister(list,tmpreg);
  1016. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  1017. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  1018. tmpref.refaddr:=addr_hi8_gs
  1019. else
  1020. tmpref.refaddr:=addr_hi8;
  1021. maybegetcpuregister(list,GetNextReg(tmpreg));
  1022. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  1023. if (ref.base<>NR_NO) then
  1024. begin
  1025. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  1026. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  1027. end;
  1028. if (ref.index<>NR_NO) then
  1029. begin
  1030. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  1031. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  1032. end;
  1033. ref.symbol:=nil;
  1034. ref.offset:=0;
  1035. ref.base:=tmpreg;
  1036. ref.index:=NR_NO;
  1037. end
  1038. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  1039. begin
  1040. maybegetcpuregister(list,tmpreg);
  1041. emit_mov(list,tmpreg,ref.base);
  1042. maybegetcpuregister(list,GetNextReg(tmpreg));
  1043. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  1044. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  1045. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  1046. ref.base:=tmpreg;
  1047. ref.index:=NR_NO;
  1048. end
  1049. else if (ref.base<>NR_NO) then
  1050. begin
  1051. maybegetcpuregister(list,tmpreg);
  1052. emit_mov(list,tmpreg,ref.base);
  1053. maybegetcpuregister(list,GetNextReg(tmpreg));
  1054. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  1055. ref.base:=tmpreg;
  1056. ref.index:=NR_NO;
  1057. end
  1058. else if (ref.index<>NR_NO) then
  1059. begin
  1060. maybegetcpuregister(list,tmpreg);
  1061. emit_mov(list,tmpreg,ref.index);
  1062. maybegetcpuregister(list,GetNextReg(tmpreg));
  1063. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  1064. ref.base:=tmpreg;
  1065. ref.index:=NR_NO;
  1066. end
  1067. else
  1068. Internalerror(2020011901);
  1069. Result:=ref;
  1070. end;
  1071. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  1072. var
  1073. href : treference;
  1074. conv_done: boolean;
  1075. tmpreg : tregister;
  1076. i : integer;
  1077. QuickRef,ungetcpuregister_z: Boolean;
  1078. begin
  1079. QuickRef:=false;
  1080. ungetcpuregister_z:=false;
  1081. href:=Ref;
  1082. { ensure, href.base contains a valid register if there is any register used }
  1083. if href.base=NR_NO then
  1084. begin
  1085. href.base:=href.index;
  1086. href.index:=NR_NO;
  1087. end;
  1088. { try to use std/sts }
  1089. if not((href.Base=NR_NO) and (href.Index=NR_NO)) then
  1090. begin
  1091. if not((href.addressmode=AM_UNCHANGED) and
  1092. (href.symbol=nil) and
  1093. (href.Index=NR_NO) and
  1094. (href.Offset in [0..64-tcgsize2size[fromsize]])) or
  1095. (CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) then
  1096. begin
  1097. href:=normalize_ref(list,href,NR_R30);
  1098. getcpuregister(list,NR_R30);
  1099. getcpuregister(list,NR_R31);
  1100. ungetcpuregister_z:=true;
  1101. end
  1102. else
  1103. begin
  1104. if (href.base<>NR_R28) and (href.base<>NR_R30) then
  1105. begin
  1106. getcpuregister(list,NR_R30);
  1107. emit_mov(list,NR_R30,href.base);
  1108. getcpuregister(list,NR_R31);
  1109. emit_mov(list,NR_R31,GetNextReg(href.base));
  1110. href.base:=NR_R30;
  1111. ungetcpuregister_z:=true;
  1112. end;
  1113. QuickRef:=true;
  1114. end;
  1115. end
  1116. else
  1117. QuickRef:=true;
  1118. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1119. internalerror(2011021303);
  1120. conv_done:=false;
  1121. if tosize<>fromsize then
  1122. begin
  1123. conv_done:=true;
  1124. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1125. fromsize:=tosize;
  1126. case fromsize of
  1127. OS_8:
  1128. begin
  1129. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  1130. href.addressmode:=AM_POSTINCREMENT;
  1131. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1132. for i:=2 to tcgsize2size[tosize] do
  1133. begin
  1134. if QuickRef then
  1135. inc(href.offset);
  1136. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1137. href.addressmode:=AM_POSTINCREMENT
  1138. else
  1139. href.addressmode:=AM_UNCHANGED;
  1140. list.concat(taicpu.op_ref_reg(GetStore(href),href,GetDefaultZeroReg));
  1141. end;
  1142. end;
  1143. OS_S8:
  1144. begin
  1145. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  1146. href.addressmode:=AM_POSTINCREMENT;
  1147. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1148. if tcgsize2size[tosize]>1 then
  1149. begin
  1150. tmpreg:=getintregister(list,OS_8);
  1151. emit_mov(list,tmpreg,GetDefaultZeroReg);
  1152. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  1153. list.concat(taicpu.op_reg(A_COM,tmpreg));
  1154. for i:=2 to tcgsize2size[tosize] do
  1155. begin
  1156. if QuickRef then
  1157. inc(href.offset);
  1158. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1159. href.addressmode:=AM_POSTINCREMENT
  1160. else
  1161. href.addressmode:=AM_UNCHANGED;
  1162. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  1163. end;
  1164. end;
  1165. end;
  1166. OS_16:
  1167. begin
  1168. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  1169. href.addressmode:=AM_POSTINCREMENT;
  1170. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1171. if QuickRef then
  1172. inc(href.offset)
  1173. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  1174. href.addressmode:=AM_POSTINCREMENT
  1175. else
  1176. href.addressmode:=AM_UNCHANGED;
  1177. reg:=GetNextReg(reg);
  1178. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1179. for i:=3 to tcgsize2size[tosize] do
  1180. begin
  1181. if QuickRef then
  1182. inc(href.offset);
  1183. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1184. href.addressmode:=AM_POSTINCREMENT
  1185. else
  1186. href.addressmode:=AM_UNCHANGED;
  1187. list.concat(taicpu.op_ref_reg(GetStore(href),href,GetDefaultZeroReg));
  1188. end;
  1189. end;
  1190. OS_S16:
  1191. begin
  1192. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  1193. href.addressmode:=AM_POSTINCREMENT;
  1194. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1195. if QuickRef then
  1196. inc(href.offset)
  1197. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  1198. href.addressmode:=AM_POSTINCREMENT
  1199. else
  1200. href.addressmode:=AM_UNCHANGED;
  1201. reg:=GetNextReg(reg);
  1202. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1203. if tcgsize2size[tosize]>2 then
  1204. begin
  1205. tmpreg:=getintregister(list,OS_8);
  1206. emit_mov(list,tmpreg,GetDefaultZeroReg);
  1207. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  1208. list.concat(taicpu.op_reg(A_COM,tmpreg));
  1209. for i:=3 to tcgsize2size[tosize] do
  1210. begin
  1211. if QuickRef then
  1212. inc(href.offset);
  1213. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1214. href.addressmode:=AM_POSTINCREMENT
  1215. else
  1216. href.addressmode:=AM_UNCHANGED;
  1217. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  1218. end;
  1219. end;
  1220. end;
  1221. else
  1222. conv_done:=false;
  1223. end;
  1224. end;
  1225. if not conv_done then
  1226. begin
  1227. { Write to 16 bit ioreg, first high byte then low byte
  1228. sequence required for 16 bit timer registers
  1229. See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
  1230. Avrxmega3: write low byte first then high byte
  1231. See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers }
  1232. if (current_settings.cputype <> cpu_avrxmega3) and
  1233. (fromsize in [OS_16, OS_S16]) and QuickRef and addr_is_io_register(href.offset) then
  1234. begin
  1235. tmpreg:=GetNextReg(reg);
  1236. href.addressmode:=AM_UNCHANGED;
  1237. inc(href.offset);
  1238. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  1239. dec(href.offset);
  1240. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1241. end
  1242. else
  1243. begin
  1244. for i:=1 to tcgsize2size[fromsize] do
  1245. begin
  1246. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1247. href.addressmode:=AM_POSTINCREMENT
  1248. else
  1249. href.addressmode:=AM_UNCHANGED;
  1250. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  1251. if QuickRef then
  1252. inc(href.offset);
  1253. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  1254. if i<tcgsize2size[fromsize] then
  1255. reg:=GetNextReg(reg);
  1256. end;
  1257. end;
  1258. end;
  1259. if not(QuickRef) or ungetcpuregister_z then
  1260. begin
  1261. ungetcpuregister(list,href.base);
  1262. ungetcpuregister(list,GetNextReg(href.base));
  1263. end;
  1264. end;
  1265. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  1266. const Ref : treference;reg : tregister);
  1267. var
  1268. href : treference;
  1269. conv_done: boolean;
  1270. tmpreg : tregister;
  1271. i : integer;
  1272. QuickRef,ungetcpuregister_z: boolean;
  1273. begin
  1274. QuickRef:=false;
  1275. ungetcpuregister_z:=false;
  1276. href:=Ref;
  1277. { ensure, href.base contains a valid register if there is any register used }
  1278. if href.base=NR_NO then
  1279. begin
  1280. href.base:=href.index;
  1281. href.index:=NR_NO;
  1282. end;
  1283. { try to use ldd/lds }
  1284. if not((href.Base=NR_NO) and (href.Index=NR_NO)) then
  1285. begin
  1286. if not((href.addressmode=AM_UNCHANGED) and
  1287. (href.symbol=nil) and
  1288. (href.Index=NR_NO) and
  1289. (href.Offset in [0..64-tcgsize2size[fromsize]])) or
  1290. (CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) then
  1291. begin
  1292. href:=normalize_ref(list,href,NR_R30);
  1293. getcpuregister(list,NR_R30);
  1294. getcpuregister(list,NR_R31);
  1295. ungetcpuregister_z:=true;
  1296. end
  1297. else
  1298. begin
  1299. if (href.base<>NR_R28) and (href.base<>NR_R30) then
  1300. begin
  1301. getcpuregister(list,NR_R30);
  1302. emit_mov(list,NR_R30,href.base);
  1303. getcpuregister(list,NR_R31);
  1304. emit_mov(list,NR_R31,GetNextReg(href.base));
  1305. href.base:=NR_R30;
  1306. ungetcpuregister_z:=true;
  1307. end;
  1308. QuickRef:=true;
  1309. end;
  1310. end
  1311. else
  1312. QuickRef:=true;
  1313. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1314. internalerror(2011021304);
  1315. conv_done:=false;
  1316. if tosize<>fromsize then
  1317. begin
  1318. conv_done:=true;
  1319. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1320. fromsize:=tosize;
  1321. case fromsize of
  1322. OS_8:
  1323. begin
  1324. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1325. for i:=2 to tcgsize2size[tosize] do
  1326. begin
  1327. reg:=GetNextReg(reg);
  1328. emit_mov(list,reg,GetDefaultZeroReg);
  1329. end;
  1330. end;
  1331. OS_S8:
  1332. begin
  1333. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1334. tmpreg:=reg;
  1335. if tcgsize2size[tosize]>1 then
  1336. begin
  1337. reg:=GetNextReg(reg);
  1338. emit_mov(list,reg,GetDefaultZeroReg);
  1339. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1340. list.concat(taicpu.op_reg(A_COM,reg));
  1341. tmpreg:=reg;
  1342. for i:=3 to tcgsize2size[tosize] do
  1343. begin
  1344. reg:=GetNextReg(reg);
  1345. emit_mov(list,reg,tmpreg);
  1346. end;
  1347. end;
  1348. end;
  1349. OS_16:
  1350. begin
  1351. if not(QuickRef) then
  1352. href.addressmode:=AM_POSTINCREMENT;
  1353. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1354. if QuickRef then
  1355. inc(href.offset);
  1356. href.addressmode:=AM_UNCHANGED;
  1357. reg:=GetNextReg(reg);
  1358. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1359. for i:=3 to tcgsize2size[tosize] do
  1360. begin
  1361. reg:=GetNextReg(reg);
  1362. emit_mov(list,reg,GetDefaultZeroReg);
  1363. end;
  1364. end;
  1365. OS_S16:
  1366. begin
  1367. if not(QuickRef) then
  1368. href.addressmode:=AM_POSTINCREMENT;
  1369. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1370. if QuickRef then
  1371. inc(href.offset);
  1372. href.addressmode:=AM_UNCHANGED;
  1373. reg:=GetNextReg(reg);
  1374. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1375. tmpreg:=reg;
  1376. reg:=GetNextReg(reg);
  1377. emit_mov(list,reg,GetDefaultZeroReg);
  1378. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  1379. list.concat(taicpu.op_reg(A_COM,reg));
  1380. tmpreg:=reg;
  1381. for i:=4 to tcgsize2size[tosize] do
  1382. begin
  1383. reg:=GetNextReg(reg);
  1384. emit_mov(list,reg,tmpreg);
  1385. end;
  1386. end;
  1387. else
  1388. conv_done:=false;
  1389. end;
  1390. end;
  1391. if not conv_done then
  1392. begin
  1393. for i:=1 to tcgsize2size[fromsize] do
  1394. begin
  1395. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  1396. href.addressmode:=AM_POSTINCREMENT
  1397. else
  1398. href.addressmode:=AM_UNCHANGED;
  1399. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  1400. if QuickRef then
  1401. inc(href.offset);
  1402. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  1403. if i<tcgsize2size[fromsize] then
  1404. reg:=GetNextReg(reg);
  1405. end;
  1406. end;
  1407. if ungetcpuregister_z then
  1408. begin
  1409. ungetcpuregister(list,href.base);
  1410. ungetcpuregister(list,GetNextReg(href.base));
  1411. end;
  1412. end;
  1413. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  1414. var
  1415. conv_done: boolean;
  1416. tmpreg : tregister;
  1417. i : integer;
  1418. begin
  1419. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  1420. internalerror(2011021310);
  1421. conv_done:=false;
  1422. if tosize<>fromsize then
  1423. begin
  1424. conv_done:=true;
  1425. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  1426. fromsize:=tosize;
  1427. case fromsize of
  1428. OS_8:
  1429. begin
  1430. emit_mov(list,reg2,reg1);
  1431. for i:=2 to tcgsize2size[tosize] do
  1432. begin
  1433. reg2:=GetNextReg(reg2);
  1434. emit_mov(list,reg2,GetDefaultZeroReg);
  1435. end;
  1436. end;
  1437. OS_S8:
  1438. begin
  1439. emit_mov(list,reg2,reg1);
  1440. if tcgsize2size[tosize]>1 then
  1441. begin
  1442. reg2:=GetNextReg(reg2);
  1443. emit_mov(list,reg2,GetDefaultZeroReg);
  1444. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1445. list.concat(taicpu.op_reg(A_COM,reg2));
  1446. tmpreg:=reg2;
  1447. for i:=3 to tcgsize2size[tosize] do
  1448. begin
  1449. reg2:=GetNextReg(reg2);
  1450. emit_mov(list,reg2,tmpreg);
  1451. end;
  1452. end;
  1453. end;
  1454. OS_16:
  1455. begin
  1456. emit_mov(list,reg2,reg1);
  1457. reg1:=GetNextReg(reg1);
  1458. reg2:=GetNextReg(reg2);
  1459. emit_mov(list,reg2,reg1);
  1460. for i:=3 to tcgsize2size[tosize] do
  1461. begin
  1462. reg2:=GetNextReg(reg2);
  1463. emit_mov(list,reg2,GetDefaultZeroReg);
  1464. end;
  1465. end;
  1466. OS_S16:
  1467. begin
  1468. emit_mov(list,reg2,reg1);
  1469. reg1:=GetNextReg(reg1);
  1470. reg2:=GetNextReg(reg2);
  1471. emit_mov(list,reg2,reg1);
  1472. if tcgsize2size[tosize]>2 then
  1473. begin
  1474. reg2:=GetNextReg(reg2);
  1475. emit_mov(list,reg2,GetDefaultZeroReg);
  1476. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  1477. list.concat(taicpu.op_reg(A_COM,reg2));
  1478. tmpreg:=reg2;
  1479. for i:=4 to tcgsize2size[tosize] do
  1480. begin
  1481. reg2:=GetNextReg(reg2);
  1482. emit_mov(list,reg2,tmpreg);
  1483. end;
  1484. end;
  1485. end;
  1486. else
  1487. conv_done:=false;
  1488. end;
  1489. end;
  1490. if not conv_done and (reg1<>reg2) then
  1491. begin
  1492. for i:=1 to tcgsize2size[fromsize] do
  1493. begin
  1494. emit_mov(list,reg2,reg1);
  1495. { check if we are not in the last iteration to avoid an internalerror in GetNextReg }
  1496. if i<tcgsize2size[fromsize] then
  1497. begin
  1498. reg1:=GetNextReg(reg1);
  1499. reg2:=GetNextReg(reg2);
  1500. end;
  1501. end;
  1502. end;
  1503. end;
  1504. procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
  1505. begin
  1506. internalerror(2012010702);
  1507. end;
  1508. procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
  1509. begin
  1510. internalerror(2012010703);
  1511. end;
  1512. procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
  1513. begin
  1514. internalerror(2012010704);
  1515. end;
  1516. { comparison operations }
  1517. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  1518. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  1519. var
  1520. swapped : boolean;
  1521. i : byte;
  1522. begin
  1523. if a=0 then
  1524. begin
  1525. swapped:=false;
  1526. { swap parameters? }
  1527. case cmp_op of
  1528. OC_GT:
  1529. begin
  1530. swapped:=true;
  1531. cmp_op:=OC_LT;
  1532. end;
  1533. OC_LTE:
  1534. begin
  1535. swapped:=true;
  1536. cmp_op:=OC_GTE;
  1537. end;
  1538. OC_BE:
  1539. begin
  1540. swapped:=true;
  1541. cmp_op:=OC_AE;
  1542. end;
  1543. OC_A:
  1544. begin
  1545. swapped:=true;
  1546. cmp_op:=OC_B;
  1547. end;
  1548. end;
  1549. { If doing a signed test for x<0, we can simply test the sign bit
  1550. of the most significant byte }
  1551. if (cmp_op in [OC_LT,OC_GTE]) and
  1552. (not swapped) then
  1553. begin
  1554. for i:=2 to tcgsize2size[size] do
  1555. reg:=GetNextReg(reg);
  1556. list.concat(taicpu.op_reg_reg(A_CP,reg,GetDefaultZeroReg));
  1557. end
  1558. else
  1559. begin
  1560. if swapped then
  1561. list.concat(taicpu.op_reg_reg(A_CP,GetDefaultZeroReg,reg))
  1562. else
  1563. list.concat(taicpu.op_reg_reg(A_CP,reg,GetDefaultZeroReg));
  1564. for i:=2 to tcgsize2size[size] do
  1565. begin
  1566. reg:=GetNextReg(reg);
  1567. if swapped then
  1568. list.concat(taicpu.op_reg_reg(A_CPC,GetDefaultZeroReg,reg))
  1569. else
  1570. list.concat(taicpu.op_reg_reg(A_CPC,reg,GetDefaultZeroReg));
  1571. end;
  1572. end;
  1573. a_jmp_cond(list,cmp_op,l);
  1574. end
  1575. else
  1576. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1577. end;
  1578. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1579. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1580. var
  1581. swapped : boolean;
  1582. tmpreg : tregister;
  1583. i : byte;
  1584. begin
  1585. swapped:=false;
  1586. { swap parameters? }
  1587. case cmp_op of
  1588. OC_GT:
  1589. begin
  1590. swapped:=true;
  1591. cmp_op:=OC_LT;
  1592. end;
  1593. OC_LTE:
  1594. begin
  1595. swapped:=true;
  1596. cmp_op:=OC_GTE;
  1597. end;
  1598. OC_BE:
  1599. begin
  1600. swapped:=true;
  1601. cmp_op:=OC_AE;
  1602. end;
  1603. OC_A:
  1604. begin
  1605. swapped:=true;
  1606. cmp_op:=OC_B;
  1607. end;
  1608. end;
  1609. if swapped then
  1610. begin
  1611. tmpreg:=reg1;
  1612. reg1:=reg2;
  1613. reg2:=tmpreg;
  1614. end;
  1615. list.concat(taicpu.op_reg_reg(A_CP,reg2,reg1));
  1616. for i:=2 to tcgsize2size[size] do
  1617. begin
  1618. reg1:=GetNextReg(reg1);
  1619. reg2:=GetNextReg(reg2);
  1620. list.concat(taicpu.op_reg_reg(A_CPC,reg2,reg1));
  1621. end;
  1622. a_jmp_cond(list,cmp_op,l);
  1623. end;
  1624. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1625. var
  1626. ai : taicpu;
  1627. begin
  1628. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1629. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s,AT_FUNCTION))
  1630. else
  1631. ai:=taicpu.op_sym(A_RJMP,current_asmdata.RefAsmSymbol(s,AT_FUNCTION));
  1632. ai.is_jmp:=true;
  1633. list.concat(ai);
  1634. end;
  1635. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1636. var
  1637. ai : taicpu;
  1638. begin
  1639. if CPUAVR_HAS_JMP_CALL in cpu_capabilities[current_settings.cputype] then
  1640. ai:=taicpu.op_sym(A_JMP,l)
  1641. else
  1642. ai:=taicpu.op_sym(A_RJMP,l);
  1643. ai.is_jmp:=true;
  1644. list.concat(ai);
  1645. end;
  1646. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1647. var
  1648. ai : taicpu;
  1649. begin
  1650. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1651. ai.is_jmp:=true;
  1652. list.concat(ai);
  1653. end;
  1654. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1655. var
  1656. l : TAsmLabel;
  1657. //tmpflags : TResFlags;
  1658. i: Integer;
  1659. hreg: TRegister;
  1660. begin
  1661. current_asmdata.getjumplabel(l);
  1662. {
  1663. if flags_to_cond(f) then
  1664. begin
  1665. tmpflags:=f;
  1666. inverse_flags(tmpflags);
  1667. emit_mov(reg,GetDefaultZeroReg);
  1668. a_jmp_flags(list,tmpflags,l);
  1669. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1670. end
  1671. else
  1672. }
  1673. begin
  1674. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1675. hreg:=reg;
  1676. for i:=2 to tcgsize2size[size] do
  1677. begin
  1678. hreg:=GetNextReg(hreg);
  1679. emit_mov(list,hreg,GetDefaultZeroReg);
  1680. end;
  1681. a_jmp_flags(list,f,l);
  1682. emit_mov(list,reg,GetDefaultZeroReg);
  1683. end;
  1684. cg.a_label(list,l);
  1685. end;
  1686. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1687. {var
  1688. i : integer; }
  1689. begin
  1690. case value of
  1691. 0:
  1692. ;
  1693. {-14..-1:
  1694. begin
  1695. if ((-value) mod 2)<>0 then
  1696. list.concat(taicpu.op_reg(A_PUSH,GetDefaultTmpReg));
  1697. for i:=1 to (-value) div 2 do
  1698. list.concat(taicpu.op_const(A_RCALL,0));
  1699. end;
  1700. 1..7:
  1701. begin
  1702. for i:=1 to value do
  1703. list.concat(taicpu.op_reg(A_POP,GetDefaultTmpReg));
  1704. end;}
  1705. else
  1706. begin
  1707. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1708. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1709. // get SREG
  1710. list.concat(taicpu.op_reg_const(A_IN,GetDefaultTmpReg,NIO_SREG));
  1711. // block interrupts
  1712. list.concat(taicpu.op_none(A_CLI));
  1713. // write high SP
  1714. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1715. // release interrupts
  1716. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,GetDefaultTmpReg));
  1717. // write low SP
  1718. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1719. end;
  1720. end;
  1721. end;
  1722. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1723. begin
  1724. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1725. result:=A_LDS
  1726. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1727. result:=A_LDD
  1728. else
  1729. result:=A_LD;
  1730. end;
  1731. function tcgavr.GetStore(const ref: treference) : tasmop;
  1732. begin
  1733. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1734. result:=A_STS
  1735. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1736. result:=A_STD
  1737. else
  1738. result:=A_ST;
  1739. end;
  1740. procedure tcgavr.gen_multiply(list: TAsmList; op: topcg; size: TCgSize; src2, src1, dst: tregister; check_overflow: boolean; var ovloc: tlocation);
  1741. procedure perform_r1_check(overflow_label: TAsmLabel; other_reg: TRegister=NR_R1);
  1742. var
  1743. ai: taicpu;
  1744. begin
  1745. if check_overflow then
  1746. begin
  1747. list.concat(taicpu.op_reg_reg(A_OR,NR_R1,other_reg));
  1748. ai:=Taicpu.Op_Sym(A_BRxx,overflow_label);
  1749. ai.SetCondition(C_NE);
  1750. ai.is_jmp:=true;
  1751. list.concat(ai);
  1752. end;
  1753. end;
  1754. procedure perform_ovf_check(overflow_label: TAsmLabel);
  1755. var
  1756. ai: taicpu;
  1757. begin
  1758. if check_overflow then
  1759. begin
  1760. ai:=Taicpu.Op_Sym(A_BRxx,overflow_label);
  1761. ai.SetCondition(C_CS);
  1762. ai.is_jmp:=true;
  1763. list.concat(ai);
  1764. end;
  1765. end;
  1766. var
  1767. pd: tprocdef;
  1768. paraloc1, paraloc2: tcgpara;
  1769. ai: taicpu;
  1770. hl, no_overflow: TAsmLabel;
  1771. name: String;
  1772. begin
  1773. ovloc.loc:=LOC_VOID;
  1774. if size in [OS_8,OS_S8] then
  1775. begin
  1776. if (CPUAVR_HAS_MUL in cpu_capabilities[current_settings.cputype]) and
  1777. (op=OP_MUL) then
  1778. begin
  1779. cg.a_reg_alloc(list,NR_R0);
  1780. cg.a_reg_alloc(list,NR_R1);
  1781. list.concat(taicpu.op_reg_reg(topcg2asmop[op],src1,src2));
  1782. // Check overflow
  1783. if check_overflow then
  1784. begin
  1785. current_asmdata.getjumplabel(hl);
  1786. list.concat(taicpu.op_reg_reg(A_AND,NR_R1,NR_R1));
  1787. { Clear carry as it's not affected by any of the instructions }
  1788. list.concat(taicpu.op_none(A_CLC));
  1789. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1790. ai.SetCondition(C_EQ);
  1791. ai.is_jmp:=true;
  1792. list.concat(ai);
  1793. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1794. list.concat(taicpu.op_none(A_SEC));
  1795. a_label(list,hl);
  1796. ovloc.loc:=LOC_FLAGS;
  1797. end
  1798. else
  1799. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1800. cg.a_reg_dealloc(list,NR_R1);
  1801. list.concat(taicpu.op_reg_reg(A_MOV,dst,NR_R0));
  1802. cg.a_reg_dealloc(list,NR_R0);
  1803. end
  1804. else if (CPUAVR_HAS_MUL in cpu_capabilities[current_settings.cputype]) and
  1805. (op=OP_IMUL) then
  1806. begin
  1807. cg.a_reg_alloc(list,NR_R0);
  1808. cg.a_reg_alloc(list,NR_R1);
  1809. list.concat(taicpu.op_reg_reg(A_MULS,src1,src2));
  1810. list.concat(taicpu.op_reg_reg(A_MOV,dst,NR_R0));
  1811. // Check overflow
  1812. if check_overflow then
  1813. begin
  1814. current_asmdata.getjumplabel(no_overflow);
  1815. list.concat(taicpu.op_reg_const(A_SBRC,NR_R0,7));
  1816. list.concat(taicpu.op_reg(A_INC,NR_R1));
  1817. list.concat(taicpu.op_reg(A_TST,NR_R1));
  1818. ai:=Taicpu.Op_Sym(A_BRxx,no_overflow);
  1819. ai.SetCondition(C_EQ);
  1820. ai.is_jmp:=true;
  1821. list.concat(ai);
  1822. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1823. a_call_name(list,'FPC_OVERFLOW',false);
  1824. a_label(list,no_overflow);
  1825. ovloc.loc:=LOC_VOID;
  1826. end
  1827. else
  1828. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1829. cg.a_reg_dealloc(list,NR_R1);
  1830. cg.a_reg_dealloc(list,NR_R0);
  1831. end
  1832. else
  1833. begin
  1834. if size=OS_8 then
  1835. name:='fpc_mul_byte'
  1836. else
  1837. name:='fpc_mul_shortint';
  1838. if check_overflow then
  1839. name:=name+'_checkoverflow';
  1840. pd:=search_system_proc(name);
  1841. paraloc1.init;
  1842. paraloc2.init;
  1843. paramanager.getcgtempparaloc(list,pd,1,paraloc1);
  1844. paramanager.getcgtempparaloc(list,pd,2,paraloc2);
  1845. a_load_reg_cgpara(list,OS_8,src1,paraloc2);
  1846. a_load_reg_cgpara(list,OS_8,src2,paraloc1);
  1847. paramanager.freecgpara(list,paraloc2);
  1848. paramanager.freecgpara(list,paraloc1);
  1849. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1850. a_call_name(list,upper(name),false);
  1851. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1852. cg.a_reg_alloc(list,NR_R24);
  1853. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R24,dst);
  1854. cg.a_reg_dealloc(list,NR_R24);
  1855. paraloc2.done;
  1856. paraloc1.done;
  1857. end;
  1858. end
  1859. else if size in [OS_16,OS_S16] then
  1860. begin
  1861. if (CPUAVR_HAS_MUL in cpu_capabilities[current_settings.cputype]) and
  1862. ((not check_overflow) or
  1863. (size=OS_16)) then
  1864. begin
  1865. if check_overflow then
  1866. begin
  1867. current_asmdata.getjumplabel(hl);
  1868. current_asmdata.getjumplabel(no_overflow);
  1869. end;
  1870. cg.a_reg_alloc(list,NR_R0);
  1871. cg.a_reg_alloc(list,NR_R1);
  1872. list.concat(taicpu.op_reg_reg(A_MUL,src2,src1));
  1873. emit_mov(list,dst,NR_R0);
  1874. emit_mov(list,GetNextReg(dst),NR_R1);
  1875. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(src1),src2));
  1876. perform_r1_check(hl);
  1877. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  1878. perform_ovf_check(hl);
  1879. list.concat(taicpu.op_reg_reg(A_MUL,src1,GetNextReg(src2)));
  1880. perform_r1_check(hl);
  1881. list.concat(taicpu.op_reg_reg(A_ADD,GetNextReg(dst),NR_R0));
  1882. perform_ovf_check(hl);
  1883. if check_overflow then
  1884. begin
  1885. list.concat(taicpu.op_reg_reg(A_MUL,GetNextReg(src1),GetNextReg(src2)));
  1886. perform_r1_check(hl,NR_R0);
  1887. end;
  1888. cg.a_reg_dealloc(list,NR_R0);
  1889. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1890. if check_overflow then
  1891. begin
  1892. {
  1893. CLV/CLC
  1894. JMP no_overflow
  1895. .hl:
  1896. CLR R1
  1897. SEV/SEC
  1898. .no_overflow:
  1899. }
  1900. if op=OP_MUL then
  1901. list.concat(taicpu.op_none(A_CLC))
  1902. else
  1903. list.concat(taicpu.op_none(A_CLV));
  1904. a_jmp_always(list,no_overflow);
  1905. a_label(list,hl);
  1906. list.concat(taicpu.op_reg(A_CLR,NR_R1));
  1907. if op=OP_MUL then
  1908. list.concat(taicpu.op_none(A_SEC))
  1909. else
  1910. list.concat(taicpu.op_none(A_SEV));
  1911. a_label(list,no_overflow);
  1912. ovloc.loc:=LOC_FLAGS;
  1913. end;
  1914. cg.a_reg_dealloc(list,NR_R1);
  1915. end
  1916. else
  1917. begin
  1918. if size=OS_16 then
  1919. name:='fpc_mul_word'
  1920. else
  1921. name:='fpc_mul_integer';
  1922. if check_overflow then
  1923. name:=name+'_checkoverflow';
  1924. pd:=search_system_proc(name);
  1925. paraloc1.init;
  1926. paraloc2.init;
  1927. paramanager.getcgtempparaloc(list,pd,1,paraloc1);
  1928. paramanager.getcgtempparaloc(list,pd,2,paraloc2);
  1929. a_load_reg_cgpara(list,OS_16,src1,paraloc2);
  1930. a_load_reg_cgpara(list,OS_16,src2,paraloc1);
  1931. paramanager.freecgpara(list,paraloc2);
  1932. paramanager.freecgpara(list,paraloc1);
  1933. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1934. a_call_name(list,upper(name),false);
  1935. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1936. cg.a_reg_alloc(list,NR_R24);
  1937. cg.a_reg_alloc(list,NR_R25);
  1938. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R24,dst);
  1939. cg.a_reg_dealloc(list,NR_R24);
  1940. cg.a_load_reg_reg(list,OS_8,OS_8,NR_R25,GetNextReg(dst));
  1941. cg.a_reg_dealloc(list,NR_R25);
  1942. paraloc2.done;
  1943. paraloc1.done;
  1944. end;
  1945. end
  1946. else
  1947. internalerror(2011022002);
  1948. end;
  1949. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1950. var
  1951. regs : tcpuregisterset;
  1952. reg : tsuperregister;
  1953. begin
  1954. if current_procinfo.procdef.isempty then
  1955. exit;
  1956. if (po_interrupt in current_procinfo.procdef.procoptions) and
  1957. (not nostackframe) then
  1958. begin
  1959. { check if the framepointer is actually used, this is done here because
  1960. we have to know the size of the locals (must be 0), avr does not know
  1961. an sp based stack }
  1962. if not(current_procinfo.procdef.stack_tainting_parameter(calleeside)) and
  1963. (localsize=0) then
  1964. current_procinfo.framepointer:=NR_NO;
  1965. { save int registers,
  1966. but only if the procedure returns }
  1967. if not(po_noreturn in current_procinfo.procdef.procoptions) then
  1968. regs:=rg[R_INTREGISTER].used_in_proc
  1969. else
  1970. regs:=[];
  1971. { if the framepointer is potentially used, save it always because we need a proper stack frame,
  1972. even if the procedure never returns, the procedure could be e.g. a nested one accessing
  1973. an outer stackframe }
  1974. if current_procinfo.framepointer<>NR_NO then
  1975. regs:=regs+[RS_R28,RS_R29];
  1976. { we clear r1 }
  1977. include(regs,getsupreg(GetDefaultZeroReg));
  1978. regs:=regs+[getsupreg(GetDefaultTmpReg)];
  1979. if current_settings.cputype=cpu_avr1 then
  1980. message1(cg_w_interrupt_does_not_save_registers,current_procinfo.procdef.fullprocname(false))
  1981. else
  1982. begin
  1983. for reg:=RS_R31 downto RS_R0 do
  1984. if reg in regs then
  1985. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1986. { Save SREG }
  1987. cg.getcpuregister(list,GetDefaultTmpReg);
  1988. list.concat(taicpu.op_reg_const(A_IN, GetDefaultTmpReg, $3F));
  1989. list.concat(taicpu.op_reg(A_PUSH, GetDefaultTmpReg));
  1990. cg.ungetcpuregister(list,GetDefaultTmpReg);
  1991. end;
  1992. list.concat(taicpu.op_reg(A_CLR,GetDefaultZeroReg));
  1993. if current_procinfo.framepointer<>NR_NO then
  1994. begin
  1995. cg.getcpuregister(list,NR_R28);
  1996. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1997. cg.getcpuregister(list,NR_R29);
  1998. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1999. a_adjust_sp(list,-localsize);
  2000. end;
  2001. end
  2002. else if not(nostackframe) then
  2003. begin
  2004. { check if the framepointer is actually used, this is done here because
  2005. we have to know the size of the locals (must be 0), avr does not know
  2006. an sp based stack }
  2007. if not(current_procinfo.procdef.stack_tainting_parameter(calleeside)) and
  2008. (localsize=0) then
  2009. current_procinfo.framepointer:=NR_NO;
  2010. { save int registers,
  2011. but only if the procedure returns }
  2012. if not(po_noreturn in current_procinfo.procdef.procoptions) then
  2013. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall)
  2014. else
  2015. regs:=[];
  2016. { if the framepointer is potentially used, save it always because we need a proper stack frame,
  2017. even if the procedure never returns, the procedure could be e.g. a nested one accessing
  2018. an outer stackframe }
  2019. if current_procinfo.framepointer<>NR_NO then
  2020. regs:=regs+[RS_R28,RS_R29];
  2021. for reg:=RS_R31 downto RS_R0 do
  2022. if reg in regs then
  2023. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  2024. if current_procinfo.framepointer<>NR_NO then
  2025. begin
  2026. cg.getcpuregister(list,NR_R28);
  2027. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  2028. cg.getcpuregister(list,NR_R29);
  2029. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  2030. a_adjust_sp(list,-localsize);
  2031. end;
  2032. end;
  2033. end;
  2034. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  2035. var
  2036. regs : tcpuregisterset;
  2037. reg : TSuperRegister;
  2038. LocalSize : longint;
  2039. begin
  2040. { every byte counts for avr, so if a subroutine is marked as non-returning, we do
  2041. not generate any exit code, so we really trust the noreturn directive
  2042. }
  2043. if po_noreturn in current_procinfo.procdef.procoptions then
  2044. exit;
  2045. if po_interrupt in current_procinfo.procdef.procoptions then
  2046. begin
  2047. if not(current_procinfo.procdef.isempty) and
  2048. (not nostackframe) then
  2049. begin
  2050. regs:=rg[R_INTREGISTER].used_in_proc;
  2051. if current_procinfo.framepointer<>NR_NO then
  2052. begin
  2053. regs:=regs+[RS_R28,RS_R29];
  2054. LocalSize:=current_procinfo.calc_stackframe_size;
  2055. a_adjust_sp(list,LocalSize);
  2056. end;
  2057. { we clear r1 }
  2058. include(regs,getsupreg(GetDefaultZeroReg));
  2059. if current_settings.cputype<>cpu_avr1 then
  2060. begin
  2061. { Reload SREG }
  2062. regs:=regs+[getsupreg(GetDefaultTmpReg)];
  2063. cg.getcpuregister(list,GetDefaultTmpReg);
  2064. list.concat(taicpu.op_reg(A_POP, GetDefaultTmpReg));
  2065. list.concat(taicpu.op_const_reg(A_OUT, $3F, GetDefaultTmpReg));
  2066. cg.ungetcpuregister(list,GetDefaultTmpReg);
  2067. for reg:=RS_R0 to RS_R31 do
  2068. if reg in regs then
  2069. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  2070. end;
  2071. end;
  2072. list.concat(taicpu.op_none(A_RETI));
  2073. end
  2074. else if not(nostackframe) and not(current_procinfo.procdef.isempty) then
  2075. begin
  2076. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  2077. if current_procinfo.framepointer<>NR_NO then
  2078. begin
  2079. regs:=regs+[RS_R28,RS_R29];
  2080. LocalSize:=current_procinfo.calc_stackframe_size;
  2081. a_adjust_sp(list,LocalSize);
  2082. end;
  2083. for reg:=RS_R0 to RS_R31 do
  2084. if reg in regs then
  2085. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  2086. list.concat(taicpu.op_none(A_RET));
  2087. end
  2088. else
  2089. list.concat(taicpu.op_none(A_RET));
  2090. end;
  2091. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  2092. var
  2093. tmpref : treference;
  2094. begin
  2095. if ref.addressmode<>AM_UNCHANGED then
  2096. internalerror(2011021706);
  2097. if assigned(ref.symbol) or (ref.offset<>0) or
  2098. { If no other reference information it must imply an absolute reference to address 0 }
  2099. ((ref.index=NR_NO) and (ref.base=NR_NO)) then
  2100. begin
  2101. reference_reset(tmpref,0,[]);
  2102. tmpref.symbol:=ref.symbol;
  2103. tmpref.offset:=ref.offset;
  2104. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  2105. tmpref.refaddr:=addr_lo8_gs
  2106. else
  2107. tmpref.refaddr:=addr_lo8;
  2108. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  2109. if assigned(ref.symbol) and (ref.symbol.typ in [AT_FUNCTION,AT_LABEL]) then
  2110. tmpref.refaddr:=addr_hi8_gs
  2111. else
  2112. tmpref.refaddr:=addr_hi8;
  2113. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  2114. if (ref.base<>NR_NO) then
  2115. begin
  2116. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  2117. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  2118. end;
  2119. if (ref.index<>NR_NO) then
  2120. begin
  2121. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  2122. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  2123. end;
  2124. end
  2125. else if (ref.base<>NR_NO)then
  2126. begin
  2127. emit_mov(list,r,ref.base);
  2128. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  2129. if (ref.index<>NR_NO) then
  2130. begin
  2131. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  2132. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  2133. end;
  2134. end
  2135. else if (ref.index<>NR_NO) then
  2136. begin
  2137. emit_mov(list,r,ref.index);
  2138. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  2139. end;
  2140. end;
  2141. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  2142. begin
  2143. internalerror(2011021320);
  2144. end;
  2145. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  2146. var
  2147. paraloc1,paraloc2,paraloc3 : TCGPara;
  2148. pd : tprocdef;
  2149. begin
  2150. pd:=search_system_proc('MOVE');
  2151. paraloc1.init;
  2152. paraloc2.init;
  2153. paraloc3.init;
  2154. paramanager.getcgtempparaloc(list,pd,1,paraloc1);
  2155. paramanager.getcgtempparaloc(list,pd,2,paraloc2);
  2156. paramanager.getcgtempparaloc(list,pd,3,paraloc3);
  2157. a_load_const_cgpara(list,OS_SINT,len,paraloc3);
  2158. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  2159. a_loadaddr_ref_cgpara(list,source,paraloc1);
  2160. paramanager.freecgpara(list,paraloc3);
  2161. paramanager.freecgpara(list,paraloc2);
  2162. paramanager.freecgpara(list,paraloc1);
  2163. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  2164. a_call_name_static(list,'FPC_MOVE');
  2165. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  2166. paraloc3.done;
  2167. paraloc2.done;
  2168. paraloc1.done;
  2169. end;
  2170. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  2171. var
  2172. countreg,tmpreg,tmpreg2: tregister;
  2173. srcref,dstref : treference;
  2174. countregsize : tcgsize;
  2175. l : TAsmLabel;
  2176. i : longint;
  2177. SrcQuickRef, DestQuickRef : Boolean;
  2178. begin
  2179. if len>16 then
  2180. begin
  2181. current_asmdata.getjumplabel(l);
  2182. reference_reset(srcref,source.alignment,source.volatility);
  2183. reference_reset(dstref,dest.alignment,source.volatility);
  2184. srcref.base:=NR_R30;
  2185. srcref.addressmode:=AM_POSTINCREMENT;
  2186. dstref.base:=NR_R26;
  2187. dstref.addressmode:=AM_POSTINCREMENT;
  2188. if len<256 then
  2189. countregsize:=OS_8
  2190. else if len<65536 then
  2191. countregsize:=OS_16
  2192. else
  2193. internalerror(2011022007);
  2194. countreg:=getintregister(list,countregsize);
  2195. a_load_const_reg(list,countregsize,len,countreg);
  2196. cg.getcpuregister(list,NR_R30);
  2197. cg.getcpuregister(list,NR_R31);
  2198. a_loadaddr_ref_reg(list,source,NR_R30);
  2199. { only base or index register in dest? }
  2200. if ((dest.addressmode=AM_UNCHANGED) and (dest.offset=0) and not(assigned(dest.symbol))) and
  2201. ((dest.base<>NR_NO) xor (dest.index<>NR_NO)) then
  2202. begin
  2203. if dest.base<>NR_NO then
  2204. tmpreg:=dest.base
  2205. else if dest.index<>NR_NO then
  2206. tmpreg:=dest.index
  2207. else
  2208. internalerror(2016112001);
  2209. end
  2210. else
  2211. begin
  2212. tmpreg:=getaddressregister(list);
  2213. a_loadaddr_ref_reg(list,dest,tmpreg);
  2214. end;
  2215. { X is used for spilling code so we can load it
  2216. only by a push/pop sequence, this can be
  2217. optimized later on by the peephole optimizer
  2218. }
  2219. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  2220. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  2221. cg.getcpuregister(list,NR_R27);
  2222. list.concat(taicpu.op_reg(A_POP,NR_R27));
  2223. cg.getcpuregister(list,NR_R26);
  2224. list.concat(taicpu.op_reg(A_POP,NR_R26));
  2225. cg.a_label(list,l);
  2226. cg.getcpuregister(list,GetDefaultTmpReg);
  2227. list.concat(taicpu.op_reg_ref(GetLoad(srcref),GetDefaultTmpReg,srcref));
  2228. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,GetDefaultTmpReg));
  2229. cg.ungetcpuregister(list,GetDefaultTmpReg);
  2230. if tcgsize2size[countregsize] = 1 then
  2231. list.concat(taicpu.op_reg(A_DEC,countreg))
  2232. else
  2233. begin
  2234. list.concat(taicpu.op_reg_const(A_SUBI,countreg,1));
  2235. list.concat(taicpu.op_reg_reg(A_SBC,GetNextReg(countreg),GetDefaultZeroReg));
  2236. end;
  2237. a_jmp_flags(list,F_NE,l);
  2238. cg.ungetcpuregister(list,NR_R26);
  2239. cg.ungetcpuregister(list,NR_R27);
  2240. cg.ungetcpuregister(list,NR_R30);
  2241. cg.ungetcpuregister(list,NR_R31);
  2242. { keep registers alive }
  2243. a_reg_sync(list,countreg);
  2244. end
  2245. else
  2246. begin
  2247. SrcQuickRef:=false;
  2248. DestQuickRef:=false;
  2249. if ((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) and
  2250. not((source.Base=NR_NO) and (source.Index=NR_NO) and (source.Offset in [0..192-len]))) or
  2251. (
  2252. not((source.addressmode=AM_UNCHANGED) and
  2253. (source.symbol=nil) and
  2254. ((source.base=NR_R28) or
  2255. (source.base=NR_R30)) and
  2256. (source.Index=NR_NO) and
  2257. (source.Offset in [0..64-len])) and
  2258. not((source.Base=NR_NO) and (source.Index=NR_NO))
  2259. ) then
  2260. begin
  2261. cg.getcpuregister(list,NR_R30);
  2262. cg.getcpuregister(list,NR_R31);
  2263. srcref:=normalize_ref(list,source,NR_R30);
  2264. end
  2265. else
  2266. begin
  2267. SrcQuickRef:=true;
  2268. srcref:=source;
  2269. end;
  2270. if ((CPUAVR_16_REGS in cpu_capabilities[current_settings.cputype]) and
  2271. not((dest.Base=NR_NO) and (dest.Index=NR_NO) and (dest.Offset in [0..192-len]))) or
  2272. (
  2273. not((dest.addressmode=AM_UNCHANGED) and
  2274. (dest.symbol=nil) and
  2275. ((dest.base=NR_R28) or
  2276. (dest.base=NR_R30)) and
  2277. (dest.Index=NR_No) and
  2278. (dest.Offset in [0..64-len])) and
  2279. not((dest.Base=NR_NO) and (dest.Index=NR_NO))
  2280. ) then
  2281. begin
  2282. if not(SrcQuickRef) then
  2283. begin
  2284. { only base or index register in dest? }
  2285. if ((dest.addressmode=AM_UNCHANGED) and (dest.offset=0) and not(assigned(dest.symbol))) and
  2286. ((dest.base<>NR_NO) xor (dest.index<>NR_NO)) then
  2287. begin
  2288. if dest.base<>NR_NO then
  2289. tmpreg:=dest.base
  2290. else if dest.index<>NR_NO then
  2291. tmpreg:=dest.index
  2292. else
  2293. internalerror(2016112002);
  2294. end
  2295. else
  2296. tmpreg:=getaddressregister(list);
  2297. dstref:=normalize_ref(list,dest,tmpreg);
  2298. { X is used for spilling code so we can load it
  2299. only by a push/pop sequence, this can be
  2300. optimized later on by the peephole optimizer
  2301. }
  2302. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  2303. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  2304. cg.getcpuregister(list,NR_R27);
  2305. list.concat(taicpu.op_reg(A_POP,NR_R27));
  2306. cg.getcpuregister(list,NR_R26);
  2307. list.concat(taicpu.op_reg(A_POP,NR_R26));
  2308. dstref.base:=NR_R26;
  2309. end
  2310. else
  2311. begin
  2312. cg.getcpuregister(list,NR_R30);
  2313. cg.getcpuregister(list,NR_R31);
  2314. dstref:=normalize_ref(list,dest,NR_R30);
  2315. end;
  2316. end
  2317. else
  2318. begin
  2319. DestQuickRef:=true;
  2320. dstref:=dest;
  2321. end;
  2322. { If dest is an ioreg and size = 16 bit then
  2323. write high byte first, then low byte
  2324. but not for avrxmega3 }
  2325. if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
  2326. addr_is_io_register(dest.offset) then
  2327. begin
  2328. // If src is also a 16 bit ioreg then read low byte then high byte
  2329. if SrcQuickRef and addr_is_io_register(srcref.offset) then
  2330. begin
  2331. // First read source into temp registers
  2332. tmpreg:=getintregister(list, OS_16);
  2333. list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
  2334. inc(srcref.offset);
  2335. tmpreg2:=GetNextReg(tmpreg);
  2336. list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
  2337. // then move temp registers to dest in reverse order
  2338. inc(dstref.offset);
  2339. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,tmpreg2));
  2340. dec(dstref.offset);
  2341. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,tmpreg));
  2342. end
  2343. else
  2344. begin
  2345. { avrtiny doesn't have LDD instruction, so use
  2346. predecrement version of LD with pre-incremented pointer }
  2347. if current_settings.cputype = cpu_avrtiny then
  2348. begin
  2349. srcref.addressmode:=AM_PREDECREMENT;
  2350. list.concat(taicpu.op_reg_const(A_SUBI,srcref.base,-2));
  2351. list.concat(taicpu.op_reg_const(A_SBCI,GetNextReg(srcref.base),$FF));
  2352. end
  2353. else
  2354. begin
  2355. srcref.addressmode:=AM_UNCHANGED;
  2356. inc(srcref.offset);
  2357. end;
  2358. dstref.addressmode:=AM_UNCHANGED;
  2359. inc(dstref.offset);
  2360. cg.getcpuregister(list,GetDefaultTmpReg);
  2361. list.concat(taicpu.op_reg_ref(GetLoad(srcref),GetDefaultTmpReg,srcref));
  2362. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,GetDefaultTmpReg));
  2363. cg.ungetcpuregister(list,GetDefaultTmpReg);
  2364. if not(SrcQuickRef) and (current_settings.cputype <> cpu_avrtiny) then
  2365. srcref.addressmode:=AM_POSTINCREMENT
  2366. else if current_settings.cputype = cpu_avrtiny then
  2367. srcref.addressmode:=AM_PREDECREMENT
  2368. else
  2369. srcref.addressmode:=AM_UNCHANGED;
  2370. if current_settings.cputype <> cpu_avrtiny then
  2371. dec(srcref.offset);
  2372. dec(dstref.offset);
  2373. cg.getcpuregister(list,GetDefaultTmpReg);
  2374. list.concat(taicpu.op_reg_ref(GetLoad(srcref),GetDefaultTmpReg,srcref));
  2375. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,GetDefaultTmpReg));
  2376. cg.ungetcpuregister(list,GetDefaultTmpReg);
  2377. end;
  2378. end
  2379. else
  2380. for i:=1 to len do
  2381. begin
  2382. if not(SrcQuickRef) and (i<len) then
  2383. srcref.addressmode:=AM_POSTINCREMENT
  2384. else
  2385. srcref.addressmode:=AM_UNCHANGED;
  2386. if not(DestQuickRef) and (i<len) then
  2387. dstref.addressmode:=AM_POSTINCREMENT
  2388. else
  2389. dstref.addressmode:=AM_UNCHANGED;
  2390. cg.getcpuregister(list,GetDefaultTmpReg);
  2391. list.concat(taicpu.op_reg_ref(GetLoad(srcref),GetDefaultTmpReg,srcref));
  2392. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,GetDefaultTmpReg));
  2393. cg.ungetcpuregister(list,GetDefaultTmpReg);
  2394. if SrcQuickRef then
  2395. inc(srcref.offset);
  2396. if DestQuickRef then
  2397. inc(dstref.offset);
  2398. end;
  2399. if not(SrcQuickRef) then
  2400. begin
  2401. ungetcpuregister(list,srcref.base);
  2402. ungetcpuregister(list,TRegister(ord(srcref.base)+1));
  2403. end;
  2404. if not(DestQuickRef) then
  2405. begin
  2406. ungetcpuregister(list,dstref.base);
  2407. ungetcpuregister(list,TRegister(ord(dstref.base)+1));
  2408. end;
  2409. end;
  2410. end;
  2411. procedure tcgavr.g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef);
  2412. var
  2413. hl : tasmlabel;
  2414. ai : taicpu;
  2415. cond : TAsmCond;
  2416. begin
  2417. if not(cs_check_overflow in current_settings.localswitches) then
  2418. exit;
  2419. current_asmdata.getjumplabel(hl);
  2420. if not ((def.typ=pointerdef) or
  2421. ((def.typ=orddef) and
  2422. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  2423. pasbool1,pasbool8,pasbool16,pasbool32,pasbool64]))) then
  2424. cond:=C_VC
  2425. else
  2426. cond:=C_CC;
  2427. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  2428. ai.SetCondition(cond);
  2429. ai.is_jmp:=true;
  2430. list.concat(ai);
  2431. a_call_name(list,'FPC_OVERFLOW',false);
  2432. a_label(list,hl);
  2433. end;
  2434. procedure tcgavr.g_overflowCheck_loc(List: TAsmList; const Loc: TLocation; def: TDef; ovloc: tlocation);
  2435. var
  2436. hl : tasmlabel;
  2437. ai : taicpu;
  2438. cond : TAsmCond;
  2439. begin
  2440. if not(cs_check_overflow in current_settings.localswitches) then
  2441. exit;
  2442. case ovloc.loc of
  2443. LOC_FLAGS:
  2444. begin
  2445. current_asmdata.getjumplabel(hl);
  2446. if not ((def.typ=pointerdef) or
  2447. ((def.typ=orddef) and
  2448. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  2449. pasbool1,pasbool8,pasbool16,pasbool32,pasbool64]))) then
  2450. cond:=C_VC
  2451. else
  2452. cond:=C_CC;
  2453. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  2454. ai.SetCondition(cond);
  2455. ai.is_jmp:=true;
  2456. list.concat(ai);
  2457. a_call_name(list,'FPC_OVERFLOW',false);
  2458. a_label(list,hl);
  2459. end;
  2460. end;
  2461. end;
  2462. procedure tcgavr.g_save_registers(list: TAsmList);
  2463. begin
  2464. { this is done by the entry code }
  2465. end;
  2466. procedure tcgavr.g_restore_registers(list: TAsmList);
  2467. begin
  2468. { this is done by the exit code }
  2469. end;
  2470. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  2471. var
  2472. ai1,ai2 : taicpu;
  2473. hl : TAsmLabel;
  2474. begin
  2475. ai1:=Taicpu.Op_sym(A_BRxx,l);
  2476. ai1.is_jmp:=true;
  2477. hl:=nil;
  2478. case cond of
  2479. OC_EQ:
  2480. ai1.SetCondition(C_EQ);
  2481. OC_GT:
  2482. begin
  2483. { emulate GT }
  2484. current_asmdata.getjumplabel(hl);
  2485. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  2486. ai2.SetCondition(C_EQ);
  2487. ai2.is_jmp:=true;
  2488. list.concat(ai2);
  2489. ai1.SetCondition(C_GE);
  2490. end;
  2491. OC_LT:
  2492. ai1.SetCondition(C_LT);
  2493. OC_GTE:
  2494. ai1.SetCondition(C_GE);
  2495. OC_LTE:
  2496. begin
  2497. { emulate LTE }
  2498. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  2499. ai2.SetCondition(C_EQ);
  2500. ai2.is_jmp:=true;
  2501. list.concat(ai2);
  2502. ai1.SetCondition(C_LT);
  2503. end;
  2504. OC_NE:
  2505. ai1.SetCondition(C_NE);
  2506. OC_BE:
  2507. begin
  2508. { emulate BE }
  2509. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  2510. ai2.SetCondition(C_EQ);
  2511. ai2.is_jmp:=true;
  2512. list.concat(ai2);
  2513. ai1.SetCondition(C_LO);
  2514. end;
  2515. OC_B:
  2516. ai1.SetCondition(C_LO);
  2517. OC_AE:
  2518. ai1.SetCondition(C_SH);
  2519. OC_A:
  2520. begin
  2521. { emulate A (unsigned GT) }
  2522. current_asmdata.getjumplabel(hl);
  2523. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  2524. ai2.SetCondition(C_EQ);
  2525. ai2.is_jmp:=true;
  2526. list.concat(ai2);
  2527. ai1.SetCondition(C_SH);
  2528. end;
  2529. else
  2530. internalerror(2011082501);
  2531. end;
  2532. list.concat(ai1);
  2533. if assigned(hl) then
  2534. a_label(list,hl);
  2535. end;
  2536. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  2537. var
  2538. instr: taicpu;
  2539. begin
  2540. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  2541. list.Concat(instr);
  2542. { Notify the register allocator that we have written a move instruction so
  2543. it can try to eliminate it. }
  2544. add_move_instruction(instr);
  2545. end;
  2546. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  2547. begin
  2548. if not(size in [OS_S64,OS_64]) then
  2549. internalerror(2012102402);
  2550. tcgavr(cg).a_op_reg_reg_internal(list,Op,size,regsrc.reglo,regsrc.reghi,regdst.reglo,regdst.reghi);
  2551. end;
  2552. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  2553. begin
  2554. tcgavr(cg).a_op_const_reg_internal(list,Op,size,value,reg.reglo,reg.reghi);
  2555. end;
  2556. procedure tcg64favr.a_op64_const_reg_reg(list: TAsmList; op: TOpCg;size: tcgsize;value: int64;src,dst : tregister64);
  2557. begin
  2558. if op in [OP_SHL,OP_SHR] then
  2559. tcgavr(cg).a_op_const_reg_reg_internal(list,Op,size,value,src.reglo,src.reghi,dst.reglo,dst.reghi)
  2560. else
  2561. Inherited a_op64_const_reg_reg(list,op,size,value,src,dst);
  2562. end;
  2563. procedure create_codegen;
  2564. begin
  2565. cg:=tcgavr.create;
  2566. cg64:=tcg64favr.create;
  2567. end;
  2568. end.