cpuinfo.pas 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152
  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv5,
  28. cpu_armv7m,
  29. cpu_cortexm3
  30. );
  31. Const
  32. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv5];
  33. cpu_thumb = [];
  34. cpu_thumb2 = [cpu_armv7m,cpu_cortexm3];
  35. Type
  36. tfputype =
  37. (fpu_none,
  38. fpu_soft,
  39. fpu_libgcc,
  40. fpu_fpa,
  41. fpu_fpa10,
  42. fpu_fpa11,
  43. fpu_vfp
  44. );
  45. tcontrollertype =
  46. (ct_none,
  47. { Phillips }
  48. ct_lpc2114,
  49. ct_lpc2124,
  50. ct_lpc2194,
  51. { ATMEL }
  52. ct_at91sam7s256,
  53. ct_at91sam7se256,
  54. ct_at91sam7x256,
  55. ct_at91sam7xc256,
  56. { STMicroelectronics }
  57. ct_stm32f103re
  58. );
  59. Const
  60. {# Size of native extended floating point type }
  61. extended_size = 12;
  62. {# Size of a multimedia register }
  63. mmreg_size = 16;
  64. { target cpu string (used by compiler options) }
  65. target_cpu_string = 'arm';
  66. { calling conventions supported by the code generator }
  67. supported_calling_conventions : tproccalloptions = [
  68. pocall_internproc,
  69. pocall_safecall,
  70. pocall_stdcall,
  71. { same as stdcall only different name mangling }
  72. pocall_cdecl,
  73. { same as stdcall only different name mangling }
  74. pocall_cppdecl,
  75. { same as stdcall but floating point numbers are handled like equal sized integers }
  76. pocall_softfloat
  77. ];
  78. cputypestr : array[tcputype] of string[8] = ('',
  79. 'ARMV3',
  80. 'ARMV4',
  81. 'ARMV5',
  82. 'ARMV7M',
  83. 'CORTEXM3'
  84. );
  85. fputypestr : array[tfputype] of string[6] = ('',
  86. 'SOFT',
  87. 'LIBGCC',
  88. 'FPA',
  89. 'FPA10',
  90. 'FPA11',
  91. 'VFP'
  92. );
  93. controllertypestr : array[tcontrollertype] of string[20] =
  94. ('',
  95. 'LPC2114',
  96. 'LPC2124',
  97. 'LPC2194',
  98. 'AT91SAM7S256',
  99. 'AT91SAM7SE256',
  100. 'AT91SAM7X256',
  101. 'AT91SAM7XC256',
  102. 'STM32F103RE'
  103. );
  104. controllerunitstr : array[tcontrollertype] of string[20] =
  105. ('',
  106. 'LPC21x4',
  107. 'LPC21x4',
  108. 'LPC21x4',
  109. 'AT91SAM7x256',
  110. 'AT91SAM7x256',
  111. 'AT91SAM7x256',
  112. 'AT91SAM7x256',
  113. 'STM32F103'
  114. );
  115. { Supported optimizations, only used for information }
  116. supported_optimizerswitches = genericlevel1optimizerswitches+
  117. genericlevel2optimizerswitches+
  118. genericlevel3optimizerswitches-
  119. { no need to write info about those }
  120. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  121. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,cs_opt_stackframe];
  122. level1optimizerswitches = genericlevel1optimizerswitches;
  123. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches + [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion];
  124. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  125. Implementation
  126. end.