2
0

arm.inc 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608
  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 2003 by the Free Pascal development team.
  4. Processor dependent implementation for the system unit for
  5. ARM
  6. See the file COPYING.FPC, included in this distribution,
  7. for details about the copyright.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11. **********************************************************************}
  12. {$asmmode gas}
  13. {$ifndef FPC_SYSTEM_HAS_MOVE}
  14. {$define FPC_SYSTEM_FPC_MOVE}
  15. {$endif FPC_SYSTEM_HAS_MOVE}
  16. {$ifdef FPC_SYSTEM_FPC_MOVE}
  17. const
  18. cpu_has_edsp : boolean = false;
  19. in_edsp_test : boolean = false;
  20. {$endif FPC_SYSTEM_FPC_MOVE}
  21. {$if not(defined(wince)) and not(defined(gba)) and not(defined(nds)) and not(defined(FPUSOFT)) and not(defined(FPULIBGCC))}
  22. {$define FPC_SYSTEM_HAS_SYSINITFPU}
  23. Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  24. begin
  25. { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
  26. asm
  27. rfs r0
  28. and r0,r0,#0xffe0ffff
  29. orr r0,r0,#0x00070000
  30. wfs r0
  31. end;
  32. end;
  33. {$endif}
  34. procedure fpc_cpuinit;
  35. begin
  36. SysInitFPU;
  37. end;
  38. {$ifdef wince}
  39. function _controlfp(new: DWORD; mask: DWORD): DWORD; cdecl; external 'coredll';
  40. {$define FPC_SYSTEM_HAS_SYSRESETFPU}
  41. Procedure SysResetFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  42. begin
  43. softfloat_exception_flags:=0;
  44. end;
  45. {$define FPC_SYSTEM_HAS_SYSINITFPU}
  46. Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  47. begin
  48. softfloat_exception_mask:=float_flag_underflow or float_flag_inexact or float_flag_denormal;
  49. { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
  50. { FPU precision 64 bit, rounding to nearest, affine infinity }
  51. _controlfp($000C0003, $030F031F);
  52. end;
  53. {$endif wince}
  54. {****************************************************************************
  55. stack frame related stuff
  56. ****************************************************************************}
  57. {$IFNDEF INTERNAL_BACKTRACE}
  58. {$define FPC_SYSTEM_HAS_GET_FRAME}
  59. function get_frame:pointer;assembler;nostackframe;
  60. asm
  61. mov r0,r11
  62. end;
  63. {$ENDIF not INTERNAL_BACKTRACE}
  64. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  65. function get_caller_addr(framebp:pointer):pointer;assembler;
  66. asm
  67. movs r0,r0
  68. beq .Lg_a_null
  69. ldr r0,[r0,#-4]
  70. .Lg_a_null:
  71. end;
  72. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  73. function get_caller_frame(framebp:pointer):pointer;assembler;
  74. asm
  75. movs r0,r0
  76. beq .Lgnf_null
  77. ldr r0,[r0,#-12]
  78. .Lgnf_null:
  79. end;
  80. {$define FPC_SYSTEM_HAS_SPTR}
  81. Function Sptr : pointer;assembler;
  82. asm
  83. mov r0,sp
  84. end;
  85. {$ifndef FPC_SYSTEM_HAS_FILLCHAR}
  86. {$define FPC_SYSTEM_HAS_FILLCHAR}
  87. Procedure FillChar(var x;count:longint;value:byte);assembler;nostackframe;
  88. asm
  89. // less than 0?
  90. cmp r1,#0
  91. movlt pc,lr
  92. mov r3,r0
  93. cmp r1,#8 // at least 8 bytes to do?
  94. blt .LFillchar2
  95. orr r2,r2,r2,lsl #8
  96. orr r2,r2,r2,lsl #16
  97. .LFillchar0:
  98. tst r3,#3 // aligned yet?
  99. strneb r2,[r3],#1
  100. subne r1,r1,#1
  101. bne .LFillchar0
  102. mov ip,r2
  103. .LFillchar1:
  104. cmp r1,#8 // 8 bytes still to do?
  105. blt .LFillchar2
  106. stmia r3!,{r2,ip}
  107. sub r1,r1,#8
  108. cmp r1,#8 // 8 bytes still to do?
  109. blt .LFillchar2
  110. stmia r3!,{r2,ip}
  111. sub r1,r1,#8
  112. cmp r1,#8 // 8 bytes still to do?
  113. blt .LFillchar2
  114. stmia r3!,{r2,ip}
  115. sub r1,r1,#8
  116. cmp r1,#8 // 8 bytes still to do?
  117. stmgeia r3!,{r2,ip}
  118. subge r1,r1,#8
  119. bge .LFillchar1
  120. .LFillchar2:
  121. movs r1,r1 // anything left?
  122. moveq pc,lr
  123. rsb r1,r1,#7
  124. add pc,pc,r1,lsl #2
  125. mov r0,r0
  126. strb r2,[r3],#1
  127. strb r2,[r3],#1
  128. strb r2,[r3],#1
  129. strb r2,[r3],#1
  130. strb r2,[r3],#1
  131. strb r2,[r3],#1
  132. strb r2,[r3],#1
  133. mov pc,lr
  134. end;
  135. {$endif FPC_SYSTEM_HAS_FILLCHAR}
  136. {$ifndef FPC_SYSTEM_HAS_MOVE}
  137. {$define FPC_SYSTEM_HAS_MOVE}
  138. procedure Move_pld(const source;var dest;count:longint);assembler;nostackframe;
  139. asm
  140. pld [r0]
  141. pld [r1]
  142. // count <=0 ?
  143. cmp r2,#0
  144. movle pc,lr
  145. // overlap?
  146. cmp r1,r0
  147. bls .Lnooverlap
  148. add r3,r0,r2
  149. cmp r3,r1
  150. bls .Lnooverlap
  151. // overlap, copy backward
  152. .Loverlapped:
  153. subs r2,r2,#1
  154. ldrb r3,[r0,r2]
  155. strb r3,[r1,r2]
  156. bne .Loverlapped
  157. mov pc,lr
  158. .Lnooverlap:
  159. // less then 16 bytes to copy?
  160. cmp r2,#8
  161. // yes, the forget about the whole optimizations
  162. // and do a bytewise copy
  163. blt .Lbyteloop
  164. // both aligned?
  165. orr r3,r0,r1
  166. tst r3,#3
  167. bne .Lbyteloop
  168. (*
  169. // yes, then align
  170. // alignment to 4 byte boundries is enough
  171. ldrb ip,[r0],#1
  172. sub r2,r2,#1
  173. stb ip,[r1],#1
  174. tst r3,#2
  175. bne .Ldifferentaligned
  176. ldrh ip,[r0],#2
  177. sub r2,r2,#2
  178. sth ip,[r1],#2
  179. .Ldifferentaligned
  180. // qword aligned?
  181. orrs r3,r0,r1
  182. tst r3,#7
  183. bne .Ldwordloop
  184. *)
  185. pld [r0,#32]
  186. pld [r1,#32]
  187. .Ldwordloop:
  188. sub r2,r2,#4
  189. ldr r3,[r0],#4
  190. // preload
  191. pld [r0,#64]
  192. pld [r1,#64]
  193. cmp r2,#4
  194. str r3,[r1],#4
  195. bcs .Ldwordloop
  196. cmp r2,#0
  197. moveq pc,lr
  198. .Lbyteloop:
  199. subs r2,r2,#1
  200. ldrb r3,[r0],#1
  201. strb r3,[r1],#1
  202. bne .Lbyteloop
  203. mov pc,lr
  204. end;
  205. procedure Move_blended(const source;var dest;count:longint);assembler;nostackframe;
  206. asm
  207. // count <=0 ?
  208. cmp r2,#0
  209. movle pc,lr
  210. // overlap?
  211. cmp r1,r0
  212. bls .Lnooverlap
  213. add r3,r0,r2
  214. cmp r3,r1
  215. bls .Lnooverlap
  216. // overlap, copy backward
  217. .Loverlapped:
  218. subs r2,r2,#1
  219. ldrb r3,[r0,r2]
  220. strb r3,[r1,r2]
  221. bne .Loverlapped
  222. mov pc,lr
  223. .Lnooverlap:
  224. // less then 16 bytes to copy?
  225. cmp r2,#8
  226. // yes, the forget about the whole optimizations
  227. // and do a bytewise copy
  228. blt .Lbyteloop
  229. // both aligned?
  230. orr r3,r0,r1
  231. tst r3,#3
  232. bne .Lbyteloop
  233. (*
  234. // yes, then align
  235. // alignment to 4 byte boundries is enough
  236. ldrb ip,[r0],#1
  237. sub r2,r2,#1
  238. stb ip,[r1],#1
  239. tst r3,#2
  240. bne .Ldifferentaligned
  241. ldrh ip,[r0],#2
  242. sub r2,r2,#2
  243. sth ip,[r1],#2
  244. .Ldifferentaligned
  245. // qword aligned?
  246. orrs r3,r0,r1
  247. tst r3,#7
  248. bne .Ldwordloop
  249. *)
  250. .Ldwordloop:
  251. sub r2,r2,#4
  252. ldr r3,[r0],#4
  253. cmp r2,#4
  254. str r3,[r1],#4
  255. bcs .Ldwordloop
  256. cmp r2,#0
  257. moveq pc,lr
  258. .Lbyteloop:
  259. subs r2,r2,#1
  260. ldrb r3,[r0],#1
  261. strb r3,[r1],#1
  262. bne .Lbyteloop
  263. mov pc,lr
  264. end;
  265. const
  266. moveproc : pointer = @move_blended;
  267. procedure Move(const source;var dest;count:longint);[public, alias: 'FPC_MOVE'];assembler;nostackframe;
  268. asm
  269. ldr ip,.Lmoveproc
  270. ldr pc,[ip]
  271. .Lmoveproc:
  272. .long moveproc
  273. end;
  274. {$endif FPC_SYSTEM_HAS_MOVE}
  275. {****************************************************************************
  276. String
  277. ****************************************************************************}
  278. {$ifndef FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  279. {$define FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  280. {$ifndef FPC_STRTOSHORTSTRINGPROC}
  281. function fpc_shortstr_to_shortstr(len:longint;const sstr:shortstring):shortstring;assembler;nostackframe;[public,alias: 'FPC_SHORTSTR_TO_SHORTSTR'];compilerproc;
  282. {$else}
  283. procedure fpc_shortstr_to_shortstr(out res:shortstring;const sstr:shortstring);assembler;nostackframe;[public,alias: 'FPC_SHORTSTR_TO_SHORTSTR'];compilerproc;
  284. {$endif}
  285. {r0: __RESULT
  286. r1: len
  287. r2: sstr}
  288. asm
  289. ldrb r12,[r2],#1
  290. cmp r12,r1
  291. movgt r12,r1
  292. strb r12,[r0],#1
  293. cmp r12,#6 (* 6 seems to be the break even point. *)
  294. blt .LStartTailCopy
  295. (* Align destination on 32bits. This is the only place where unrolling
  296. really seems to help, since in the common case, sstr is aligned on
  297. 32 bits, therefore in the common case we need to copy 3 bytes to
  298. align, i.e. in the case of a loop, you wouldn't branch out early.*)
  299. rsb r3,r0,#0
  300. ands r3,r3,#3
  301. sub r12,r12,r3
  302. ldrneb r1,[r2],#1
  303. strneb r1,[r0],#1
  304. subnes r3,r3,#1
  305. ldrneb r1,[r2],#1
  306. strneb r1,[r0],#1
  307. subnes r3,r3,#1
  308. ldrneb r1,[r2],#1
  309. strneb r1,[r0],#1
  310. subnes r3,r3,#1
  311. .LDoneAlign:
  312. (* Destination should be aligned now, but source might not be aligned,
  313. if this is the case, do a byte-per-byte copy. *)
  314. tst r2,#3
  315. bne .LStartTailCopy
  316. (* Start the main copy, 32 bit at a time. *)
  317. movs r3,r12,lsr #2
  318. and r12,r12,#3
  319. beq .LStartTailCopy
  320. .LNext4bytes:
  321. (* Unrolling this loop would save a little bit of time for long strings
  322. (>20 chars), but alas, it hurts for short strings and they are the
  323. common case.*)
  324. ldrne r1,[r2],#4
  325. strne r1,[r0],#4
  326. subnes r3,r3,#1
  327. bne .LNext4bytes
  328. .LStartTailCopy:
  329. (* Do remaining bytes. *)
  330. cmp r12,#0
  331. beq .LDoneTail
  332. .LNextChar3:
  333. ldrb r1,[r2],#1
  334. strb r1,[r0],#1
  335. subs r12,r12,#1
  336. bne .LNextChar3
  337. .LDoneTail:
  338. end;
  339. procedure fpc_shortstr_assign(len:longint;sstr,dstr:pointer);assembler;nostackframe;[public,alias:'FPC_SHORTSTR_ASSIGN'];compilerproc;
  340. {r0: len
  341. r1: sstr
  342. r2: dstr}
  343. asm
  344. ldrb r12,[r1],#1
  345. cmp r12,r0
  346. movgt r12,r0
  347. strb r12,[r2],#1
  348. cmp r12,#6 (* 6 seems to be the break even point. *)
  349. blt .LStartTailCopy
  350. (* Align destination on 32bits. This is the only place where unrolling
  351. really seems to help, since in the common case, sstr is aligned on
  352. 32 bits, therefore in the common case we need to copy 3 bytes to
  353. align, i.e. in the case of a loop, you wouldn't branch out early.*)
  354. rsb r3,r2,#0
  355. ands r3,r3,#3
  356. sub r12,r12,r3
  357. ldrneb r0,[r1],#1
  358. strneb r0,[r2],#1
  359. subnes r3,r3,#1
  360. ldrneb r0,[r1],#1
  361. strneb r0,[r2],#1
  362. subnes r3,r3,#1
  363. ldrneb r0,[r1],#1
  364. strneb r0,[r2],#1
  365. subnes r3,r3,#1
  366. .LDoneAlign:
  367. (* Destination should be aligned now, but source might not be aligned,
  368. if this is the case, do a byte-per-byte copy. *)
  369. tst r1,#3
  370. bne .LStartTailCopy
  371. (* Start the main copy, 32 bit at a time. *)
  372. movs r3,r12,lsr #2
  373. and r12,r12,#3
  374. beq .LStartTailCopy
  375. .LNext4bytes:
  376. (* Unrolling this loop would save a little bit of time for long strings
  377. (>20 chars), but alas, it hurts for short strings and they are the
  378. common case.*)
  379. ldrne r0,[r1],#4
  380. strne r0,[r2],#4
  381. subnes r3,r3,#1
  382. bne .LNext4bytes
  383. .LStartTailCopy:
  384. (* Do remaining bytes. *)
  385. cmp r12,#0
  386. beq .LDoneTail
  387. .LNextChar3:
  388. ldrb r0,[r1],#1
  389. strb r0,[r2],#1
  390. subs r12,r12,#1
  391. bne .LNextChar3
  392. .LDoneTail:
  393. end;
  394. {$endif FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  395. {$ifndef FPC_SYSTEM_HAS_FPC_PCHAR_LENGTH}
  396. {$define FPC_SYSTEM_HAS_FPC_PCHAR_LENGTH}
  397. function fpc_Pchar_length(p:Pchar):longint;assembler;nostackframe;[public,alias:'FPC_PCHAR_LENGTH'];compilerproc;
  398. asm
  399. cmp r0,#0
  400. mov r1,r0
  401. beq .Ldone
  402. .Lnextchar:
  403. (*Are we aligned?*)
  404. tst r1,#3
  405. bne .Ltest_unaligned (*No, do byte per byte.*)
  406. ldr r3,.L01010101
  407. .Ltest_aligned:
  408. (*Aligned, load 4 bytes at a time.*)
  409. ldr r12,[r1],#4
  410. (*Check wether r12 contains a 0 byte.*)
  411. sub r2,r12,r3
  412. mvn r12,r12
  413. and r2,r2,r12
  414. ands r2,r2,r3,lsl #7 (*r3 lsl 7 = $80808080*)
  415. beq .Ltest_aligned (*No 0 byte, repeat.*)
  416. sub r1,r1,#4
  417. .Ltest_unaligned:
  418. ldrb r12,[r1],#1
  419. cmp r12,#1 (*r12<1 same as r12=0, but result in carry flag*)
  420. bcs .Lnextchar
  421. (*Dirty trick: we need to subtract 1 extra because we have counted the
  422. terminating 0, due to the known carry flag sbc can do this.*)
  423. sbc r0,r1,r0
  424. .Ldone:
  425. mov pc,lr
  426. .L01010101:
  427. .long 0x01010101
  428. end;
  429. {$endif}
  430. var
  431. fpc_system_lock: longint; export name 'fpc_system_lock';
  432. function InterLockedDecrement (var Target: longint) : longint; assembler; nostackframe;
  433. asm
  434. // lock
  435. ldr r3, .Lfpc_system_lock
  436. mov r1, #1
  437. .Lloop:
  438. swp r2, r1, [r3]
  439. cmp r2, #0
  440. bne .Lloop
  441. // do the job
  442. ldr r1, [r0]
  443. sub r1, r1, #1
  444. str r1, [r0]
  445. mov r0, r1
  446. // unlock and return
  447. str r2, [r3]
  448. mov pc, lr
  449. .Lfpc_system_lock:
  450. .long fpc_system_lock
  451. end;
  452. function InterLockedIncrement (var Target: longint) : longint; assembler; nostackframe;
  453. asm
  454. // lock
  455. ldr r3, .Lfpc_system_lock
  456. mov r1, #1
  457. .Lloop:
  458. swp r2, r1, [r3]
  459. cmp r2, #0
  460. bne .Lloop
  461. // do the job
  462. ldr r1, [r0]
  463. add r1, r1, #1
  464. str r1, [r0]
  465. mov r0, r1
  466. // unlock and return
  467. str r2, [r3]
  468. mov pc, lr
  469. .Lfpc_system_lock:
  470. .long fpc_system_lock
  471. end;
  472. function InterLockedExchange (var Target: longint;Source : longint) : longint; assembler; nostackframe;
  473. asm
  474. swp r1, r1, [r0]
  475. mov r0,r1
  476. end;
  477. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint; assembler; nostackframe;
  478. asm
  479. // lock
  480. ldr r3, .Lfpc_system_lock
  481. mov r2, #1
  482. .Lloop:
  483. swp r2, r2, [r3]
  484. cmp r2, #0
  485. bne .Lloop
  486. // do the job
  487. ldr r2, [r0]
  488. add r1, r1, r2
  489. str r1, [r0]
  490. mov r0, r2
  491. // unlock and return
  492. mov r2, #0
  493. str r2, [r3]
  494. mov pc, lr
  495. .Lfpc_system_lock:
  496. .long fpc_system_lock
  497. end;
  498. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint; assembler; nostackframe;
  499. asm
  500. // lock
  501. ldr r12, .Lfpc_system_lock
  502. mov r3, #1
  503. .Lloop:
  504. swp r3, r3, [r12]
  505. cmp r3, #0
  506. bne .Lloop
  507. // do the job
  508. ldr r3, [r0]
  509. cmp r3, r2
  510. streq r1, [r0]
  511. mov r0, r3
  512. // unlock and return
  513. mov r3, #0
  514. str r3, [r12]
  515. mov pc, lr
  516. .Lfpc_system_lock:
  517. .long fpc_system_lock
  518. end;
  519. {$define FPC_SYSTEM_HAS_DECLOCKED_LONGINT}
  520. function declocked(var l: longint) : boolean; inline;
  521. begin
  522. Result:=InterLockedDecrement(l) = 0;
  523. end;
  524. {$define FPC_SYSTEM_HAS_INCLOCKED_LONGINT}
  525. procedure inclocked(var l: longint); inline;
  526. begin
  527. InterLockedIncrement(l);
  528. end;
  529. procedure fpc_cpucodeinit;
  530. begin
  531. {$ifdef FPC_SYSTEM_FPC_MOVE}
  532. cpu_has_edsp:=true;
  533. in_edsp_test:=true;
  534. asm
  535. bic r0,sp,#7
  536. ldrd r0,[r0]
  537. end;
  538. in_edsp_test:=false;
  539. if cpu_has_edsp then
  540. moveproc:=@move_pld
  541. else
  542. moveproc:=@move_blended;
  543. {$endif FPC_SYSTEM_FPC_MOVE}
  544. end;
  545. {include hand-optimized assembler division code}
  546. {$i divide.inc}