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aasmcpu.pas
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78dbdcb095
Disable overflow/range check in some part of the arm code
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hai 1 ano |
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agarmgas.pas
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7c7f2cfdea
* pass float abi always to the arm assembler
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%!s(int64=3) %!d(string=hai) anos |
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aoptcpu.pas
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92cd9502ef
Merge of revisions 40277
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%!s(int64=6) %!d(string=hai) anos |
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aoptcpub.pas
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d37e72dbf9
* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.
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%!s(int64=11) %!d(string=hai) anos |
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aoptcpud.pas
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790a4fe2d3
* log and id tags removed
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%!s(int64=20) %!d(string=hai) anos |
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armatt.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armatts.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armins.dat
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a3db71325e
Merge of commit #47207
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%!s(int64=4) %!d(string=hai) anos |
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armnop.inc
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4f5f3c4a09
+ support for vmov.xx vreg,#imm on arm
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%!s(int64=7) %!d(string=hai) anos |
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armop.inc
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9d1646e2a8
Add support for writeback in RFE and SRS instructions.
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%!s(int64=9) %!d(string=hai) anos |
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armreg.dat
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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armtab.inc
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a3db71325e
Merge of commit #47207
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%!s(int64=4) %!d(string=hai) anos |
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cgcpu.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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cpubase.pas
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78dbdcb095
Disable overflow/range check in some part of the arm code
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hai 1 ano |
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cpuelf.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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cpuinfo.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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cpunode.pas
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a0efde8167
* automatically generate necessary indirect symbols when a new assembler
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%!s(int64=9) %!d(string=hai) anos |
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cpupara.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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cpupi.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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cputarg.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
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hlcgcpu.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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%!s(int64=7) %!d(string=hai) anos |
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itcpugas.pas
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47d43750e4
* remove unused units from uses statements
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%!s(int64=12) %!d(string=hai) anos |
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narmadd.pas
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d1f31fab15
Merge commits 42525 and 45891 that add
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%!s(int64=5) %!d(string=hai) anos |
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narmcal.pas
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f5f895e2a3
syscalls: unify call reference creation across 4 different CPU archs. less copypasted code, brings x86_64 AROS support up to speed
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%!s(int64=8) %!d(string=hai) anos |
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narmcnv.pas
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c961c72c30
* tarmtypeconvnode.first_int_to_real should call the generic method in the parent class, if soft fpu code is generated, resolves #31350
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%!s(int64=8) %!d(string=hai) anos |
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narmcon.pas
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4aa0ad6735
* use vmov.xx to load float constants if possible
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%!s(int64=7) %!d(string=hai) anos |
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narminl.pas
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d1f31fab15
Merge commits 42525 and 45891 that add
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%!s(int64=5) %!d(string=hai) anos |
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narmmat.pas
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d1f31fab15
Merge commits 42525 and 45891 that add
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%!s(int64=5) %!d(string=hai) anos |
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narmmem.pas
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d6de2c03cb
* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe
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%!s(int64=10) %!d(string=hai) anos |
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narmset.pas
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197f5cbec5
* let all the case code generation work with tconstexprint instead of aint,
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%!s(int64=4) %!d(string=hai) anos |
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pp.lpi.template
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1f032375c3
* improved template with help from Mattias Gaertner
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%!s(int64=19) %!d(string=hai) anos |
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raarm.pas
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780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
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%!s(int64=14) %!d(string=hai) anos |
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raarmgas.pas
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1b66995754
* factored out check to determine whether a variable can be subscripted in
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%!s(int64=7) %!d(string=hai) anos |
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rarmcon.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmdwa.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmnor.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmnum.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmrni.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsri.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsta.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmstd.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rarmsup.inc
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387824c1ee
Added some APSR register bitmask definitions.
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%!s(int64=10) %!d(string=hai) anos |
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rgcpu.pas
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4686f61002
* keep track of the temp position separately from the offset in references,
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%!s(int64=7) %!d(string=hai) anos |
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symcpu.pas
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3ac703506c
* rest of the previous accidental partial commit
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%!s(int64=6) %!d(string=hai) anos |
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tripletcpu.pas
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76045bfc04
* merged macOS/AArch64 support + revisions these changes depended on
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%!s(int64=4) %!d(string=hai) anos |
pierre
78dbdcb095
Disable overflow/range check in some part of the arm code