atmega168pb.pp 21 KB

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  1. unit ATmega168PB;
  2. {$goto on}
  3. interface
  4. var
  5. PINB: byte absolute $23; // Port B Input Pins
  6. DDRB: byte absolute $24; // Port B Data Direction Register
  7. PORTB: byte absolute $25; // Port B Data Register
  8. PINC: byte absolute $26; // Port C Input Pins
  9. DDRC: byte absolute $27; // Port C Data Direction Register
  10. PORTC: byte absolute $28; // Port C Data Register
  11. PIND: byte absolute $29; // Port D Input Pins
  12. DDRD: byte absolute $2A; // Port D Data Direction Register
  13. PORTD: byte absolute $2B; // Port D Data Register
  14. PINE: byte absolute $2C; // Port E Input Pins
  15. DDRE: byte absolute $2D; // Port E Data Direction Register
  16. PORTE: byte absolute $2E; // Port E Data Register
  17. TIFR0: byte absolute $35; // Timer/Counter0 Interrupt Flag register
  18. TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
  19. TIFR2: byte absolute $37; // Timer/Counter Interrupt Flag Register
  20. PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
  21. EIFR: byte absolute $3C; // External Interrupt Flag Register
  22. EIMSK: byte absolute $3D; // External Interrupt Mask Register
  23. GPIOR0: byte absolute $3E; // General Purpose I/O Register 0
  24. EECR: byte absolute $3F; // EEPROM Control Register
  25. EEDR: byte absolute $40; // EEPROM Data Register
  26. EEAR: word absolute $41; // EEPROM Address Register Bytes
  27. EEARL: byte absolute $41; // EEPROM Address Register Bytes
  28. EEARH: byte absolute $42; // EEPROM Address Register Bytes;
  29. GTCCR: byte absolute $43; // General Timer/Counter Control Register
  30. TCCR0A: byte absolute $44; // Timer/Counter Control Register A
  31. TCCR0B: byte absolute $45; // Timer/Counter Control Register B
  32. TCNT0: byte absolute $46; // Timer/Counter0
  33. OCR0A: byte absolute $47; // Timer/Counter0 Output Compare Register
  34. OCR0B: byte absolute $48; // Timer/Counter0 Output Compare Register
  35. GPIOR1: byte absolute $4A; // General Purpose I/O Register 1
  36. GPIOR2: byte absolute $4B; // General Purpose I/O Register 2
  37. SPCR: byte absolute $4C; // SPI Control Register
  38. SPSR: byte absolute $4D; // SPI Status Register
  39. SPDR: byte absolute $4E; // SPI Data Register
  40. ACSRB: byte absolute $4F; // Analog Comparator Status Register B
  41. ACSR: byte absolute $50; // Analog Comparator Control And Status Register
  42. SMCR: byte absolute $53; // Sleep Mode Control Register
  43. MCUSR: byte absolute $54; // MCU Status Register
  44. MCUCR: byte absolute $55; // MCU Control Register
  45. SPMCSR: byte absolute $57; // Store Program Memory Control and Status Register
  46. SP: word absolute $5D; // Stack Pointer
  47. SPL: byte absolute $5D; // Stack Pointer
  48. SPH: byte absolute $5E; // Stack Pointer ;
  49. SREG: byte absolute $5F; // Status Register
  50. WDTCSR: byte absolute $60; // Watchdog Timer Control Register
  51. CLKPR: byte absolute $61; // Clock Prescale Register
  52. PRR: byte absolute $64; // Power Reduction Register
  53. OSCCAL: byte absolute $66; // Oscillator Calibration Value
  54. PCICR: byte absolute $68; // Pin Change Interrupt Control Register
  55. EICRA: byte absolute $69; // External Interrupt Control Register
  56. PCMSK0: byte absolute $6B; // Pin Change Mask Register 0
  57. PCMSK1: byte absolute $6C; // Pin Change Mask Register 1
  58. PCMSK2: byte absolute $6D; // Pin Change Mask Register 2
  59. TIMSK0: byte absolute $6E; // Timer/Counter0 Interrupt Mask Register
  60. TIMSK1: byte absolute $6F; // Timer/Counter Interrupt Mask Register
  61. TIMSK2: byte absolute $70; // Timer/Counter Interrupt Mask register
  62. ADC: word absolute $78; // ADC Data Register Bytes
  63. ADCL: byte absolute $78; // ADC Data Register Bytes
  64. ADCH: byte absolute $79; // ADC Data Register Bytes;
  65. ADCSRA: byte absolute $7A; // The ADC Control and Status register A
  66. ADCSRB: byte absolute $7B; // The ADC Control and Status register B
  67. ADMUX: byte absolute $7C; // The ADC multiplexer Selection Register
  68. DIDR0: byte absolute $7E; // Digital Input Disable Register
  69. DIDR1: byte absolute $7F; // Digital Input Disable Register 1
  70. TCCR1A: byte absolute $80; // Timer/Counter1 Control Register A
  71. TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
  72. TCCR1C: byte absolute $82; // Timer/Counter1 Control Register C
  73. TCNT1: word absolute $84; // Timer/Counter1 Bytes
  74. TCNT1L: byte absolute $84; // Timer/Counter1 Bytes
  75. TCNT1H: byte absolute $85; // Timer/Counter1 Bytes;
  76. ICR1: word absolute $86; // Timer/Counter1 Input Capture Register Bytes
  77. ICR1L: byte absolute $86; // Timer/Counter1 Input Capture Register Bytes
  78. ICR1H: byte absolute $87; // Timer/Counter1 Input Capture Register Bytes;
  79. OCR1A: word absolute $88; // Timer/Counter1 Output Compare Register Bytes
  80. OCR1AL: byte absolute $88; // Timer/Counter1 Output Compare Register Bytes
  81. OCR1AH: byte absolute $89; // Timer/Counter1 Output Compare Register Bytes;
  82. OCR1B: word absolute $8A; // Timer/Counter1 Output Compare Register Bytes
  83. OCR1BL: byte absolute $8A; // Timer/Counter1 Output Compare Register Bytes
  84. OCR1BH: byte absolute $8B; // Timer/Counter1 Output Compare Register Bytes;
  85. TCCR2A: byte absolute $B0; // Timer/Counter2 Control Register A
  86. TCCR2B: byte absolute $B1; // Timer/Counter2 Control Register B
  87. TCNT2: byte absolute $B2; // Timer/Counter2
  88. OCR2A: byte absolute $B3; // Timer/Counter2 Output Compare Register A
  89. OCR2B: byte absolute $B4; // Timer/Counter2 Output Compare Register B
  90. ASSR: byte absolute $B6; // Asynchronous Status Register
  91. TWBR: byte absolute $B8; // TWI Bit Rate register
  92. TWSR: byte absolute $B9; // TWI Status Register
  93. TWAR: byte absolute $BA; // TWI (Slave) Address register
  94. TWDR: byte absolute $BB; // TWI Data register
  95. TWCR: byte absolute $BC; // TWI Control Register
  96. TWAMR: byte absolute $BD; // TWI (Slave) Address Mask Register
  97. UCSR0A: byte absolute $C0; // USART Control and Status Register A
  98. UCSR0B: byte absolute $C1; // USART Control and Status Register B
  99. UCSR0C: byte absolute $C2; // USART Control and Status Register C
  100. UCSR0D: byte absolute $C3; // USART Control and Status Register D
  101. UBRR0: word absolute $C4; // USART Baud Rate Register Bytes
  102. UBRR0L: byte absolute $C4; // USART Baud Rate Register Bytes
  103. UBRR0H: byte absolute $C5; // USART Baud Rate Register Bytes;
  104. UDR0: byte absolute $C6; // USART I/O Data Register
  105. DEVID0: byte absolute $F0;
  106. DEVID1: byte absolute $F1;
  107. DEVID2: byte absolute $F2;
  108. DEVID3: byte absolute $F3;
  109. DEVID4: byte absolute $F4;
  110. DEVID5: byte absolute $F5;
  111. DEVID6: byte absolute $F6;
  112. DEVID7: byte absolute $F7;
  113. DEVID8: byte absolute $F8;
  114. const
  115. // Port B Data Register
  116. PB0 = $00;
  117. PB1 = $01;
  118. PB2 = $02;
  119. PB3 = $03;
  120. PB4 = $04;
  121. PB5 = $05;
  122. PB6 = $06;
  123. PB7 = $07;
  124. // Port C Data Register
  125. PC0 = $00;
  126. PC1 = $01;
  127. PC2 = $02;
  128. PC3 = $03;
  129. PC4 = $04;
  130. PC5 = $05;
  131. PC6 = $06;
  132. // Port D Data Register
  133. PD0 = $00;
  134. PD1 = $01;
  135. PD2 = $02;
  136. PD3 = $03;
  137. PD4 = $04;
  138. PD5 = $05;
  139. PD6 = $06;
  140. PD7 = $07;
  141. // Port E Data Register
  142. PE0 = $00;
  143. PE1 = $01;
  144. PE2 = $02;
  145. PE3 = $03;
  146. // Timer/Counter0 Interrupt Flag register
  147. TOV0 = $00;
  148. OCF0A = $01;
  149. OCF0B = $02;
  150. // Timer/Counter Interrupt Flag register
  151. TOV1 = $00;
  152. OCF1A = $01;
  153. OCF1B = $02;
  154. ICF1 = $05;
  155. // Timer/Counter Interrupt Flag Register
  156. TOV2 = $00;
  157. OCF2A = $01;
  158. OCF2B = $02;
  159. // Pin Change Interrupt Flag Register
  160. PCIF0 = $00; // Pin Change Interrupt Flags
  161. PCIF1 = $01; // Pin Change Interrupt Flags
  162. PCIF2 = $02; // Pin Change Interrupt Flags
  163. // External Interrupt Flag Register
  164. INTF0 = $00; // External Interrupt Flags
  165. INTF1 = $01; // External Interrupt Flags
  166. // External Interrupt Mask Register
  167. INT0 = $00; // External Interrupt Request 1 Enable
  168. INT1 = $01; // External Interrupt Request 1 Enable
  169. // EEPROM Control Register
  170. EERE = $00;
  171. EEPE = $01;
  172. EEMPE = $02;
  173. EERIE = $03;
  174. EEPM0 = $04; // EEPROM Programming Mode Bits
  175. EEPM1 = $05; // EEPROM Programming Mode Bits
  176. // General Timer/Counter Control Register
  177. PSRSYNC = $00;
  178. PSRASY = $01;
  179. TSM = $07;
  180. // Timer/Counter Control Register A
  181. WGM00 = $00; // Waveform Generation Mode
  182. WGM01 = $01; // Waveform Generation Mode
  183. COM0B0 = $04; // Compare Output Mode, Fast PWm
  184. COM0B1 = $05; // Compare Output Mode, Fast PWm
  185. COM0A0 = $06; // Compare Output Mode, Phase Correct PWM Mode
  186. COM0A1 = $07; // Compare Output Mode, Phase Correct PWM Mode
  187. // Timer/Counter Control Register B
  188. CS00 = $00; // Clock Select
  189. CS01 = $01; // Clock Select
  190. CS02 = $02; // Clock Select
  191. WGM02 = $03;
  192. FOC0B = $06;
  193. FOC0A = $07;
  194. // SPI Control Register
  195. SPR0 = $00; // SPI Clock Rate Selects
  196. SPR1 = $01; // SPI Clock Rate Selects
  197. CPHA = $02;
  198. CPOL = $03;
  199. MSTR = $04;
  200. DORD = $05;
  201. SPE = $06;
  202. SPIE = $07;
  203. // SPI Status Register
  204. SPI2X = $00;
  205. WCOL = $06;
  206. SPIF = $07;
  207. // Analog Comparator Status Register B
  208. ACOE = $00;
  209. // Analog Comparator Control And Status Register
  210. ACIS0 = $00; // Analog Comparator Interrupt Mode Select bits
  211. ACIS1 = $01; // Analog Comparator Interrupt Mode Select bits
  212. ACIC = $02;
  213. ACIE = $03;
  214. ACI = $04;
  215. ACO = $05;
  216. ACBG = $06;
  217. ACD = $07;
  218. // Sleep Mode Control Register
  219. SE = $00;
  220. SM0 = $01; // Sleep Mode Select Bits
  221. SM1 = $02; // Sleep Mode Select Bits
  222. SM2 = $03; // Sleep Mode Select Bits
  223. // MCU Status Register
  224. PORF = $00;
  225. EXTRF = $01;
  226. BORF = $02;
  227. WDRF = $03;
  228. // MCU Control Register
  229. IVCE = $00;
  230. IVSEL = $01;
  231. PUD = $04;
  232. BODSE = $05;
  233. BODS = $06;
  234. // Store Program Memory Control and Status Register
  235. SPMEN = $00;
  236. PGERS = $01;
  237. PGWRT = $02;
  238. BLBSET = $03;
  239. RWWSRE = $04;
  240. SIGRD = $05;
  241. RWWSB = $06;
  242. SPMIE = $07;
  243. // Status Register
  244. C = $00;
  245. Z = $01;
  246. N = $02;
  247. V = $03;
  248. S = $04;
  249. H = $05;
  250. T = $06;
  251. I = $07;
  252. // Watchdog Timer Control Register
  253. WDE = $03;
  254. WDCE = $04;
  255. WDP0 = $00; // Watchdog Timer Prescaler Bits
  256. WDP1 = $01; // Watchdog Timer Prescaler Bits
  257. WDP2 = $02; // Watchdog Timer Prescaler Bits
  258. WDP3 = $05; // Watchdog Timer Prescaler Bits
  259. WDIE = $06;
  260. WDIF = $07;
  261. // Clock Prescale Register
  262. CLKPS0 = $00; // Clock Prescaler Select Bits
  263. CLKPS1 = $01; // Clock Prescaler Select Bits
  264. CLKPS2 = $02; // Clock Prescaler Select Bits
  265. CLKPS3 = $03; // Clock Prescaler Select Bits
  266. CLKPCE = $07;
  267. // Power Reduction Register
  268. PRADC = $00;
  269. PRUSART0 = $01;
  270. PRSPI = $02;
  271. PRTIM1 = $03;
  272. PRTIM0 = $05;
  273. PRTIM2 = $06;
  274. PRTWI = $07;
  275. // Oscillator Calibration Value
  276. OSCCAL0 = $00; // Oscillator Calibration
  277. OSCCAL1 = $01; // Oscillator Calibration
  278. OSCCAL2 = $02; // Oscillator Calibration
  279. OSCCAL3 = $03; // Oscillator Calibration
  280. OSCCAL4 = $04; // Oscillator Calibration
  281. OSCCAL5 = $05; // Oscillator Calibration
  282. OSCCAL6 = $06; // Oscillator Calibration
  283. OSCCAL7 = $07; // Oscillator Calibration
  284. // Pin Change Interrupt Control Register
  285. PCIE0 = $00; // Pin Change Interrupt Enables
  286. PCIE1 = $01; // Pin Change Interrupt Enables
  287. PCIE2 = $02; // Pin Change Interrupt Enables
  288. // External Interrupt Control Register
  289. ISC00 = $00; // External Interrupt Sense Control 0 Bits
  290. ISC01 = $01; // External Interrupt Sense Control 0 Bits
  291. ISC10 = $02; // External Interrupt Sense Control 1 Bits
  292. ISC11 = $03; // External Interrupt Sense Control 1 Bits
  293. // Pin Change Mask Register 2
  294. PCINT16 = $00; // Pin Change Enable Masks
  295. PCINT17 = $01; // Pin Change Enable Masks
  296. PCINT18 = $02; // Pin Change Enable Masks
  297. PCINT19 = $03; // Pin Change Enable Masks
  298. PCINT20 = $04; // Pin Change Enable Masks
  299. PCINT21 = $05; // Pin Change Enable Masks
  300. PCINT22 = $06; // Pin Change Enable Masks
  301. PCINT23 = $07; // Pin Change Enable Masks
  302. // Timer/Counter0 Interrupt Mask Register
  303. TOIE0 = $00;
  304. OCIE0A = $01;
  305. OCIE0B = $02;
  306. // Timer/Counter Interrupt Mask Register
  307. TOIE1 = $00;
  308. OCIE1A = $01;
  309. OCIE1B = $02;
  310. ICIE1 = $05;
  311. // Timer/Counter Interrupt Mask register
  312. TOIE2 = $00;
  313. OCIE2A = $01;
  314. OCIE2B = $02;
  315. // The ADC Control and Status register A
  316. ADPS0 = $00; // ADC Prescaler Select Bits
  317. ADPS1 = $01; // ADC Prescaler Select Bits
  318. ADPS2 = $02; // ADC Prescaler Select Bits
  319. ADIE = $03;
  320. ADIF = $04;
  321. ADATE = $05;
  322. ADSC = $06;
  323. ADEN = $07;
  324. // The ADC Control and Status register B
  325. ADTS0 = $00; // ADC Auto Trigger Source bits
  326. ADTS1 = $01; // ADC Auto Trigger Source bits
  327. ADTS2 = $02; // ADC Auto Trigger Source bits
  328. ACME = $06;
  329. // The ADC multiplexer Selection Register
  330. MUX0 = $00; // Analog Channel Selection Bits
  331. MUX1 = $01; // Analog Channel Selection Bits
  332. MUX2 = $02; // Analog Channel Selection Bits
  333. MUX3 = $03; // Analog Channel Selection Bits
  334. ADLAR = $05;
  335. REFS0 = $06; // Reference Selection Bits
  336. REFS1 = $07; // Reference Selection Bits
  337. // Digital Input Disable Register
  338. ADC0D = $00;
  339. ADC1D = $01;
  340. ADC2D = $02;
  341. ADC3D = $03;
  342. ADC4D = $04;
  343. ADC5D = $05;
  344. // Digital Input Disable Register 1
  345. AIN0D = $00;
  346. AIN1D = $01;
  347. // Timer/Counter1 Control Register A
  348. WGM10 = $00; // Waveform Generation Mode
  349. WGM11 = $01; // Waveform Generation Mode
  350. COM1B0 = $04; // Compare Output Mode 1B, bits
  351. COM1B1 = $05; // Compare Output Mode 1B, bits
  352. COM1A0 = $06; // Compare Output Mode 1A, bits
  353. COM1A1 = $07; // Compare Output Mode 1A, bits
  354. // Timer/Counter1 Control Register B
  355. CS10 = $00; // Prescaler source of Timer/Counter 1
  356. CS11 = $01; // Prescaler source of Timer/Counter 1
  357. CS12 = $02; // Prescaler source of Timer/Counter 1
  358. ICES1 = $06;
  359. ICNC1 = $07;
  360. // Timer/Counter1 Control Register C
  361. FOC1B = $06;
  362. FOC1A = $07;
  363. // Timer/Counter2 Control Register A
  364. WGM20 = $00; // Waveform Genration Mode
  365. WGM21 = $01; // Waveform Genration Mode
  366. COM2B0 = $04; // Compare Output Mode bits
  367. COM2B1 = $05; // Compare Output Mode bits
  368. COM2A0 = $06; // Compare Output Mode bits
  369. COM2A1 = $07; // Compare Output Mode bits
  370. // Timer/Counter2 Control Register B
  371. CS20 = $00; // Clock Select bits
  372. CS21 = $01; // Clock Select bits
  373. CS22 = $02; // Clock Select bits
  374. WGM22 = $03;
  375. FOC2B = $06;
  376. FOC2A = $07;
  377. // Asynchronous Status Register
  378. TCR2BUB = $00;
  379. TCR2AUB = $01;
  380. OCR2BUB = $02;
  381. OCR2AUB = $03;
  382. TCN2UB = $04;
  383. AS2 = $05;
  384. EXCLK = $06;
  385. // TWI Status Register
  386. TWPS0 = $00; // TWI Prescaler
  387. TWPS1 = $01; // TWI Prescaler
  388. TWS3 = $03; // TWI Status
  389. TWS4 = $04; // TWI Status
  390. TWS5 = $05; // TWI Status
  391. TWS6 = $06; // TWI Status
  392. TWS7 = $07; // TWI Status
  393. // TWI (Slave) Address register
  394. TWGCE = $00;
  395. TWA0 = $01; // TWI (Slave) Address register Bits
  396. TWA1 = $02; // TWI (Slave) Address register Bits
  397. TWA2 = $03; // TWI (Slave) Address register Bits
  398. TWA3 = $04; // TWI (Slave) Address register Bits
  399. TWA4 = $05; // TWI (Slave) Address register Bits
  400. TWA5 = $06; // TWI (Slave) Address register Bits
  401. TWA6 = $07; // TWI (Slave) Address register Bits
  402. // TWI Control Register
  403. TWIE = $00;
  404. TWEN = $02;
  405. TWWC = $03;
  406. TWSTO = $04;
  407. TWSTA = $05;
  408. TWEA = $06;
  409. TWINT = $07;
  410. // TWI (Slave) Address Mask Register
  411. TWAM0 = $01;
  412. TWAM1 = $02;
  413. TWAM2 = $03;
  414. TWAM3 = $04;
  415. TWAM4 = $05;
  416. TWAM5 = $06;
  417. TWAM6 = $07;
  418. // USART Control and Status Register A
  419. MPCM0 = $00;
  420. U2X0 = $01;
  421. UPE0 = $02;
  422. DOR0 = $03;
  423. FE0 = $04;
  424. UDRE0 = $05;
  425. TXC0 = $06;
  426. RXC0 = $07;
  427. // USART Control and Status Register B
  428. TXB80 = $00;
  429. RXB80 = $01;
  430. UCSZ02 = $02;
  431. TXEN0 = $03;
  432. RXEN0 = $04;
  433. UDRIE0 = $05;
  434. TXCIE0 = $06;
  435. RXCIE0 = $07;
  436. // USART Control and Status Register C
  437. UCPOL0 = $00;
  438. UCSZ00 = $01; // Character Size - together with UCSZ2 in UCSR0B
  439. UCSZ01 = $02; // Character Size - together with UCSZ2 in UCSR0B
  440. USBS0 = $03;
  441. UPM00 = $04; // Parity Mode Bits
  442. UPM01 = $05; // Parity Mode Bits
  443. UMSEL00 = $06; // USART Mode Select
  444. UMSEL01 = $07; // USART Mode Select
  445. // USART Control and Status Register D
  446. SFDE = $05;
  447. RXS = $06;
  448. RXSIE = $07;
  449. implementation
  450. {$i avrcommon.inc}
  451. procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
  452. procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
  453. procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0
  454. procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 0
  455. procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 5 Pin Change Interrupt Request 1
  456. procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 6 Watchdog Time-out Interrupt
  457. procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 7 Timer/Counter2 Compare Match A
  458. procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 8 Timer/Counter2 Compare Match A
  459. procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 9 Timer/Counter2 Overflow
  460. procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 10 Timer/Counter1 Capture Event
  461. procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 11 Timer/Counter1 Compare Match A
  462. procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 12 Timer/Counter1 Compare Match B
  463. procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 13 Timer/Counter1 Overflow
  464. procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 14 TimerCounter0 Compare Match A
  465. procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 15 TimerCounter0 Compare Match B
  466. procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 16 Timer/Couner0 Overflow
  467. procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 17 SPI Serial Transfer Complete
  468. procedure USART_RX_ISR; external name 'USART_RX_ISR'; // Interrupt 18 USART Rx Complete
  469. procedure USART_UDRE_ISR; external name 'USART_UDRE_ISR'; // Interrupt 19 USART, Data Register Empty
  470. procedure USART_TX_ISR; external name 'USART_TX_ISR'; // Interrupt 20 USART Tx Complete
  471. procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 21 ADC Conversion Complete
  472. procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 22 EEPROM Ready
  473. procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 23 Analog Comparator
  474. procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 24 Two-wire Serial Interface
  475. procedure SPM_Ready_ISR; external name 'SPM_Ready_ISR'; // Interrupt 25 Store Program Memory Read
  476. procedure USART_START_ISR; external name 'USART_START_ISR'; // Interrupt 26 USART Start Edge Interrupt
  477. procedure _FPC_start; assembler; nostackframe;
  478. label
  479. _start;
  480. asm
  481. .init
  482. .globl _start
  483. jmp _start
  484. jmp INT0_ISR
  485. jmp INT1_ISR
  486. jmp PCINT0_ISR
  487. jmp PCINT1_ISR
  488. jmp PCINT2_ISR
  489. jmp WDT_ISR
  490. jmp TIMER2_COMPA_ISR
  491. jmp TIMER2_COMPB_ISR
  492. jmp TIMER2_OVF_ISR
  493. jmp TIMER1_CAPT_ISR
  494. jmp TIMER1_COMPA_ISR
  495. jmp TIMER1_COMPB_ISR
  496. jmp TIMER1_OVF_ISR
  497. jmp TIMER0_COMPA_ISR
  498. jmp TIMER0_COMPB_ISR
  499. jmp TIMER0_OVF_ISR
  500. jmp SPI_STC_ISR
  501. jmp USART_RX_ISR
  502. jmp USART_UDRE_ISR
  503. jmp USART_TX_ISR
  504. jmp ADC_ISR
  505. jmp EE_READY_ISR
  506. jmp ANALOG_COMP_ISR
  507. jmp TWI_ISR
  508. jmp SPM_Ready_ISR
  509. jmp USART_START_ISR
  510. {$i start.inc}
  511. .weak INT0_ISR
  512. .weak INT1_ISR
  513. .weak PCINT0_ISR
  514. .weak PCINT1_ISR
  515. .weak PCINT2_ISR
  516. .weak WDT_ISR
  517. .weak TIMER2_COMPA_ISR
  518. .weak TIMER2_COMPB_ISR
  519. .weak TIMER2_OVF_ISR
  520. .weak TIMER1_CAPT_ISR
  521. .weak TIMER1_COMPA_ISR
  522. .weak TIMER1_COMPB_ISR
  523. .weak TIMER1_OVF_ISR
  524. .weak TIMER0_COMPA_ISR
  525. .weak TIMER0_COMPB_ISR
  526. .weak TIMER0_OVF_ISR
  527. .weak SPI_STC_ISR
  528. .weak USART_RX_ISR
  529. .weak USART_UDRE_ISR
  530. .weak USART_TX_ISR
  531. .weak ADC_ISR
  532. .weak EE_READY_ISR
  533. .weak ANALOG_COMP_ISR
  534. .weak TWI_ISR
  535. .weak SPM_Ready_ISR
  536. .weak USART_START_ISR
  537. .set INT0_ISR, Default_IRQ_handler
  538. .set INT1_ISR, Default_IRQ_handler
  539. .set PCINT0_ISR, Default_IRQ_handler
  540. .set PCINT1_ISR, Default_IRQ_handler
  541. .set PCINT2_ISR, Default_IRQ_handler
  542. .set WDT_ISR, Default_IRQ_handler
  543. .set TIMER2_COMPA_ISR, Default_IRQ_handler
  544. .set TIMER2_COMPB_ISR, Default_IRQ_handler
  545. .set TIMER2_OVF_ISR, Default_IRQ_handler
  546. .set TIMER1_CAPT_ISR, Default_IRQ_handler
  547. .set TIMER1_COMPA_ISR, Default_IRQ_handler
  548. .set TIMER1_COMPB_ISR, Default_IRQ_handler
  549. .set TIMER1_OVF_ISR, Default_IRQ_handler
  550. .set TIMER0_COMPA_ISR, Default_IRQ_handler
  551. .set TIMER0_COMPB_ISR, Default_IRQ_handler
  552. .set TIMER0_OVF_ISR, Default_IRQ_handler
  553. .set SPI_STC_ISR, Default_IRQ_handler
  554. .set USART_RX_ISR, Default_IRQ_handler
  555. .set USART_UDRE_ISR, Default_IRQ_handler
  556. .set USART_TX_ISR, Default_IRQ_handler
  557. .set ADC_ISR, Default_IRQ_handler
  558. .set EE_READY_ISR, Default_IRQ_handler
  559. .set ANALOG_COMP_ISR, Default_IRQ_handler
  560. .set TWI_ISR, Default_IRQ_handler
  561. .set SPM_Ready_ISR, Default_IRQ_handler
  562. .set USART_START_ISR, Default_IRQ_handler
  563. end;
  564. end.