atmega3209.pp 57 KB

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  1. unit ATmega3209;
  2. {$goto on}
  3. interface
  4. type
  5. TAC = object //Analog Comparator
  6. CTRLA: byte; //Control A
  7. Reserved1: byte;
  8. MUXCTRLA: byte; //Mux Control A
  9. Reserved3: byte;
  10. DACREF: byte; //Referance scale control
  11. Reserved5: byte;
  12. INTCTRL: byte; //Interrupt Control
  13. STATUS: byte; //Status
  14. const
  15. // Enable
  16. ENABLEbm = $01;
  17. // AC_HYSMODE
  18. HYSMODEmask = $06;
  19. HYSMODE_OFF = $00;
  20. HYSMODE_10mV = $02;
  21. HYSMODE_25mV = $04;
  22. HYSMODE_50mV = $06;
  23. // AC_INTMODE
  24. INTMODEmask = $30;
  25. INTMODE_BOTHEDGE = $00;
  26. INTMODE_NEGEDGE = $20;
  27. INTMODE_POSEDGE = $30;
  28. // AC_LPMODE
  29. LPMODEmask = $08;
  30. LPMODE_DIS = $00;
  31. LPMODE_EN = $08;
  32. // Output Buffer Enable
  33. OUTENbm = $40;
  34. // Run in Standby Mode
  35. RUNSTDBYbm = $80;
  36. // DAC voltage reference
  37. DATA0bm = $01;
  38. DATA1bm = $02;
  39. DATA2bm = $04;
  40. DATA3bm = $08;
  41. DATA4bm = $10;
  42. DATA5bm = $20;
  43. DATA6bm = $40;
  44. DATA7bm = $80;
  45. // Analog Comparator 0 Interrupt Enable
  46. CMPbm = $01;
  47. // Invert AC Output
  48. INVERTbm = $80;
  49. // AC_MUXNEG
  50. MUXNEGmask = $03;
  51. MUXNEG_PIN0 = $00;
  52. MUXNEG_PIN1 = $01;
  53. MUXNEG_PIN2 = $02;
  54. MUXNEG_DACREF = $03;
  55. // AC_MUXPOS
  56. MUXPOSmask = $18;
  57. MUXPOS_PIN0 = $00;
  58. MUXPOS_PIN1 = $08;
  59. MUXPOS_PIN2 = $10;
  60. MUXPOS_PIN3 = $18;
  61. // Analog Comparator State
  62. STATEbm = $10;
  63. end;
  64. TADC = object //Analog to Digital Converter
  65. CTRLA: byte; //Control A
  66. CTRLB: byte; //Control B
  67. CTRLC: byte; //Control C
  68. CTRLD: byte; //Control D
  69. CTRLE: byte; //Control E
  70. SAMPCTRL: byte; //Sample Control
  71. MUXPOS: byte; //Positive mux input
  72. Reserved7: byte;
  73. COMMAND: byte; //Command
  74. EVCTRL: byte; //Event Control
  75. INTCTRL: byte; //Interrupt Control
  76. INTFLAGS: byte; //Interrupt Flags
  77. DBGCTRL: byte; //Debug Control
  78. TEMP: byte; //Temporary Data
  79. Reserved14: byte;
  80. Reserved15: byte;
  81. RES: word; //ADC Accumulator Result
  82. WINLT: word; //Window comparator low threshold
  83. WINHT: word; //Window comparator high threshold
  84. CALIB: byte; //Calibration
  85. const
  86. // ADC_DUTYCYC
  87. DUTYCYCmask = $01;
  88. DUTYCYC_DUTY50 = $00;
  89. DUTYCYC_DUTY25 = $01;
  90. // Start Conversion Operation
  91. STCONVbm = $01;
  92. // ADC Enable
  93. ENABLEbm = $01;
  94. // ADC Freerun mode
  95. FREERUNbm = $02;
  96. // ADC_RESSEL
  97. RESSELmask = $04;
  98. RESSEL_10BIT = $00;
  99. RESSEL_8BIT = $04;
  100. // Run standby mode
  101. RUNSTBYbm = $80;
  102. // ADC_SAMPNUM
  103. SAMPNUMmask = $07;
  104. SAMPNUM_ACC1 = $00;
  105. SAMPNUM_ACC2 = $01;
  106. SAMPNUM_ACC4 = $02;
  107. SAMPNUM_ACC8 = $03;
  108. SAMPNUM_ACC16 = $04;
  109. SAMPNUM_ACC32 = $05;
  110. SAMPNUM_ACC64 = $06;
  111. // ADC_PRESC
  112. PRESCmask = $07;
  113. PRESC_DIV2 = $00;
  114. PRESC_DIV4 = $01;
  115. PRESC_DIV8 = $02;
  116. PRESC_DIV16 = $03;
  117. PRESC_DIV32 = $04;
  118. PRESC_DIV64 = $05;
  119. PRESC_DIV128 = $06;
  120. PRESC_DIV256 = $07;
  121. // ADC_REFSEL
  122. REFSELmask = $30;
  123. REFSEL_INTREF = $00;
  124. REFSEL_VDDREF = $10;
  125. REFSEL_VREFA = $20;
  126. // Sample Capacitance Selection
  127. SAMPCAPbm = $40;
  128. // ADC_ASDV
  129. ASDVmask = $10;
  130. ASDV_ASVOFF = $00;
  131. ASDV_ASVON = $10;
  132. // ADC_INITDLY
  133. INITDLYmask = $E0;
  134. INITDLY_DLY0 = $00;
  135. INITDLY_DLY16 = $20;
  136. INITDLY_DLY32 = $40;
  137. INITDLY_DLY64 = $60;
  138. INITDLY_DLY128 = $80;
  139. INITDLY_DLY256 = $A0;
  140. // Sampling Delay Selection
  141. SAMPDLY0bm = $01;
  142. SAMPDLY1bm = $02;
  143. SAMPDLY2bm = $04;
  144. SAMPDLY3bm = $08;
  145. // ADC_WINCM
  146. WINCMmask = $07;
  147. WINCM_NONE = $00;
  148. WINCM_BELOW = $01;
  149. WINCM_ABOVE = $02;
  150. WINCM_INSIDE = $03;
  151. WINCM_OUTSIDE = $04;
  152. // Debug run
  153. DBGRUNbm = $01;
  154. // Start Event Input Enable
  155. STARTEIbm = $01;
  156. // Result Ready Interrupt Enable
  157. RESRDYbm = $01;
  158. // Window Comparator Interrupt Enable
  159. WCMPbm = $02;
  160. // ADC_MUXPOS
  161. MUXPOSmask = $1F;
  162. MUXPOS_AIN0 = $00;
  163. MUXPOS_AIN1 = $01;
  164. MUXPOS_AIN2 = $02;
  165. MUXPOS_AIN3 = $03;
  166. MUXPOS_AIN4 = $04;
  167. MUXPOS_AIN5 = $05;
  168. MUXPOS_AIN6 = $06;
  169. MUXPOS_AIN7 = $07;
  170. MUXPOS_AIN8 = $08;
  171. MUXPOS_AIN9 = $09;
  172. MUXPOS_AIN10 = $0A;
  173. MUXPOS_AIN11 = $0B;
  174. MUXPOS_AIN12 = $0C;
  175. MUXPOS_AIN13 = $0D;
  176. MUXPOS_AIN14 = $0E;
  177. MUXPOS_AIN15 = $0F;
  178. MUXPOS_DACREF = $1C;
  179. MUXPOS_TEMPSENSE = $1E;
  180. MUXPOS_GND = $1F;
  181. // Sample lenght
  182. SAMPLEN0bm = $01;
  183. SAMPLEN1bm = $02;
  184. SAMPLEN2bm = $04;
  185. SAMPLEN3bm = $08;
  186. SAMPLEN4bm = $10;
  187. // Temporary
  188. TEMP0bm = $01;
  189. TEMP1bm = $02;
  190. TEMP2bm = $04;
  191. TEMP3bm = $08;
  192. TEMP4bm = $10;
  193. TEMP5bm = $20;
  194. TEMP6bm = $40;
  195. TEMP7bm = $80;
  196. end;
  197. TBOD = object //Bod interface
  198. CTRLA: byte; //Control A
  199. CTRLB: byte; //Control B
  200. Reserved2: byte;
  201. Reserved3: byte;
  202. Reserved4: byte;
  203. Reserved5: byte;
  204. Reserved6: byte;
  205. Reserved7: byte;
  206. VLMCTRLA: byte; //Voltage level monitor Control
  207. INTCTRL: byte; //Voltage level monitor interrupt Control
  208. INTFLAGS: byte; //Voltage level monitor interrupt Flags
  209. STATUS: byte; //Voltage level monitor status
  210. const
  211. // BOD_ACTIVE
  212. ACTIVEmask = $0C;
  213. ACTIVE_DIS = $00;
  214. ACTIVE_ENABLED = $04;
  215. ACTIVE_SAMPLED = $08;
  216. ACTIVE_ENWAKE = $0C;
  217. // BOD_SAMPFREQ
  218. SAMPFREQmask = $10;
  219. SAMPFREQ_1KHZ = $00;
  220. SAMPFREQ_125HZ = $10;
  221. // BOD_SLEEP
  222. SLEEPmask = $03;
  223. SLEEP_DIS = $00;
  224. SLEEP_ENABLED = $01;
  225. SLEEP_SAMPLED = $02;
  226. // BOD_LVL
  227. LVLmask = $07;
  228. LVL_BODLEVEL0 = $00;
  229. LVL_BODLEVEL2 = $02;
  230. LVL_BODLEVEL7 = $07;
  231. // BOD_VLMCFG
  232. VLMCFGmask = $06;
  233. VLMCFG_BELOW = $00;
  234. VLMCFG_ABOVE = $02;
  235. VLMCFG_CROSS = $04;
  236. // voltage level monitor interrrupt enable
  237. VLMIEbm = $01;
  238. // Voltage level monitor interrupt flag
  239. VLMIFbm = $01;
  240. // Voltage level monitor status
  241. VLMSbm = $01;
  242. // BOD_VLMLVL
  243. VLMLVLmask = $03;
  244. VLMLVL_5ABOVE = $00;
  245. VLMLVL_15ABOVE = $01;
  246. VLMLVL_25ABOVE = $02;
  247. end;
  248. TCCL = object //Configurable Custom Logic
  249. CTRLA: byte; //Control Register A
  250. SEQCTRL0: byte; //Sequential Control 0
  251. SEQCTRL1: byte; //Sequential Control 1
  252. Reserved3: byte;
  253. Reserved4: byte;
  254. INTCTRL0: byte; //Interrupt Control 0
  255. Reserved6: byte;
  256. INTFLAGS: byte; //Interrupt Flags
  257. LUT0CTRLA: byte; //LUT Control 0 A
  258. LUT0CTRLB: byte; //LUT Control 0 B
  259. LUT0CTRLC: byte; //LUT Control 0 C
  260. TRUTH0: byte; //Truth 0
  261. LUT1CTRLA: byte; //LUT Control 1 A
  262. LUT1CTRLB: byte; //LUT Control 1 B
  263. LUT1CTRLC: byte; //LUT Control 1 C
  264. TRUTH1: byte; //Truth 1
  265. LUT2CTRLA: byte; //LUT Control 2 A
  266. LUT2CTRLB: byte; //LUT Control 2 B
  267. LUT2CTRLC: byte; //LUT Control 2 C
  268. TRUTH2: byte; //Truth 2
  269. LUT3CTRLA: byte; //LUT Control 3 A
  270. LUT3CTRLB: byte; //LUT Control 3 B
  271. LUT3CTRLC: byte; //LUT Control 3 C
  272. TRUTH3: byte; //Truth 3
  273. const
  274. // Enable
  275. ENABLEbm = $01;
  276. // Run in Standby
  277. RUNSTDBYbm = $40;
  278. // CCL_INTMODE0
  279. INTMODE0mask = $03;
  280. INTMODE0_INTDISABLE = $00;
  281. INTMODE0_RISING = $01;
  282. INTMODE0_FALLING = $02;
  283. INTMODE0_BOTH = $03;
  284. // CCL_INTMODE1
  285. INTMODE1mask = $0C;
  286. INTMODE1_INTDISABLE = $00;
  287. INTMODE1_RISING = $04;
  288. INTMODE1_FALLING = $08;
  289. INTMODE1_BOTH = $0C;
  290. // CCL_INTMODE2
  291. INTMODE2mask = $30;
  292. INTMODE2_INTDISABLE = $00;
  293. INTMODE2_RISING = $10;
  294. INTMODE2_FALLING = $20;
  295. INTMODE2_BOTH = $30;
  296. // CCL_INTMODE3
  297. INTMODE3mask = $C0;
  298. INTMODE3_INTDISABLE = $00;
  299. INTMODE3_RISING = $40;
  300. INTMODE3_FALLING = $80;
  301. INTMODE3_BOTH = $C0;
  302. // Interrupt Flags
  303. INT0bm = $01;
  304. INT1bm = $02;
  305. INT2bm = $04;
  306. INT3bm = $08;
  307. // CCL_CLKSRC
  308. CLKSRCmask = $0E;
  309. CLKSRC_CLKPER = $00;
  310. CLKSRC_IN2 = $02;
  311. CLKSRC_OSC20M = $08;
  312. CLKSRC_OSCULP32K = $0A;
  313. CLKSRC_OSCULP1K = $0C;
  314. // CCL_EDGEDET
  315. EDGEDETmask = $80;
  316. EDGEDET_DIS = $00;
  317. EDGEDET_EN = $80;
  318. // CCL_FILTSEL
  319. FILTSELmask = $30;
  320. FILTSEL_DISABLE = $00;
  321. FILTSEL_SYNCH = $10;
  322. FILTSEL_FILTER = $20;
  323. // Output Enable
  324. OUTENbm = $40;
  325. // CCL_INSEL0
  326. INSEL0mask = $0F;
  327. INSEL0_MASK = $00;
  328. INSEL0_FEEDBACK = $01;
  329. INSEL0_LINK = $02;
  330. INSEL0_EVENTA = $03;
  331. INSEL0_EVENTB = $04;
  332. INSEL0_IO = $05;
  333. INSEL0_AC0 = $06;
  334. INSEL0_USART0 = $08;
  335. INSEL0_SPI0 = $09;
  336. INSEL0_TCA0 = $0A;
  337. INSEL0_TCB0 = $0C;
  338. // CCL_INSEL1
  339. INSEL1mask = $F0;
  340. INSEL1_MASK = $00;
  341. INSEL1_FEEDBACK = $10;
  342. INSEL1_LINK = $20;
  343. INSEL1_EVENTA = $30;
  344. INSEL1_EVENTB = $40;
  345. INSEL1_IO = $50;
  346. INSEL1_AC0 = $60;
  347. INSEL1_USART1 = $80;
  348. INSEL1_SPI0 = $90;
  349. INSEL1_TCA0 = $A0;
  350. INSEL1_TCB1 = $C0;
  351. // CCL_INSEL2
  352. INSEL2mask = $0F;
  353. INSEL2_MASK = $00;
  354. INSEL2_FEEDBACK = $01;
  355. INSEL2_LINK = $02;
  356. INSEL2_EVENTA = $03;
  357. INSEL2_EVENTB = $04;
  358. INSEL2_IO = $05;
  359. INSEL2_AC0 = $06;
  360. INSEL2_USART2 = $08;
  361. INSEL2_SPI0 = $09;
  362. INSEL2_TCA0 = $0A;
  363. INSEL2_TCB2 = $0C;
  364. // CCL_SEQSEL0
  365. SEQSEL0mask = $07;
  366. SEQSEL0_DISABLE = $00;
  367. SEQSEL0_DFF = $01;
  368. SEQSEL0_JK = $02;
  369. SEQSEL0_LATCH = $03;
  370. SEQSEL0_RS = $04;
  371. // CCL_SEQSEL1
  372. SEQSEL1mask = $07;
  373. SEQSEL1_DISABLE = $00;
  374. SEQSEL1_DFF = $01;
  375. SEQSEL1_JK = $02;
  376. SEQSEL1_LATCH = $03;
  377. SEQSEL1_RS = $04;
  378. end;
  379. TCLKCTRL = object //Clock controller
  380. MCLKCTRLA: byte; //MCLK Control A
  381. MCLKCTRLB: byte; //MCLK Control B
  382. MCLKLOCK: byte; //MCLK Lock
  383. MCLKSTATUS: byte; //MCLK Status
  384. Reserved4: byte;
  385. Reserved5: byte;
  386. Reserved6: byte;
  387. Reserved7: byte;
  388. Reserved8: byte;
  389. Reserved9: byte;
  390. Reserved10: byte;
  391. Reserved11: byte;
  392. Reserved12: byte;
  393. Reserved13: byte;
  394. Reserved14: byte;
  395. Reserved15: byte;
  396. OSC20MCTRLA: byte; //OSC20M Control A
  397. OSC20MCALIBA: byte; //OSC20M Calibration A
  398. OSC20MCALIBB: byte; //OSC20M Calibration B
  399. Reserved19: byte;
  400. Reserved20: byte;
  401. Reserved21: byte;
  402. Reserved22: byte;
  403. Reserved23: byte;
  404. OSC32KCTRLA: byte; //OSC32K Control A
  405. Reserved25: byte;
  406. Reserved26: byte;
  407. Reserved27: byte;
  408. XOSC32KCTRLA: byte; //XOSC32K Control A
  409. const
  410. // System clock out
  411. CLKOUTbm = $80;
  412. // CLKCTRL_CLKSEL
  413. CLKSELmask = $03;
  414. CLKSEL_OSC20M = $00;
  415. CLKSEL_OSCULP32K = $01;
  416. CLKSEL_XOSC32K = $02;
  417. CLKSEL_EXTCLK = $03;
  418. // CLKCTRL_PDIV
  419. PDIVmask = $1E;
  420. PDIV_2X = $00;
  421. PDIV_4X = $02;
  422. PDIV_8X = $04;
  423. PDIV_16X = $06;
  424. PDIV_32X = $08;
  425. PDIV_64X = $0A;
  426. PDIV_6X = $10;
  427. PDIV_10X = $12;
  428. PDIV_12X = $14;
  429. PDIV_24X = $16;
  430. PDIV_48X = $18;
  431. // Prescaler enable
  432. PENbm = $01;
  433. // lock ebable
  434. LOCKENbm = $01;
  435. // External Clock status
  436. EXTSbm = $80;
  437. // 20MHz oscillator status
  438. OSC20MSbm = $10;
  439. // 32KHz oscillator status
  440. OSC32KSbm = $20;
  441. // System Oscillator changing
  442. SOSCbm = $01;
  443. // 32.768 kHz Crystal Oscillator status
  444. XOSC32KSbm = $40;
  445. // Calibration
  446. CAL20M0bm = $01;
  447. CAL20M1bm = $02;
  448. CAL20M2bm = $04;
  449. CAL20M3bm = $08;
  450. CAL20M4bm = $10;
  451. CAL20M5bm = $20;
  452. CAL20M6bm = $40;
  453. // Lock
  454. LOCKbm = $80;
  455. // Oscillator temperature coefficient
  456. TEMPCAL20M0bm = $01;
  457. TEMPCAL20M1bm = $02;
  458. TEMPCAL20M2bm = $04;
  459. TEMPCAL20M3bm = $08;
  460. // Run standby
  461. RUNSTDBYbm = $02;
  462. // CLKCTRL_CSUT
  463. CSUTmask = $30;
  464. CSUT_1K = $00;
  465. CSUT_16K = $10;
  466. CSUT_32K = $20;
  467. CSUT_64K = $30;
  468. // Enable
  469. ENABLEbm = $01;
  470. // Select
  471. SELbm = $04;
  472. end;
  473. TCPU = object //CPU
  474. Reserved0: byte;
  475. Reserved1: byte;
  476. Reserved2: byte;
  477. Reserved3: byte;
  478. CCP: byte; //Configuration Change Protection
  479. Reserved5: byte;
  480. Reserved6: byte;
  481. Reserved7: byte;
  482. Reserved8: byte;
  483. Reserved9: byte;
  484. Reserved10: byte;
  485. Reserved11: byte;
  486. Reserved12: byte;
  487. SPL: byte; //Stack Pointer Low
  488. SPH: byte; //Stack Pointer High
  489. SREG: byte; //Status Register
  490. const
  491. // CPU_CCP
  492. CCPmask = $FF;
  493. CCP_SPM = $9D;
  494. CCP_IOREG = $D8;
  495. // Carry Flag
  496. Cbm = $01;
  497. // Half Carry Flag
  498. Hbm = $20;
  499. // Global Interrupt Enable Flag
  500. Ibm = $80;
  501. // Negative Flag
  502. Nbm = $04;
  503. // N Exclusive Or V Flag
  504. Sbm = $10;
  505. // Transfer Bit
  506. Tbm = $40;
  507. // Two's Complement Overflow Flag
  508. Vbm = $08;
  509. // Zero Flag
  510. Zbm = $02;
  511. end;
  512. TCPUINT = object //Interrupt Controller
  513. CTRLA: byte; //Control A
  514. STATUS: byte; //Status
  515. LVL0PRI: byte; //Interrupt Level 0 Priority
  516. LVL1VEC: byte; //Interrupt Level 1 Priority Vector
  517. const
  518. // Compact Vector Table
  519. CVTbm = $20;
  520. // Interrupt Vector Select
  521. IVSELbm = $40;
  522. // Round-robin Scheduling Enable
  523. LVL0RRbm = $01;
  524. // Interrupt Level Priority
  525. LVL0PRI0bm = $01;
  526. LVL0PRI1bm = $02;
  527. LVL0PRI2bm = $04;
  528. LVL0PRI3bm = $08;
  529. LVL0PRI4bm = $10;
  530. LVL0PRI5bm = $20;
  531. LVL0PRI6bm = $40;
  532. LVL0PRI7bm = $80;
  533. // Interrupt Vector with High Priority
  534. LVL1VEC0bm = $01;
  535. LVL1VEC1bm = $02;
  536. LVL1VEC2bm = $04;
  537. LVL1VEC3bm = $08;
  538. LVL1VEC4bm = $10;
  539. LVL1VEC5bm = $20;
  540. LVL1VEC6bm = $40;
  541. LVL1VEC7bm = $80;
  542. // Level 0 Interrupt Executing
  543. LVL0EXbm = $01;
  544. // Level 1 Interrupt Executing
  545. LVL1EXbm = $02;
  546. // Non-maskable Interrupt Executing
  547. NMIEXbm = $80;
  548. end;
  549. TCRCSCAN = object //CRCSCAN
  550. CTRLA: byte; //Control A
  551. CTRLB: byte; //Control B
  552. STATUS: byte; //Status
  553. const
  554. // Enable CRC scan
  555. ENABLEbm = $01;
  556. // Enable NMI Trigger
  557. NMIENbm = $02;
  558. // Reset CRC scan
  559. RESETbm = $80;
  560. // CRCSCAN_SRC
  561. SRCmask = $03;
  562. SRC_FLASH = $00;
  563. SRC_APPLICATION = $01;
  564. SRC_BOOT = $02;
  565. // CRC Busy
  566. BUSYbm = $01;
  567. // CRC Ok
  568. OKbm = $02;
  569. end;
  570. TEVSYS = object //Event System
  571. STROBE: byte; //Channel Strobe
  572. Reserved1: byte;
  573. Reserved2: byte;
  574. Reserved3: byte;
  575. Reserved4: byte;
  576. Reserved5: byte;
  577. Reserved6: byte;
  578. Reserved7: byte;
  579. Reserved8: byte;
  580. Reserved9: byte;
  581. Reserved10: byte;
  582. Reserved11: byte;
  583. Reserved12: byte;
  584. Reserved13: byte;
  585. Reserved14: byte;
  586. Reserved15: byte;
  587. CHANNEL0: byte; //Multiplexer Channel 0
  588. CHANNEL1: byte; //Multiplexer Channel 1
  589. CHANNEL2: byte; //Multiplexer Channel 2
  590. CHANNEL3: byte; //Multiplexer Channel 3
  591. CHANNEL4: byte; //Multiplexer Channel 4
  592. CHANNEL5: byte; //Multiplexer Channel 5
  593. CHANNEL6: byte; //Multiplexer Channel 6
  594. CHANNEL7: byte; //Multiplexer Channel 7
  595. Reserved24: byte;
  596. Reserved25: byte;
  597. Reserved26: byte;
  598. Reserved27: byte;
  599. Reserved28: byte;
  600. Reserved29: byte;
  601. Reserved30: byte;
  602. Reserved31: byte;
  603. USERCCLLUT0A: byte; //User CCL LUT0 Event A
  604. USERCCLLUT0B: byte; //User CCL LUT0 Event B
  605. USERCCLLUT1A: byte; //User CCL LUT1 Event A
  606. USERCCLLUT1B: byte; //User CCL LUT1 Event B
  607. USERCCLLUT2A: byte; //User CCL LUT2 Event A
  608. USERCCLLUT2B: byte; //User CCL LUT2 Event B
  609. USERCCLLUT3A: byte; //User CCL LUT3 Event A
  610. USERCCLLUT3B: byte; //User CCL LUT3 Event B
  611. USERADC0: byte; //User ADC0
  612. USEREVOUTA: byte; //User EVOUT Port A
  613. USEREVOUTB: byte; //User EVOUT Port B
  614. USEREVOUTC: byte; //User EVOUT Port C
  615. USEREVOUTD: byte; //User EVOUT Port D
  616. USEREVOUTE: byte; //User EVOUT Port E
  617. USEREVOUTF: byte; //User EVOUT Port F
  618. USERUSART0: byte; //User USART0
  619. USERUSART1: byte; //User USART1
  620. USERUSART2: byte; //User USART2
  621. USERUSART3: byte; //User USART3
  622. USERTCA0: byte; //User TCA0
  623. USERTCB0: byte; //User TCB0
  624. USERTCB1: byte; //User TCB1
  625. USERTCB2: byte; //User TCB2
  626. USERTCB3: byte; //User TCB3
  627. const
  628. // EVSYS_GENERATOR
  629. GENERATORmask = $FF;
  630. GENERATOR_OFF = $00;
  631. GENERATOR_UPDI = $01;
  632. GENERATOR_RTC_OVF = $06;
  633. GENERATOR_RTC_CMP = $07;
  634. GENERATOR_RTC_PIT0 = $08;
  635. GENERATOR_RTC_PIT1 = $09;
  636. GENERATOR_RTC_PIT2 = $0A;
  637. GENERATOR_RTC_PIT3 = $0B;
  638. GENERATOR_CCL_LUT0 = $10;
  639. GENERATOR_CCL_LUT1 = $11;
  640. GENERATOR_CCL_LUT2 = $12;
  641. GENERATOR_CCL_LUT3 = $13;
  642. GENERATOR_AC0_OUT = $20;
  643. GENERATOR_ADC0_RESRDY = $24;
  644. GENERATOR_PORT0_PIN0 = $40;
  645. GENERATOR_PORT0_PIN1 = $41;
  646. GENERATOR_PORT0_PIN2 = $42;
  647. GENERATOR_PORT0_PIN3 = $43;
  648. GENERATOR_PORT0_PIN4 = $44;
  649. GENERATOR_PORT0_PIN5 = $45;
  650. GENERATOR_PORT0_PIN6 = $46;
  651. GENERATOR_PORT0_PIN7 = $47;
  652. GENERATOR_PORT1_PIN0 = $48;
  653. GENERATOR_PORT1_PIN1 = $49;
  654. GENERATOR_PORT1_PIN2 = $4A;
  655. GENERATOR_PORT1_PIN3 = $4B;
  656. GENERATOR_PORT1_PIN4 = $4C;
  657. GENERATOR_PORT1_PIN5 = $4D;
  658. GENERATOR_PORT1_PIN6 = $4E;
  659. GENERATOR_PORT1_PIN7 = $4F;
  660. GENERATOR_USART0_XCK = $60;
  661. GENERATOR_USART1_XCK = $61;
  662. GENERATOR_USART2_XCK = $62;
  663. GENERATOR_USART3_XCK = $63;
  664. GENERATOR_SPI0_SCK = $68;
  665. GENERATOR_TCA0_OVF_LUNF = $80;
  666. GENERATOR_TCA0_HUNF = $81;
  667. GENERATOR_TCA0_CMP0 = $84;
  668. GENERATOR_TCA0_CMP1 = $85;
  669. GENERATOR_TCA0_CMP2 = $86;
  670. GENERATOR_TCB0_CAPT = $A0;
  671. GENERATOR_TCB1_CAPT = $A2;
  672. GENERATOR_TCB2_CAPT = $A4;
  673. GENERATOR_TCB3_CAPT = $A6;
  674. // EVSYS_STROBE0
  675. STROBE0mask = $FF;
  676. STROBE0_EV_STROBE_CH0 = $01;
  677. STROBE0_EV_STROBE_CH1 = $02;
  678. STROBE0_EV_STROBE_CH2 = $04;
  679. STROBE0_EV_STROBE_CH3 = $08;
  680. STROBE0_EV_STROBE_CH4 = $10;
  681. STROBE0_EV_STROBE_CH5 = $20;
  682. STROBE0_EV_STROBE_CH6 = $40;
  683. STROBE0_EV_STROBE_CH7 = $80;
  684. // EVSYS_CHANNEL
  685. CHANNELmask = $FF;
  686. CHANNEL_OFF = $00;
  687. CHANNEL_CHANNEL0 = $01;
  688. CHANNEL_CHANNEL1 = $02;
  689. CHANNEL_CHANNEL2 = $03;
  690. CHANNEL_CHANNEL3 = $04;
  691. CHANNEL_CHANNEL4 = $05;
  692. CHANNEL_CHANNEL5 = $06;
  693. CHANNEL_CHANNEL6 = $07;
  694. CHANNEL_CHANNEL7 = $08;
  695. end;
  696. TFUSE = object //Fuses
  697. WDTCFG: byte; //Watchdog Configuration
  698. BODCFG: byte; //BOD Configuration
  699. OSCCFG: byte; //Oscillator Configuration
  700. Reserved3: byte;
  701. Reserved4: byte;
  702. SYSCFG0: byte; //System Configuration 0
  703. SYSCFG1: byte; //System Configuration 1
  704. APPEND: byte; //Application Code Section End
  705. BOOTEND: byte; //Boot Section End
  706. const
  707. // FUSE_ACTIVE
  708. ACTIVEmask = $0C;
  709. ACTIVE_DIS = $00;
  710. ACTIVE_ENABLED = $04;
  711. ACTIVE_SAMPLED = $08;
  712. ACTIVE_ENWAKE = $0C;
  713. // FUSE_LVL
  714. LVLmask = $E0;
  715. LVL_BODLEVEL0 = $00;
  716. LVL_BODLEVEL2 = $40;
  717. LVL_BODLEVEL7 = $E0;
  718. // FUSE_SAMPFREQ
  719. SAMPFREQmask = $10;
  720. SAMPFREQ_1KHZ = $00;
  721. SAMPFREQ_125HZ = $10;
  722. // FUSE_SLEEP
  723. SLEEPmask = $03;
  724. SLEEP_DIS = $00;
  725. SLEEP_ENABLED = $01;
  726. SLEEP_SAMPLED = $02;
  727. // FUSE_FREQSEL
  728. FREQSELmask = $03;
  729. FREQSEL_16MHZ = $01;
  730. FREQSEL_20MHZ = $02;
  731. // Oscillator Lock
  732. OSCLOCKbm = $80;
  733. // FUSE_CRCSRC
  734. CRCSRCmask = $C0;
  735. CRCSRC_FLASH = $00;
  736. CRCSRC_BOOT = $40;
  737. CRCSRC_BOOTAPP = $80;
  738. CRCSRC_NOCRC = $C0;
  739. // EEPROM Save
  740. EESAVEbm = $01;
  741. // FUSE_RSTPINCFG
  742. RSTPINCFGmask = $08;
  743. RSTPINCFG_GPIO = $00;
  744. RSTPINCFG_RST = $08;
  745. // FUSE_SUT
  746. SUTmask = $07;
  747. SUT_0MS = $00;
  748. SUT_1MS = $01;
  749. SUT_2MS = $02;
  750. SUT_4MS = $03;
  751. SUT_8MS = $04;
  752. SUT_16MS = $05;
  753. SUT_32MS = $06;
  754. SUT_64MS = $07;
  755. // FUSE_PERIOD
  756. PERIODmask = $0F;
  757. PERIOD_OFF = $00;
  758. PERIOD_8CLK = $01;
  759. PERIOD_16CLK = $02;
  760. PERIOD_32CLK = $03;
  761. PERIOD_64CLK = $04;
  762. PERIOD_128CLK = $05;
  763. PERIOD_256CLK = $06;
  764. PERIOD_512CLK = $07;
  765. PERIOD_1KCLK = $08;
  766. PERIOD_2KCLK = $09;
  767. PERIOD_4KCLK = $0A;
  768. PERIOD_8KCLK = $0B;
  769. // FUSE_WINDOW
  770. WINDOWmask = $F0;
  771. WINDOW_OFF = $00;
  772. WINDOW_8CLK = $10;
  773. WINDOW_16CLK = $20;
  774. WINDOW_32CLK = $30;
  775. WINDOW_64CLK = $40;
  776. WINDOW_128CLK = $50;
  777. WINDOW_256CLK = $60;
  778. WINDOW_512CLK = $70;
  779. WINDOW_1KCLK = $80;
  780. WINDOW_2KCLK = $90;
  781. WINDOW_4KCLK = $A0;
  782. WINDOW_8KCLK = $B0;
  783. end;
  784. TGPIO = object //General Purpose IO
  785. GPIOR0: byte; //General Purpose IO Register 0
  786. GPIOR1: byte; //General Purpose IO Register 1
  787. GPIOR2: byte; //General Purpose IO Register 2
  788. GPIOR3: byte; //General Purpose IO Register 3
  789. end;
  790. TLOCKBIT = object //Lockbit
  791. LOCKBIT: byte; //Lock Bits
  792. const
  793. // LOCKBIT_LB
  794. LBmask = $FF;
  795. LB_RWLOCK = $3A;
  796. LB_NOLOCK = $C5;
  797. end;
  798. TNVMCTRL = object //Non-volatile Memory Controller
  799. CTRLA: byte; //Control A
  800. CTRLB: byte; //Control B
  801. STATUS: byte; //Status
  802. INTCTRL: byte; //Interrupt Control
  803. INTFLAGS: byte; //Interrupt Flags
  804. Reserved5: byte;
  805. DATA: word; //Data
  806. ADDR: word; //Address
  807. const
  808. // NVMCTRL_CMD
  809. CMDmask = $07;
  810. CMD_NONE = $00;
  811. CMD_PAGEWRITE = $01;
  812. CMD_PAGEERASE = $02;
  813. CMD_PAGEERASEWRITE = $03;
  814. CMD_PAGEBUFCLR = $04;
  815. CMD_CHIPERASE = $05;
  816. CMD_EEERASE = $06;
  817. CMD_FUSEWRITE = $07;
  818. // Application code write protect
  819. APCWPbm = $01;
  820. // Boot Lock
  821. BOOTLOCKbm = $02;
  822. // EEPROM Ready
  823. EEREADYbm = $01;
  824. // EEPROM busy
  825. EEBUSYbm = $02;
  826. // Flash busy
  827. FBUSYbm = $01;
  828. // Write error
  829. WRERRORbm = $04;
  830. end;
  831. TPORT = object //I/O Ports
  832. DIR: byte; //Data Direction
  833. DIRSET: byte; //Data Direction Set
  834. DIRCLR: byte; //Data Direction Clear
  835. DIRTGL: byte; //Data Direction Toggle
  836. OUT_: byte; //Output Value
  837. OUTSET: byte; //Output Value Set
  838. OUTCLR: byte; //Output Value Clear
  839. OUTTGL: byte; //Output Value Toggle
  840. IN_: byte; //Input Value
  841. INTFLAGS: byte; //Interrupt Flags
  842. PORTCTRL: byte; //Port Control
  843. Reserved11: byte;
  844. Reserved12: byte;
  845. Reserved13: byte;
  846. Reserved14: byte;
  847. Reserved15: byte;
  848. PIN0CTRL: byte; //Pin 0 Control
  849. PIN1CTRL: byte; //Pin 1 Control
  850. PIN2CTRL: byte; //Pin 2 Control
  851. PIN3CTRL: byte; //Pin 3 Control
  852. PIN4CTRL: byte; //Pin 4 Control
  853. PIN5CTRL: byte; //Pin 5 Control
  854. PIN6CTRL: byte; //Pin 6 Control
  855. PIN7CTRL: byte; //Pin 7 Control
  856. const
  857. // Pin Interrupt
  858. INT0bm = $01;
  859. INT1bm = $02;
  860. INT2bm = $04;
  861. INT3bm = $08;
  862. INT4bm = $10;
  863. INT5bm = $20;
  864. INT6bm = $40;
  865. INT7bm = $80;
  866. // Inverted I/O Enable
  867. INVENbm = $80;
  868. // PORT_ISC
  869. ISCmask = $07;
  870. ISC_INTDISABLE = $00;
  871. ISC_BOTHEDGES = $01;
  872. ISC_RISING = $02;
  873. ISC_FALLING = $03;
  874. ISC_INPUT_DISABLE = $04;
  875. ISC_LEVEL = $05;
  876. // Pullup enable
  877. PULLUPENbm = $08;
  878. // Slew Rate Limit Enable
  879. SRLbm = $01;
  880. end;
  881. TPORTMUX = object //Port Multiplexer
  882. EVSYSROUTEA: byte; //Port Multiplexer EVSYS
  883. CCLROUTEA: byte; //Port Multiplexer CCL
  884. USARTROUTEA: byte; //Port Multiplexer USART register A
  885. TWISPIROUTEA: byte; //Port Multiplexer TWI and SPI
  886. TCAROUTEA: byte; //Port Multiplexer TCA
  887. TCBROUTEA: byte; //Port Multiplexer TCB
  888. const
  889. // CCL LUT0
  890. LUT0bm = $01;
  891. // CCL LUT1
  892. LUT1bm = $02;
  893. // CCL LUT2
  894. LUT2bm = $04;
  895. // CCL LUT3
  896. LUT3bm = $08;
  897. // Event Output 0
  898. EVOUT0bm = $01;
  899. // Event Output 1
  900. EVOUT1bm = $02;
  901. // Event Output 2
  902. EVOUT2bm = $04;
  903. // Event Output 3
  904. EVOUT3bm = $08;
  905. // Event Output 4
  906. EVOUT4bm = $10;
  907. // Event Output 5
  908. EVOUT5bm = $20;
  909. // PORTMUX_TCA0
  910. TCA0mask = $07;
  911. TCA0_PORTA = $00;
  912. TCA0_PORTB = $01;
  913. TCA0_PORTC = $02;
  914. TCA0_PORTD = $03;
  915. TCA0_PORTE = $04;
  916. TCA0_PORTF = $05;
  917. // Port Multiplexer TCB0
  918. TCB0bm = $01;
  919. // Port Multiplexer TCB1
  920. TCB1bm = $02;
  921. // Port Multiplexer TCB2
  922. TCB2bm = $04;
  923. // Port Multiplexer TCB3
  924. TCB3bm = $08;
  925. // PORTMUX_SPI0
  926. SPI0mask = $03;
  927. SPI0_DEFAULT = $00;
  928. SPI0_ALT1 = $01;
  929. SPI0_ALT2 = $02;
  930. SPI0_NONE = $03;
  931. // PORTMUX_TWI0
  932. TWI0mask = $30;
  933. TWI0_DEFAULT = $00;
  934. TWI0_ALT1 = $10;
  935. TWI0_ALT2 = $20;
  936. TWI0_NONE = $30;
  937. // PORTMUX_USART0
  938. USART0mask = $03;
  939. USART0_DEFAULT = $00;
  940. USART0_ALT1 = $01;
  941. USART0_NONE = $03;
  942. // PORTMUX_USART1
  943. USART1mask = $0C;
  944. USART1_DEFAULT = $00;
  945. USART1_ALT1 = $04;
  946. USART1_NONE = $0C;
  947. // PORTMUX_USART2
  948. USART2mask = $30;
  949. USART2_DEFAULT = $00;
  950. USART2_ALT1 = $10;
  951. USART2_NONE = $30;
  952. // PORTMUX_USART3
  953. USART3mask = $C0;
  954. USART3_DEFAULT = $00;
  955. USART3_ALT1 = $40;
  956. USART3_NONE = $C0;
  957. end;
  958. TRSTCTRL = object //Reset controller
  959. RSTFR: byte; //Reset Flags
  960. SWRR: byte; //Software Reset
  961. const
  962. // Brown out detector Reset flag
  963. BORFbm = $02;
  964. // External Reset flag
  965. EXTRFbm = $04;
  966. // Power on Reset flag
  967. PORFbm = $01;
  968. // Software Reset flag
  969. SWRFbm = $10;
  970. // UPDI Reset flag
  971. UPDIRFbm = $20;
  972. // Watch dog Reset flag
  973. WDRFbm = $08;
  974. // Software reset enable
  975. SWREbm = $01;
  976. end;
  977. TRTC = object //Real-Time Counter
  978. CTRLA: byte; //Control A
  979. STATUS: byte; //Status
  980. INTCTRL: byte; //Interrupt Control
  981. INTFLAGS: byte; //Interrupt Flags
  982. TEMP: byte; //Temporary
  983. DBGCTRL: byte; //Debug control
  984. CALIB: byte; //Calibration
  985. CLKSEL: byte; //Clock Select
  986. CNT: word; //Counter
  987. PER: word; //Period
  988. CMP: word; //Compare
  989. Reserved14: byte;
  990. Reserved15: byte;
  991. PITCTRLA: byte; //PIT Control A
  992. PITSTATUS: byte; //PIT Status
  993. PITINTCTRL: byte; //PIT Interrupt Control
  994. PITINTFLAGS: byte; //PIT Interrupt Flags
  995. Reserved20: byte;
  996. PITDBGCTRL: byte; //PIT Debug control
  997. const
  998. // Error Correction Value
  999. ERROR0bm = $01;
  1000. ERROR1bm = $02;
  1001. ERROR2bm = $04;
  1002. ERROR3bm = $08;
  1003. ERROR4bm = $10;
  1004. ERROR5bm = $20;
  1005. ERROR6bm = $40;
  1006. // Error Correction Sign Bit
  1007. SIGNbm = $80;
  1008. // RTC_CLKSEL
  1009. CLKSELmask = $03;
  1010. CLKSEL_INT32K = $00;
  1011. CLKSEL_INT1K = $01;
  1012. CLKSEL_TOSC32K = $02;
  1013. CLKSEL_EXTCLK = $03;
  1014. // Correction enable
  1015. CORRENbm = $04;
  1016. // RTC_PRESCALER
  1017. PRESCALERmask = $78;
  1018. PRESCALER_DIV1 = $00;
  1019. PRESCALER_DIV2 = $08;
  1020. PRESCALER_DIV4 = $10;
  1021. PRESCALER_DIV8 = $18;
  1022. PRESCALER_DIV16 = $20;
  1023. PRESCALER_DIV32 = $28;
  1024. PRESCALER_DIV64 = $30;
  1025. PRESCALER_DIV128 = $38;
  1026. PRESCALER_DIV256 = $40;
  1027. PRESCALER_DIV512 = $48;
  1028. PRESCALER_DIV1024 = $50;
  1029. PRESCALER_DIV2048 = $58;
  1030. PRESCALER_DIV4096 = $60;
  1031. PRESCALER_DIV8192 = $68;
  1032. PRESCALER_DIV16384 = $70;
  1033. PRESCALER_DIV32768 = $78;
  1034. // Enable
  1035. RTCENbm = $01;
  1036. // Run In Standby
  1037. RUNSTDBYbm = $80;
  1038. // Run in debug
  1039. DBGRUNbm = $01;
  1040. // Compare Match Interrupt enable
  1041. CMPbm = $02;
  1042. // Overflow Interrupt enable
  1043. OVFbm = $01;
  1044. // RTC_PERIOD
  1045. PERIODmask = $78;
  1046. PERIOD_OFF = $00;
  1047. PERIOD_CYC4 = $08;
  1048. PERIOD_CYC8 = $10;
  1049. PERIOD_CYC16 = $18;
  1050. PERIOD_CYC32 = $20;
  1051. PERIOD_CYC64 = $28;
  1052. PERIOD_CYC128 = $30;
  1053. PERIOD_CYC256 = $38;
  1054. PERIOD_CYC512 = $40;
  1055. PERIOD_CYC1024 = $48;
  1056. PERIOD_CYC2048 = $50;
  1057. PERIOD_CYC4096 = $58;
  1058. PERIOD_CYC8192 = $60;
  1059. PERIOD_CYC16384 = $68;
  1060. PERIOD_CYC32768 = $70;
  1061. // Enable
  1062. PITENbm = $01;
  1063. // Periodic Interrupt
  1064. PIbm = $01;
  1065. // CTRLA Synchronization Busy Flag
  1066. CTRLBUSYbm = $01;
  1067. // Comparator Synchronization Busy Flag
  1068. CMPBUSYbm = $08;
  1069. // Count Synchronization Busy Flag
  1070. CNTBUSYbm = $02;
  1071. // CTRLA Synchronization Busy Flag
  1072. CTRLABUSYbm = $01;
  1073. // Period Synchronization Busy Flag
  1074. PERBUSYbm = $04;
  1075. end;
  1076. TSIGROW = object //Signature row
  1077. DEVICEID0: byte; //Device ID Byte 0
  1078. DEVICEID1: byte; //Device ID Byte 1
  1079. DEVICEID2: byte; //Device ID Byte 2
  1080. SERNUM0: byte; //Serial Number Byte 0
  1081. SERNUM1: byte; //Serial Number Byte 1
  1082. SERNUM2: byte; //Serial Number Byte 2
  1083. SERNUM3: byte; //Serial Number Byte 3
  1084. SERNUM4: byte; //Serial Number Byte 4
  1085. SERNUM5: byte; //Serial Number Byte 5
  1086. SERNUM6: byte; //Serial Number Byte 6
  1087. SERNUM7: byte; //Serial Number Byte 7
  1088. SERNUM8: byte; //Serial Number Byte 8
  1089. SERNUM9: byte; //Serial Number Byte 9
  1090. Reserved13: byte;
  1091. Reserved14: byte;
  1092. Reserved15: byte;
  1093. Reserved16: byte;
  1094. Reserved17: byte;
  1095. Reserved18: byte;
  1096. Reserved19: byte;
  1097. OSCCAL32K: byte; //Oscillator Calibration for 32kHz ULP
  1098. Reserved21: byte;
  1099. Reserved22: byte;
  1100. Reserved23: byte;
  1101. OSCCAL16M0: byte; //Oscillator Calibration 16 MHz Byte 0
  1102. OSCCAL16M1: byte; //Oscillator Calibration 16 MHz Byte 1
  1103. OSCCAL20M0: byte; //Oscillator Calibration 20 MHz Byte 0
  1104. OSCCAL20M1: byte; //Oscillator Calibration 20 MHz Byte 1
  1105. Reserved28: byte;
  1106. Reserved29: byte;
  1107. Reserved30: byte;
  1108. Reserved31: byte;
  1109. TEMPSENSE0: byte; //Temperature Sensor Calibration Byte 0
  1110. TEMPSENSE1: byte; //Temperature Sensor Calibration Byte 1
  1111. OSC16ERR3V: byte; //OSC16 error at 3V
  1112. OSC16ERR5V: byte; //OSC16 error at 5V
  1113. OSC20ERR3V: byte; //OSC20 error at 3V
  1114. OSC20ERR5V: byte; //OSC20 error at 5V
  1115. Reserved38: byte;
  1116. Reserved39: byte;
  1117. Reserved40: byte;
  1118. Reserved41: byte;
  1119. Reserved42: byte;
  1120. Reserved43: byte;
  1121. Reserved44: byte;
  1122. Reserved45: byte;
  1123. Reserved46: byte;
  1124. CHECKSUM1: byte; //CRC Checksum Byte 1
  1125. end;
  1126. TSLPCTRL = object //Sleep Controller
  1127. CTRLA: byte; //Control
  1128. const
  1129. // Sleep enable
  1130. SENbm = $01;
  1131. // SLPCTRL_SMODE
  1132. SMODEmask = $06;
  1133. SMODE_IDLE = $00;
  1134. SMODE_STDBY = $02;
  1135. SMODE_PDOWN = $04;
  1136. end;
  1137. TSPI = object //Serial Peripheral Interface
  1138. CTRLA: byte; //Control A
  1139. CTRLB: byte; //Control B
  1140. INTCTRL: byte; //Interrupt Control
  1141. INTFLAGS: byte; //Interrupt Flags
  1142. DATA: byte; //Data
  1143. const
  1144. // Enable Double Speed
  1145. CLK2Xbm = $10;
  1146. // Data Order Setting
  1147. DORDbm = $40;
  1148. // Enable Module
  1149. ENABLEbm = $01;
  1150. // Master Operation Enable
  1151. MASTERbm = $20;
  1152. // SPI_PRESC
  1153. PRESCmask = $06;
  1154. PRESC_DIV4 = $00;
  1155. PRESC_DIV16 = $02;
  1156. PRESC_DIV64 = $04;
  1157. PRESC_DIV128 = $06;
  1158. // Buffer Mode Enable
  1159. BUFENbm = $80;
  1160. // Buffer Write Mode
  1161. BUFWRbm = $40;
  1162. // SPI_MODE
  1163. MODEmask = $03;
  1164. MODE_0 = $00;
  1165. MODE_1 = $01;
  1166. MODE_2 = $02;
  1167. MODE_3 = $03;
  1168. // Slave Select Disable
  1169. SSDbm = $04;
  1170. // Data Register Empty Interrupt Enable
  1171. DREIEbm = $20;
  1172. // Interrupt Enable
  1173. IEbm = $01;
  1174. // Receive Complete Interrupt Enable
  1175. RXCIEbm = $80;
  1176. // Slave Select Trigger Interrupt Enable
  1177. SSIEbm = $10;
  1178. // Transfer Complete Interrupt Enable
  1179. TXCIEbm = $40;
  1180. // Buffer Overflow
  1181. BUFOVFbm = $01;
  1182. // Data Register Empty Interrupt Flag
  1183. DREIFbm = $20;
  1184. // Receive Complete Interrupt Flag
  1185. RXCIFbm = $80;
  1186. // Slave Select Trigger Interrupt Flag
  1187. SSIFbm = $10;
  1188. // Transfer Complete Interrupt Flag
  1189. TXCIFbm = $40;
  1190. // Interrupt Flag
  1191. IFbm = $80;
  1192. // Write Collision
  1193. WRCOLbm = $40;
  1194. end;
  1195. TSYSCFG = object //System Configuration Registers
  1196. Reserved0: byte;
  1197. REVID: byte; //Revision ID
  1198. EXTBRK: byte; //External Break
  1199. Reserved3: byte;
  1200. Reserved4: byte;
  1201. Reserved5: byte;
  1202. Reserved6: byte;
  1203. Reserved7: byte;
  1204. Reserved8: byte;
  1205. Reserved9: byte;
  1206. Reserved10: byte;
  1207. Reserved11: byte;
  1208. Reserved12: byte;
  1209. Reserved13: byte;
  1210. Reserved14: byte;
  1211. Reserved15: byte;
  1212. Reserved16: byte;
  1213. Reserved17: byte;
  1214. Reserved18: byte;
  1215. Reserved19: byte;
  1216. Reserved20: byte;
  1217. Reserved21: byte;
  1218. Reserved22: byte;
  1219. Reserved23: byte;
  1220. OCDM: byte; //OCD Message Register
  1221. OCDMS: byte; //OCD Message Status
  1222. const
  1223. // External break enable
  1224. ENEXTBRKbm = $01;
  1225. // OCD Message Read
  1226. OCDMRbm = $01;
  1227. end;
  1228. TTCA_SINGLE = object //16-bit Timer/Counter Type A - Single Mode
  1229. CTRLA: byte; //Control A
  1230. CTRLB: byte; //Control B
  1231. CTRLC: byte; //Control C
  1232. CTRLD: byte; //Control D
  1233. CTRLECLR: byte; //Control E Clear
  1234. CTRLESET: byte; //Control E Set
  1235. CTRLFCLR: byte; //Control F Clear
  1236. CTRLFSET: byte; //Control F Set
  1237. Reserved8: byte;
  1238. EVCTRL: byte; //Event Control
  1239. INTCTRL: byte; //Interrupt Control
  1240. INTFLAGS: byte; //Interrupt Flags
  1241. Reserved12: byte;
  1242. Reserved13: byte;
  1243. DBGCTRL: byte; //Degbug Control
  1244. TEMP: byte; //Temporary data for 16-bit Access
  1245. Reserved16: byte;
  1246. Reserved17: byte;
  1247. Reserved18: byte;
  1248. Reserved19: byte;
  1249. Reserved20: byte;
  1250. Reserved21: byte;
  1251. Reserved22: byte;
  1252. Reserved23: byte;
  1253. Reserved24: byte;
  1254. Reserved25: byte;
  1255. Reserved26: byte;
  1256. Reserved27: byte;
  1257. Reserved28: byte;
  1258. Reserved29: byte;
  1259. Reserved30: byte;
  1260. Reserved31: byte;
  1261. CNT: word; //Count
  1262. Reserved34: byte;
  1263. Reserved35: byte;
  1264. Reserved36: byte;
  1265. Reserved37: byte;
  1266. PER: word; //Period
  1267. CMP0: word; //Compare 0
  1268. CMP1: word; //Compare 1
  1269. CMP2: word; //Compare 2
  1270. Reserved46: byte;
  1271. Reserved47: byte;
  1272. Reserved48: byte;
  1273. Reserved49: byte;
  1274. Reserved50: byte;
  1275. Reserved51: byte;
  1276. Reserved52: byte;
  1277. Reserved53: byte;
  1278. PERBUF: word; //Period Buffer
  1279. CMP0BUF: word; //Compare 0 Buffer
  1280. CMP1BUF: word; //Compare 1 Buffer
  1281. CMP2BUF: word; //Compare 2 Buffer
  1282. const
  1283. // TCA_SINGLE_CLKSEL
  1284. SINGLE_CLKSELmask = $0E;
  1285. SINGLE_CLKSEL_DIV1 = $00;
  1286. SINGLE_CLKSEL_DIV2 = $02;
  1287. SINGLE_CLKSEL_DIV4 = $04;
  1288. SINGLE_CLKSEL_DIV8 = $06;
  1289. SINGLE_CLKSEL_DIV16 = $08;
  1290. SINGLE_CLKSEL_DIV64 = $0A;
  1291. SINGLE_CLKSEL_DIV256 = $0C;
  1292. SINGLE_CLKSEL_DIV1024 = $0E;
  1293. // Module Enable
  1294. ENABLEbm = $01;
  1295. // Auto Lock Update
  1296. ALUPDbm = $08;
  1297. // Compare 0 Enable
  1298. CMP0ENbm = $10;
  1299. // Compare 1 Enable
  1300. CMP1ENbm = $20;
  1301. // Compare 2 Enable
  1302. CMP2ENbm = $40;
  1303. // TCA_SINGLE_WGMODE
  1304. SINGLE_WGMODEmask = $07;
  1305. SINGLE_WGMODE_NORMAL = $00;
  1306. SINGLE_WGMODE_FRQ = $01;
  1307. SINGLE_WGMODE_SINGLESLOPE = $03;
  1308. SINGLE_WGMODE_DSTOP = $05;
  1309. SINGLE_WGMODE_DSBOTH = $06;
  1310. SINGLE_WGMODE_DSBOTTOM = $07;
  1311. // Compare 0 Waveform Output Value
  1312. CMP0OVbm = $01;
  1313. // Compare 1 Waveform Output Value
  1314. CMP1OVbm = $02;
  1315. // Compare 2 Waveform Output Value
  1316. CMP2OVbm = $04;
  1317. // Split Mode Enable
  1318. SPLITMbm = $01;
  1319. // TCA_SINGLE_CMD
  1320. SINGLE_CMDmask = $0C;
  1321. SINGLE_CMD_NONE = $00;
  1322. SINGLE_CMD_UPDATE = $04;
  1323. SINGLE_CMD_RESTART = $08;
  1324. SINGLE_CMD_RESET = $0C;
  1325. // Direction
  1326. DIRbm = $01;
  1327. // Lock Update
  1328. LUPDbm = $02;
  1329. // Compare 0 Buffer Valid
  1330. CMP0BVbm = $02;
  1331. // Compare 1 Buffer Valid
  1332. CMP1BVbm = $04;
  1333. // Compare 2 Buffer Valid
  1334. CMP2BVbm = $08;
  1335. // Period Buffer Valid
  1336. PERBVbm = $01;
  1337. // Debug Run
  1338. DBGRUNbm = $01;
  1339. // Count on Event Input
  1340. CNTEIbm = $01;
  1341. // TCA_SINGLE_EVACT
  1342. SINGLE_EVACTmask = $06;
  1343. SINGLE_EVACT_POSEDGE = $00;
  1344. SINGLE_EVACT_ANYEDGE = $02;
  1345. SINGLE_EVACT_HIGHLVL = $04;
  1346. SINGLE_EVACT_UPDOWN = $06;
  1347. // Compare 0 Interrupt
  1348. CMP0bm = $10;
  1349. // Compare 1 Interrupt
  1350. CMP1bm = $20;
  1351. // Compare 2 Interrupt
  1352. CMP2bm = $40;
  1353. // Overflow Interrupt
  1354. OVFbm = $01;
  1355. end;
  1356. TTCA_SPLIT = object //16-bit Timer/Counter Type A - Split Mode
  1357. CTRLA: byte; //Control A
  1358. CTRLB: byte; //Control B
  1359. CTRLC: byte; //Control C
  1360. CTRLD: byte; //Control D
  1361. CTRLECLR: byte; //Control E Clear
  1362. CTRLESET: byte; //Control E Set
  1363. Reserved6: byte;
  1364. Reserved7: byte;
  1365. Reserved8: byte;
  1366. Reserved9: byte;
  1367. INTCTRL: byte; //Interrupt Control
  1368. INTFLAGS: byte; //Interrupt Flags
  1369. Reserved12: byte;
  1370. Reserved13: byte;
  1371. DBGCTRL: byte; //Degbug Control
  1372. Reserved15: byte;
  1373. Reserved16: byte;
  1374. Reserved17: byte;
  1375. Reserved18: byte;
  1376. Reserved19: byte;
  1377. Reserved20: byte;
  1378. Reserved21: byte;
  1379. Reserved22: byte;
  1380. Reserved23: byte;
  1381. Reserved24: byte;
  1382. Reserved25: byte;
  1383. Reserved26: byte;
  1384. Reserved27: byte;
  1385. Reserved28: byte;
  1386. Reserved29: byte;
  1387. Reserved30: byte;
  1388. Reserved31: byte;
  1389. LCNT: byte; //Low Count
  1390. HCNT: byte; //High Count
  1391. Reserved34: byte;
  1392. Reserved35: byte;
  1393. Reserved36: byte;
  1394. Reserved37: byte;
  1395. LPER: byte; //Low Period
  1396. HPER: byte; //High Period
  1397. LCMP0: byte; //Low Compare
  1398. HCMP0: byte; //High Compare
  1399. LCMP1: byte; //Low Compare
  1400. HCMP1: byte; //High Compare
  1401. LCMP2: byte; //Low Compare
  1402. HCMP2: byte; //High Compare
  1403. const
  1404. // TCA_SPLIT_CLKSEL
  1405. SPLIT_CLKSELmask = $0E;
  1406. SPLIT_CLKSEL_DIV1 = $00;
  1407. SPLIT_CLKSEL_DIV2 = $02;
  1408. SPLIT_CLKSEL_DIV4 = $04;
  1409. SPLIT_CLKSEL_DIV8 = $06;
  1410. SPLIT_CLKSEL_DIV16 = $08;
  1411. SPLIT_CLKSEL_DIV64 = $0A;
  1412. SPLIT_CLKSEL_DIV256 = $0C;
  1413. SPLIT_CLKSEL_DIV1024 = $0E;
  1414. // Module Enable
  1415. ENABLEbm = $01;
  1416. // High Compare 0 Enable
  1417. HCMP0ENbm = $10;
  1418. // High Compare 1 Enable
  1419. HCMP1ENbm = $20;
  1420. // High Compare 2 Enable
  1421. HCMP2ENbm = $40;
  1422. // Low Compare 0 Enable
  1423. LCMP0ENbm = $01;
  1424. // Low Compare 1 Enable
  1425. LCMP1ENbm = $02;
  1426. // Low Compare 2 Enable
  1427. LCMP2ENbm = $04;
  1428. // High Compare 0 Output Value
  1429. HCMP0OVbm = $10;
  1430. // High Compare 1 Output Value
  1431. HCMP1OVbm = $20;
  1432. // High Compare 2 Output Value
  1433. HCMP2OVbm = $40;
  1434. // Low Compare 0 Output Value
  1435. LCMP0OVbm = $01;
  1436. // Low Compare 1 Output Value
  1437. LCMP1OVbm = $02;
  1438. // Low Compare 2 Output Value
  1439. LCMP2OVbm = $04;
  1440. // Split Mode Enable
  1441. SPLITMbm = $01;
  1442. // TCA_SPLIT_CMD
  1443. SPLIT_CMDmask = $0C;
  1444. SPLIT_CMD_NONE = $00;
  1445. SPLIT_CMD_UPDATE = $04;
  1446. SPLIT_CMD_RESTART = $08;
  1447. SPLIT_CMD_RESET = $0C;
  1448. // Debug Run
  1449. DBGRUNbm = $01;
  1450. // High Underflow Interrupt Enable
  1451. HUNFbm = $02;
  1452. // Low Compare 0 Interrupt Enable
  1453. LCMP0bm = $10;
  1454. // Low Compare 1 Interrupt Enable
  1455. LCMP1bm = $20;
  1456. // Low Compare 2 Interrupt Enable
  1457. LCMP2bm = $40;
  1458. // Low Underflow Interrupt Enable
  1459. LUNFbm = $01;
  1460. end;
  1461. TTCA = record //16-bit Timer/Counter Type A
  1462. case byte of
  1463. 0: (SINGLE: TTCA_SINGLE);
  1464. 1: (SPLIT: TTCA_SPLIT);
  1465. end;
  1466. TTCB = object //16-bit Timer Type B
  1467. CTRLA: byte; //Control A
  1468. CTRLB: byte; //Control Register B
  1469. Reserved2: byte;
  1470. Reserved3: byte;
  1471. EVCTRL: byte; //Event Control
  1472. INTCTRL: byte; //Interrupt Control
  1473. INTFLAGS: byte; //Interrupt Flags
  1474. STATUS: byte; //Status
  1475. DBGCTRL: byte; //Debug Control
  1476. TEMP: byte; //Temporary Value
  1477. CNT: word; //Count
  1478. CCMP: word; //Compare or Capture
  1479. const
  1480. // TCB_CLKSEL
  1481. CLKSELmask = $06;
  1482. CLKSEL_CLKDIV1 = $00;
  1483. CLKSEL_CLKDIV2 = $02;
  1484. CLKSEL_CLKTCA = $04;
  1485. // Enable
  1486. ENABLEbm = $01;
  1487. // Run Standby
  1488. RUNSTDBYbm = $40;
  1489. // Synchronize Update
  1490. SYNCUPDbm = $10;
  1491. // Asynchronous Enable
  1492. ASYNCbm = $40;
  1493. // Pin Output Enable
  1494. CCMPENbm = $10;
  1495. // Pin Initial State
  1496. CCMPINITbm = $20;
  1497. // TCB_CNTMODE
  1498. CNTMODEmask = $07;
  1499. CNTMODE_INT = $00;
  1500. CNTMODE_TIMEOUT = $01;
  1501. CNTMODE_CAPT = $02;
  1502. CNTMODE_FRQ = $03;
  1503. CNTMODE_PW = $04;
  1504. CNTMODE_FRQPW = $05;
  1505. CNTMODE_SINGLE = $06;
  1506. CNTMODE_PWM8 = $07;
  1507. // Debug Run
  1508. DBGRUNbm = $01;
  1509. // Event Input Enable
  1510. CAPTEIbm = $01;
  1511. // Event Edge
  1512. EDGEbm = $10;
  1513. // Input Capture Noise Cancellation Filter
  1514. FILTERbm = $40;
  1515. // Capture or Timeout
  1516. CAPTbm = $01;
  1517. // Run
  1518. RUNbm = $01;
  1519. end;
  1520. TTWI = object //Two-Wire Interface
  1521. CTRLA: byte; //Control A
  1522. DUALCTRL: byte; //Dual Control
  1523. DBGCTRL: byte; //Debug Control Register
  1524. MCTRLA: byte; //Master Control A
  1525. MCTRLB: byte; //Master Control B
  1526. MSTATUS: byte; //Master Status
  1527. MBAUD: byte; //Master Baurd Rate Control
  1528. MADDR: byte; //Master Address
  1529. MDATA: byte; //Master Data
  1530. SCTRLA: byte; //Slave Control A
  1531. SCTRLB: byte; //Slave Control B
  1532. SSTATUS: byte; //Slave Status
  1533. SADDR: byte; //Slave Address
  1534. SDATA: byte; //Slave Data
  1535. SADDRMASK: byte; //Slave Address Mask
  1536. const
  1537. // FM Plus Enable
  1538. FMPENbm = $02;
  1539. // TWI_DEFAULT_SDAHOLD
  1540. DEFAULT_SDAHOLDmask = $0C;
  1541. DEFAULT_SDAHOLD_OFF = $00;
  1542. DEFAULT_SDAHOLD_50NS = $04;
  1543. DEFAULT_SDAHOLD_300NS = $08;
  1544. DEFAULT_SDAHOLD_500NS = $0C;
  1545. // TWI_DEFAULT_SDASETUP
  1546. DEFAULT_SDASETUPmask = $10;
  1547. DEFAULT_SDASETUP_4CYC = $00;
  1548. DEFAULT_SDASETUP_8CYC = $10;
  1549. // Debug Run
  1550. DBGRUNbm = $01;
  1551. // Dual Control Enable
  1552. ENABLEbm = $01;
  1553. // Quick Command Enable
  1554. QCENbm = $10;
  1555. // Read Interrupt Enable
  1556. RIENbm = $80;
  1557. // Smart Mode Enable
  1558. SMENbm = $02;
  1559. // TWI_TIMEOUT
  1560. TIMEOUTmask = $0C;
  1561. TIMEOUT_DISABLED = $00;
  1562. TIMEOUT_50US = $04;
  1563. TIMEOUT_100US = $08;
  1564. TIMEOUT_200US = $0C;
  1565. // Write Interrupt Enable
  1566. WIENbm = $40;
  1567. // TWI_ACKACT
  1568. ACKACTmask = $04;
  1569. ACKACT_ACK = $00;
  1570. ACKACT_NACK = $04;
  1571. // Flush
  1572. FLUSHbm = $08;
  1573. // TWI_MCMD
  1574. MCMDmask = $03;
  1575. MCMD_NOACT = $00;
  1576. MCMD_REPSTART = $01;
  1577. MCMD_RECVTRANS = $02;
  1578. MCMD_STOP = $03;
  1579. // Arbitration Lost
  1580. ARBLOSTbm = $08;
  1581. // Bus Error
  1582. BUSERRbm = $04;
  1583. // TWI_BUSSTATE
  1584. BUSSTATEmask = $03;
  1585. BUSSTATE_UNKNOWN = $00;
  1586. BUSSTATE_IDLE = $01;
  1587. BUSSTATE_OWNER = $02;
  1588. BUSSTATE_BUSY = $03;
  1589. // Clock Hold
  1590. CLKHOLDbm = $20;
  1591. // Read Interrupt Flag
  1592. RIFbm = $80;
  1593. // Received Acknowledge
  1594. RXACKbm = $10;
  1595. // Write Interrupt Flag
  1596. WIFbm = $40;
  1597. // Address Enable
  1598. ADDRENbm = $01;
  1599. // Address Mask
  1600. ADDRMASK0bm = $02;
  1601. ADDRMASK1bm = $04;
  1602. ADDRMASK2bm = $08;
  1603. ADDRMASK3bm = $10;
  1604. ADDRMASK4bm = $20;
  1605. ADDRMASK5bm = $40;
  1606. ADDRMASK6bm = $80;
  1607. // Address/Stop Interrupt Enable
  1608. APIENbm = $40;
  1609. // Data Interrupt Enable
  1610. DIENbm = $80;
  1611. // Stop Interrupt Enable
  1612. PIENbm = $20;
  1613. // Promiscuous Mode Enable
  1614. PMENbm = $04;
  1615. // TWI_SCMD
  1616. SCMDmask = $03;
  1617. SCMD_NOACT = $00;
  1618. SCMD_COMPTRANS = $02;
  1619. SCMD_RESPONSE = $03;
  1620. // TWI_AP
  1621. APmask = $01;
  1622. AP_STOP = $00;
  1623. AP_ADR = $01;
  1624. // Address/Stop Interrupt Flag
  1625. APIFbm = $40;
  1626. // Collision
  1627. COLLbm = $08;
  1628. // Data Interrupt Flag
  1629. DIFbm = $80;
  1630. // Read/Write Direction
  1631. DIRbm = $02;
  1632. end;
  1633. TUSART = object //Universal Synchronous and Asynchronous Receiver and Transmitter
  1634. RXDATAL: byte; //Receive Data Low Byte
  1635. RXDATAH: byte; //Receive Data High Byte
  1636. TXDATAL: byte; //Transmit Data Low Byte
  1637. TXDATAH: byte; //Transmit Data High Byte
  1638. STATUS: byte; //Status
  1639. CTRLA: byte; //Control A
  1640. CTRLB: byte; //Control B
  1641. CTRLC: byte; //Control C
  1642. BAUD: word; //Baud Rate
  1643. CTRLD: byte; //Control D
  1644. DBGCTRL: byte; //Debug Control
  1645. EVCTRL: byte; //Event Control
  1646. TXPLCTRL: byte; //IRCOM Transmitter Pulse Length Control
  1647. RXPLCTRL: byte; //IRCOM Receiver Pulse Length Control
  1648. const
  1649. // Auto-baud Error Interrupt Enable
  1650. ABEIEbm = $04;
  1651. // Data Register Empty Interrupt Enable
  1652. DREIEbm = $20;
  1653. // Loop-back Mode Enable
  1654. LBMEbm = $08;
  1655. // USART_RS485
  1656. RS485mask = $03;
  1657. RS485_OFF = $00;
  1658. RS485_EXT = $01;
  1659. RS485_INT = $02;
  1660. // Receive Complete Interrupt Enable
  1661. RXCIEbm = $80;
  1662. // Receiver Start Frame Interrupt Enable
  1663. RXSIEbm = $10;
  1664. // Transmit Complete Interrupt Enable
  1665. TXCIEbm = $40;
  1666. // Multi-processor Communication Mode
  1667. MPCMbm = $01;
  1668. // Open Drain Mode Enable
  1669. ODMEbm = $08;
  1670. // Reciever enable
  1671. RXENbm = $80;
  1672. // USART_RXMODE
  1673. RXMODEmask = $06;
  1674. RXMODE_NORMAL = $00;
  1675. RXMODE_CLK2X = $02;
  1676. RXMODE_GENAUTO = $04;
  1677. RXMODE_LINAUTO = $06;
  1678. // Start Frame Detection Enable
  1679. SFDENbm = $10;
  1680. // Transmitter Enable
  1681. TXENbm = $40;
  1682. // USART_MSPI_CMODE
  1683. MSPI_CMODEmask = $C0;
  1684. MSPI_CMODE_ASYNCHRONOUS = $00;
  1685. MSPI_CMODE_SYNCHRONOUS = $40;
  1686. MSPI_CMODE_IRCOM = $80;
  1687. MSPI_CMODE_MSPI = $C0;
  1688. // SPI Master Mode, Clock Phase
  1689. UCPHAbm = $02;
  1690. // SPI Master Mode, Data Order
  1691. UDORDbm = $04;
  1692. // USART_NORMAL_CHSIZE
  1693. NORMAL_CHSIZEmask = $07;
  1694. NORMAL_CHSIZE_5BIT = $00;
  1695. NORMAL_CHSIZE_6BIT = $01;
  1696. NORMAL_CHSIZE_7BIT = $02;
  1697. NORMAL_CHSIZE_8BIT = $03;
  1698. NORMAL_CHSIZE_9BITL = $06;
  1699. NORMAL_CHSIZE_9BITH = $07;
  1700. // USART_NORMAL_CMODE
  1701. NORMAL_CMODEmask = $C0;
  1702. NORMAL_CMODE_ASYNCHRONOUS = $00;
  1703. NORMAL_CMODE_SYNCHRONOUS = $40;
  1704. NORMAL_CMODE_IRCOM = $80;
  1705. NORMAL_CMODE_MSPI = $C0;
  1706. // USART_NORMAL_PMODE
  1707. NORMAL_PMODEmask = $30;
  1708. NORMAL_PMODE_DISABLED = $00;
  1709. NORMAL_PMODE_EVEN = $20;
  1710. NORMAL_PMODE_ODD = $30;
  1711. // USART_NORMAL_SBMODE
  1712. NORMAL_SBMODEmask = $08;
  1713. NORMAL_SBMODE_1BIT = $00;
  1714. NORMAL_SBMODE_2BIT = $08;
  1715. // USART_ABW
  1716. ABWmask = $C0;
  1717. ABW_WDW0 = $00;
  1718. ABW_WDW1 = $40;
  1719. ABW_WDW2 = $80;
  1720. ABW_WDW3 = $C0;
  1721. // Autobaud majority voter bypass
  1722. ABMBPbm = $80;
  1723. // Debug Run
  1724. DBGRUNbm = $01;
  1725. // IrDA Event Input Enable
  1726. IREIbm = $01;
  1727. // Buffer Overflow
  1728. BUFOVFbm = $40;
  1729. // Receiver Data Register
  1730. DATA8bm = $01;
  1731. // Frame Error
  1732. FERRbm = $04;
  1733. // Parity Error
  1734. PERRbm = $02;
  1735. // Receive Complete Interrupt Flag
  1736. RXCIFbm = $80;
  1737. // RX Data
  1738. DATA0bm = $01;
  1739. DATA1bm = $02;
  1740. DATA2bm = $04;
  1741. DATA3bm = $08;
  1742. DATA4bm = $10;
  1743. DATA5bm = $20;
  1744. DATA6bm = $40;
  1745. DATA7bm = $80;
  1746. // Receiver Pulse Lenght
  1747. RXPL0bm = $01;
  1748. RXPL1bm = $02;
  1749. RXPL2bm = $04;
  1750. RXPL3bm = $08;
  1751. RXPL4bm = $10;
  1752. RXPL5bm = $20;
  1753. RXPL6bm = $40;
  1754. // Break Detected Flag
  1755. BDFbm = $02;
  1756. // Data Register Empty Flag
  1757. DREIFbm = $20;
  1758. // Inconsistent Sync Field Interrupt Flag
  1759. ISFIFbm = $08;
  1760. // Receive Start Interrupt
  1761. RXSIFbm = $10;
  1762. // Transmit Interrupt Flag
  1763. TXCIFbm = $40;
  1764. // Wait For Break
  1765. WFBbm = $01;
  1766. // Transmit pulse length
  1767. TXPL0bm = $01;
  1768. TXPL1bm = $02;
  1769. TXPL2bm = $04;
  1770. TXPL3bm = $08;
  1771. TXPL4bm = $10;
  1772. TXPL5bm = $20;
  1773. TXPL6bm = $40;
  1774. TXPL7bm = $80;
  1775. end;
  1776. TUSERROW = object //User Row
  1777. USERROW0: byte; //User Row Byte 0
  1778. USERROW1: byte; //User Row Byte 1
  1779. USERROW2: byte; //User Row Byte 2
  1780. USERROW3: byte; //User Row Byte 3
  1781. USERROW4: byte; //User Row Byte 4
  1782. USERROW5: byte; //User Row Byte 5
  1783. USERROW6: byte; //User Row Byte 6
  1784. USERROW7: byte; //User Row Byte 7
  1785. USERROW8: byte; //User Row Byte 8
  1786. USERROW9: byte; //User Row Byte 9
  1787. USERROW10: byte; //User Row Byte 10
  1788. USERROW11: byte; //User Row Byte 11
  1789. USERROW12: byte; //User Row Byte 12
  1790. USERROW13: byte; //User Row Byte 13
  1791. USERROW14: byte; //User Row Byte 14
  1792. USERROW15: byte; //User Row Byte 15
  1793. USERROW16: byte; //User Row Byte 16
  1794. USERROW17: byte; //User Row Byte 17
  1795. USERROW18: byte; //User Row Byte 18
  1796. USERROW19: byte; //User Row Byte 19
  1797. USERROW20: byte; //User Row Byte 20
  1798. USERROW21: byte; //User Row Byte 21
  1799. USERROW22: byte; //User Row Byte 22
  1800. USERROW23: byte; //User Row Byte 23
  1801. USERROW24: byte; //User Row Byte 24
  1802. USERROW25: byte; //User Row Byte 25
  1803. USERROW26: byte; //User Row Byte 26
  1804. USERROW27: byte; //User Row Byte 27
  1805. USERROW28: byte; //User Row Byte 28
  1806. USERROW29: byte; //User Row Byte 29
  1807. USERROW30: byte; //User Row Byte 30
  1808. USERROW31: byte; //User Row Byte 31
  1809. USERROW32: byte; //User Row Byte 32
  1810. USERROW33: byte; //User Row Byte 33
  1811. USERROW34: byte; //User Row Byte 34
  1812. USERROW35: byte; //User Row Byte 35
  1813. USERROW36: byte; //User Row Byte 36
  1814. USERROW37: byte; //User Row Byte 37
  1815. USERROW38: byte; //User Row Byte 38
  1816. USERROW39: byte; //User Row Byte 39
  1817. USERROW40: byte; //User Row Byte 40
  1818. USERROW41: byte; //User Row Byte 41
  1819. USERROW42: byte; //User Row Byte 42
  1820. USERROW43: byte; //User Row Byte 43
  1821. USERROW44: byte; //User Row Byte 44
  1822. USERROW45: byte; //User Row Byte 45
  1823. USERROW46: byte; //User Row Byte 46
  1824. USERROW47: byte; //User Row Byte 47
  1825. USERROW48: byte; //User Row Byte 48
  1826. USERROW49: byte; //User Row Byte 49
  1827. USERROW50: byte; //User Row Byte 50
  1828. USERROW51: byte; //User Row Byte 51
  1829. USERROW52: byte; //User Row Byte 52
  1830. USERROW53: byte; //User Row Byte 53
  1831. USERROW54: byte; //User Row Byte 54
  1832. USERROW55: byte; //User Row Byte 55
  1833. USERROW56: byte; //User Row Byte 56
  1834. USERROW57: byte; //User Row Byte 57
  1835. USERROW58: byte; //User Row Byte 58
  1836. USERROW59: byte; //User Row Byte 59
  1837. USERROW60: byte; //User Row Byte 60
  1838. USERROW61: byte; //User Row Byte 61
  1839. USERROW62: byte; //User Row Byte 62
  1840. USERROW63: byte; //User Row Byte 63
  1841. end;
  1842. TVPORT = object //Virtual Ports
  1843. DIR: byte; //Data Direction
  1844. OUT_: byte; //Output Value
  1845. IN_: byte; //Input Value
  1846. INTFLAGS: byte; //Interrupt Flags
  1847. const
  1848. // Pin Interrupt
  1849. INT0bm = $01;
  1850. INT1bm = $02;
  1851. INT2bm = $04;
  1852. INT3bm = $08;
  1853. INT4bm = $10;
  1854. INT5bm = $20;
  1855. INT6bm = $40;
  1856. INT7bm = $80;
  1857. end;
  1858. TVREF = object //Voltage reference
  1859. CTRLA: byte; //Control A
  1860. CTRLB: byte; //Control B
  1861. const
  1862. // VREF_AC0REFSEL
  1863. AC0REFSELmask = $07;
  1864. AC0REFSEL_0V55 = $00;
  1865. AC0REFSEL_1V1 = $01;
  1866. AC0REFSEL_2V5 = $02;
  1867. AC0REFSEL_4V34 = $03;
  1868. AC0REFSEL_1V5 = $04;
  1869. AC0REFSEL_AVDD = $07;
  1870. // VREF_ADC0REFSEL
  1871. ADC0REFSELmask = $70;
  1872. ADC0REFSEL_0V55 = $00;
  1873. ADC0REFSEL_1V1 = $10;
  1874. ADC0REFSEL_2V5 = $20;
  1875. ADC0REFSEL_4V34 = $30;
  1876. ADC0REFSEL_1V5 = $40;
  1877. // AC0 DACREF reference enable
  1878. AC0REFENbm = $01;
  1879. // ADC0 reference enable
  1880. ADC0REFENbm = $02;
  1881. end;
  1882. TWDT = object //Watch-Dog Timer
  1883. CTRLA: byte; //Control A
  1884. STATUS: byte; //Status
  1885. const
  1886. // WDT_PERIOD
  1887. PERIODmask = $0F;
  1888. PERIOD_OFF = $00;
  1889. PERIOD_8CLK = $01;
  1890. PERIOD_16CLK = $02;
  1891. PERIOD_32CLK = $03;
  1892. PERIOD_64CLK = $04;
  1893. PERIOD_128CLK = $05;
  1894. PERIOD_256CLK = $06;
  1895. PERIOD_512CLK = $07;
  1896. PERIOD_1KCLK = $08;
  1897. PERIOD_2KCLK = $09;
  1898. PERIOD_4KCLK = $0A;
  1899. PERIOD_8KCLK = $0B;
  1900. // WDT_WINDOW
  1901. WINDOWmask = $F0;
  1902. WINDOW_OFF = $00;
  1903. WINDOW_8CLK = $10;
  1904. WINDOW_16CLK = $20;
  1905. WINDOW_32CLK = $30;
  1906. WINDOW_64CLK = $40;
  1907. WINDOW_128CLK = $50;
  1908. WINDOW_256CLK = $60;
  1909. WINDOW_512CLK = $70;
  1910. WINDOW_1KCLK = $80;
  1911. WINDOW_2KCLK = $90;
  1912. WINDOW_4KCLK = $A0;
  1913. WINDOW_8KCLK = $B0;
  1914. // Lock enable
  1915. LOCKbm = $80;
  1916. // Syncronization busy
  1917. SYNCBUSYbm = $01;
  1918. end;
  1919. const
  1920. Pin0idx = 0; Pin0bm = 1;
  1921. Pin1idx = 1; Pin1bm = 2;
  1922. Pin2idx = 2; Pin2bm = 4;
  1923. Pin3idx = 3; Pin3bm = 8;
  1924. Pin4idx = 4; Pin4bm = 16;
  1925. Pin5idx = 5; Pin5bm = 32;
  1926. Pin6idx = 6; Pin6bm = 64;
  1927. Pin7idx = 7; Pin7bm = 128;
  1928. var
  1929. VPORTA: TVPORT absolute $0000;
  1930. VPORTB: TVPORT absolute $0004;
  1931. VPORTC: TVPORT absolute $0008;
  1932. VPORTD: TVPORT absolute $000C;
  1933. VPORTE: TVPORT absolute $0010;
  1934. VPORTF: TVPORT absolute $0014;
  1935. GPIO: TGPIO absolute $001C;
  1936. CPU: TCPU absolute $0030;
  1937. RSTCTRL: TRSTCTRL absolute $0040;
  1938. SLPCTRL: TSLPCTRL absolute $0050;
  1939. CLKCTRL: TCLKCTRL absolute $0060;
  1940. BOD: TBOD absolute $0080;
  1941. VREF: TVREF absolute $00A0;
  1942. WDT: TWDT absolute $0100;
  1943. CPUINT: TCPUINT absolute $0110;
  1944. CRCSCAN: TCRCSCAN absolute $0120;
  1945. RTC: TRTC absolute $0140;
  1946. EVSYS: TEVSYS absolute $0180;
  1947. CCL: TCCL absolute $01C0;
  1948. PORTA: TPORT absolute $0400;
  1949. PORTB: TPORT absolute $0420;
  1950. PORTC: TPORT absolute $0440;
  1951. PORTD: TPORT absolute $0460;
  1952. PORTE: TPORT absolute $0480;
  1953. PORTF: TPORT absolute $04A0;
  1954. PORTMUX: TPORTMUX absolute $05E0;
  1955. ADC0: TADC absolute $0600;
  1956. AC0: TAC absolute $0680;
  1957. USART0: TUSART absolute $0800;
  1958. USART1: TUSART absolute $0820;
  1959. USART2: TUSART absolute $0840;
  1960. USART3: TUSART absolute $0860;
  1961. TWI0: TTWI absolute $08A0;
  1962. SPI0: TSPI absolute $08C0;
  1963. TCA0: TTCA absolute $0A00;
  1964. TCB0: TTCB absolute $0A80;
  1965. TCB1: TTCB absolute $0A90;
  1966. TCB2: TTCB absolute $0AA0;
  1967. TCB3: TTCB absolute $0AB0;
  1968. SYSCFG: TSYSCFG absolute $0F00;
  1969. NVMCTRL: TNVMCTRL absolute $1000;
  1970. SIGROW: TSIGROW absolute $1100;
  1971. FUSE: TFUSE absolute $1280;
  1972. LOCKBIT: TLOCKBIT absolute $128A;
  1973. USERROW: TUSERROW absolute $1300;
  1974. implementation
  1975. {$i avrcommon.inc}
  1976. procedure CRCSCAN_NMI_ISR; external name 'CRCSCAN_NMI_ISR'; // Interrupt 1
  1977. procedure BOD_VLM_ISR; external name 'BOD_VLM_ISR'; // Interrupt 2
  1978. procedure RTC_CNT_ISR; external name 'RTC_CNT_ISR'; // Interrupt 3
  1979. procedure RTC_PIT_ISR; external name 'RTC_PIT_ISR'; // Interrupt 4
  1980. procedure CCL_CCL_ISR; external name 'CCL_CCL_ISR'; // Interrupt 5
  1981. procedure PORTA_PORT_ISR; external name 'PORTA_PORT_ISR'; // Interrupt 6
  1982. procedure TCA0_LUNF_ISR; external name 'TCA0_LUNF_ISR'; // Interrupt 7
  1983. //procedure TCA0_OVF_ISR; external name 'TCA0_OVF_ISR'; // Interrupt 7
  1984. procedure TCA0_HUNF_ISR; external name 'TCA0_HUNF_ISR'; // Interrupt 8
  1985. procedure TCA0_LCMP0_ISR; external name 'TCA0_LCMP0_ISR'; // Interrupt 9
  1986. //procedure TCA0_CMP0_ISR; external name 'TCA0_CMP0_ISR'; // Interrupt 9
  1987. procedure TCA0_CMP1_ISR; external name 'TCA0_CMP1_ISR'; // Interrupt 10
  1988. //procedure TCA0_LCMP1_ISR; external name 'TCA0_LCMP1_ISR'; // Interrupt 10
  1989. procedure TCA0_CMP2_ISR; external name 'TCA0_CMP2_ISR'; // Interrupt 11
  1990. //procedure TCA0_LCMP2_ISR; external name 'TCA0_LCMP2_ISR'; // Interrupt 11
  1991. procedure TCB0_INT_ISR; external name 'TCB0_INT_ISR'; // Interrupt 12
  1992. procedure TCB1_INT_ISR; external name 'TCB1_INT_ISR'; // Interrupt 13
  1993. procedure TWI0_TWIS_ISR; external name 'TWI0_TWIS_ISR'; // Interrupt 14
  1994. procedure TWI0_TWIM_ISR; external name 'TWI0_TWIM_ISR'; // Interrupt 15
  1995. procedure SPI0_INT_ISR; external name 'SPI0_INT_ISR'; // Interrupt 16
  1996. procedure USART0_RXC_ISR; external name 'USART0_RXC_ISR'; // Interrupt 17
  1997. procedure USART0_DRE_ISR; external name 'USART0_DRE_ISR'; // Interrupt 18
  1998. procedure USART0_TXC_ISR; external name 'USART0_TXC_ISR'; // Interrupt 19
  1999. procedure PORTD_PORT_ISR; external name 'PORTD_PORT_ISR'; // Interrupt 20
  2000. procedure AC0_AC_ISR; external name 'AC0_AC_ISR'; // Interrupt 21
  2001. procedure ADC0_RESRDY_ISR; external name 'ADC0_RESRDY_ISR'; // Interrupt 22
  2002. procedure ADC0_WCOMP_ISR; external name 'ADC0_WCOMP_ISR'; // Interrupt 23
  2003. procedure PORTC_PORT_ISR; external name 'PORTC_PORT_ISR'; // Interrupt 24
  2004. procedure TCB2_INT_ISR; external name 'TCB2_INT_ISR'; // Interrupt 25
  2005. procedure USART1_RXC_ISR; external name 'USART1_RXC_ISR'; // Interrupt 26
  2006. procedure USART1_DRE_ISR; external name 'USART1_DRE_ISR'; // Interrupt 27
  2007. procedure USART1_TXC_ISR; external name 'USART1_TXC_ISR'; // Interrupt 28
  2008. procedure PORTF_PORT_ISR; external name 'PORTF_PORT_ISR'; // Interrupt 29
  2009. procedure NVMCTRL_EE_ISR; external name 'NVMCTRL_EE_ISR'; // Interrupt 30
  2010. procedure USART2_RXC_ISR; external name 'USART2_RXC_ISR'; // Interrupt 31
  2011. procedure USART2_DRE_ISR; external name 'USART2_DRE_ISR'; // Interrupt 32
  2012. procedure USART2_TXC_ISR; external name 'USART2_TXC_ISR'; // Interrupt 33
  2013. procedure PORTB_PORT_ISR; external name 'PORTB_PORT_ISR'; // Interrupt 34
  2014. procedure PORTE_PORT_ISR; external name 'PORTE_PORT_ISR'; // Interrupt 35
  2015. procedure TCB3_INT_ISR; external name 'TCB3_INT_ISR'; // Interrupt 36
  2016. procedure USART3_RXC_ISR; external name 'USART3_RXC_ISR'; // Interrupt 37
  2017. procedure USART3_DRE_ISR; external name 'USART3_DRE_ISR'; // Interrupt 38
  2018. procedure USART3_TXC_ISR; external name 'USART3_TXC_ISR'; // Interrupt 39
  2019. procedure _FPC_start; assembler; nostackframe;
  2020. label
  2021. _start;
  2022. asm
  2023. .init
  2024. .globl _start
  2025. jmp _start
  2026. jmp CRCSCAN_NMI_ISR
  2027. jmp BOD_VLM_ISR
  2028. jmp RTC_CNT_ISR
  2029. jmp RTC_PIT_ISR
  2030. jmp CCL_CCL_ISR
  2031. jmp PORTA_PORT_ISR
  2032. jmp TCA0_LUNF_ISR
  2033. // jmp TCA0_OVF_ISR
  2034. jmp TCA0_HUNF_ISR
  2035. jmp TCA0_LCMP0_ISR
  2036. // jmp TCA0_CMP0_ISR
  2037. jmp TCA0_CMP1_ISR
  2038. // jmp TCA0_LCMP1_ISR
  2039. jmp TCA0_CMP2_ISR
  2040. // jmp TCA0_LCMP2_ISR
  2041. jmp TCB0_INT_ISR
  2042. jmp TCB1_INT_ISR
  2043. jmp TWI0_TWIS_ISR
  2044. jmp TWI0_TWIM_ISR
  2045. jmp SPI0_INT_ISR
  2046. jmp USART0_RXC_ISR
  2047. jmp USART0_DRE_ISR
  2048. jmp USART0_TXC_ISR
  2049. jmp PORTD_PORT_ISR
  2050. jmp AC0_AC_ISR
  2051. jmp ADC0_RESRDY_ISR
  2052. jmp ADC0_WCOMP_ISR
  2053. jmp PORTC_PORT_ISR
  2054. jmp TCB2_INT_ISR
  2055. jmp USART1_RXC_ISR
  2056. jmp USART1_DRE_ISR
  2057. jmp USART1_TXC_ISR
  2058. jmp PORTF_PORT_ISR
  2059. jmp NVMCTRL_EE_ISR
  2060. jmp USART2_RXC_ISR
  2061. jmp USART2_DRE_ISR
  2062. jmp USART2_TXC_ISR
  2063. jmp PORTB_PORT_ISR
  2064. jmp PORTE_PORT_ISR
  2065. jmp TCB3_INT_ISR
  2066. jmp USART3_RXC_ISR
  2067. jmp USART3_DRE_ISR
  2068. jmp USART3_TXC_ISR
  2069. {$i start.inc}
  2070. .weak CRCSCAN_NMI_ISR
  2071. .weak BOD_VLM_ISR
  2072. .weak RTC_CNT_ISR
  2073. .weak RTC_PIT_ISR
  2074. .weak CCL_CCL_ISR
  2075. .weak PORTA_PORT_ISR
  2076. .weak TCA0_LUNF_ISR
  2077. // .weak TCA0_OVF_ISR
  2078. .weak TCA0_HUNF_ISR
  2079. .weak TCA0_LCMP0_ISR
  2080. // .weak TCA0_CMP0_ISR
  2081. .weak TCA0_CMP1_ISR
  2082. // .weak TCA0_LCMP1_ISR
  2083. .weak TCA0_CMP2_ISR
  2084. // .weak TCA0_LCMP2_ISR
  2085. .weak TCB0_INT_ISR
  2086. .weak TCB1_INT_ISR
  2087. .weak TWI0_TWIS_ISR
  2088. .weak TWI0_TWIM_ISR
  2089. .weak SPI0_INT_ISR
  2090. .weak USART0_RXC_ISR
  2091. .weak USART0_DRE_ISR
  2092. .weak USART0_TXC_ISR
  2093. .weak PORTD_PORT_ISR
  2094. .weak AC0_AC_ISR
  2095. .weak ADC0_RESRDY_ISR
  2096. .weak ADC0_WCOMP_ISR
  2097. .weak PORTC_PORT_ISR
  2098. .weak TCB2_INT_ISR
  2099. .weak USART1_RXC_ISR
  2100. .weak USART1_DRE_ISR
  2101. .weak USART1_TXC_ISR
  2102. .weak PORTF_PORT_ISR
  2103. .weak NVMCTRL_EE_ISR
  2104. .weak USART2_RXC_ISR
  2105. .weak USART2_DRE_ISR
  2106. .weak USART2_TXC_ISR
  2107. .weak PORTB_PORT_ISR
  2108. .weak PORTE_PORT_ISR
  2109. .weak TCB3_INT_ISR
  2110. .weak USART3_RXC_ISR
  2111. .weak USART3_DRE_ISR
  2112. .weak USART3_TXC_ISR
  2113. .set CRCSCAN_NMI_ISR, Default_IRQ_handler
  2114. .set BOD_VLM_ISR, Default_IRQ_handler
  2115. .set RTC_CNT_ISR, Default_IRQ_handler
  2116. .set RTC_PIT_ISR, Default_IRQ_handler
  2117. .set CCL_CCL_ISR, Default_IRQ_handler
  2118. .set PORTA_PORT_ISR, Default_IRQ_handler
  2119. .set TCA0_LUNF_ISR, Default_IRQ_handler
  2120. // .set TCA0_OVF_ISR, Default_IRQ_handler
  2121. .set TCA0_HUNF_ISR, Default_IRQ_handler
  2122. .set TCA0_LCMP0_ISR, Default_IRQ_handler
  2123. // .set TCA0_CMP0_ISR, Default_IRQ_handler
  2124. .set TCA0_CMP1_ISR, Default_IRQ_handler
  2125. // .set TCA0_LCMP1_ISR, Default_IRQ_handler
  2126. .set TCA0_CMP2_ISR, Default_IRQ_handler
  2127. // .set TCA0_LCMP2_ISR, Default_IRQ_handler
  2128. .set TCB0_INT_ISR, Default_IRQ_handler
  2129. .set TCB1_INT_ISR, Default_IRQ_handler
  2130. .set TWI0_TWIS_ISR, Default_IRQ_handler
  2131. .set TWI0_TWIM_ISR, Default_IRQ_handler
  2132. .set SPI0_INT_ISR, Default_IRQ_handler
  2133. .set USART0_RXC_ISR, Default_IRQ_handler
  2134. .set USART0_DRE_ISR, Default_IRQ_handler
  2135. .set USART0_TXC_ISR, Default_IRQ_handler
  2136. .set PORTD_PORT_ISR, Default_IRQ_handler
  2137. .set AC0_AC_ISR, Default_IRQ_handler
  2138. .set ADC0_RESRDY_ISR, Default_IRQ_handler
  2139. .set ADC0_WCOMP_ISR, Default_IRQ_handler
  2140. .set PORTC_PORT_ISR, Default_IRQ_handler
  2141. .set TCB2_INT_ISR, Default_IRQ_handler
  2142. .set USART1_RXC_ISR, Default_IRQ_handler
  2143. .set USART1_DRE_ISR, Default_IRQ_handler
  2144. .set USART1_TXC_ISR, Default_IRQ_handler
  2145. .set PORTF_PORT_ISR, Default_IRQ_handler
  2146. .set NVMCTRL_EE_ISR, Default_IRQ_handler
  2147. .set USART2_RXC_ISR, Default_IRQ_handler
  2148. .set USART2_DRE_ISR, Default_IRQ_handler
  2149. .set USART2_TXC_ISR, Default_IRQ_handler
  2150. .set PORTB_PORT_ISR, Default_IRQ_handler
  2151. .set PORTE_PORT_ISR, Default_IRQ_handler
  2152. .set TCB3_INT_ISR, Default_IRQ_handler
  2153. .set USART3_RXC_ISR, Default_IRQ_handler
  2154. .set USART3_DRE_ISR, Default_IRQ_handler
  2155. .set USART3_TXC_ISR, Default_IRQ_handler
  2156. end;
  2157. end.