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aasmcpu.pas
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d37e72dbf9
* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.
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il y a 11 ans |
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agarmgas.pas
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3309254474
* do not write a space before the condition for instructions without operands, not sure why this was there
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il y a 11 ans |
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aoptcpu.pas
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a3c439c60f
- No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up.
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il y a 11 ans |
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aoptcpub.pas
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d37e72dbf9
* ARM: instructions do modify the base register of pre/postindexed references. Report this fact in spilling_get_operation_type_ref and RegModifiedByInstruction functions.
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il y a 11 ans |
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aoptcpuc.pas
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790a4fe2d3
* log and id tags removed
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il y a 20 ans |
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aoptcpud.pas
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790a4fe2d3
* log and id tags removed
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il y a 20 ans |
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armatt.inc
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b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
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il y a 11 ans |
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armatts.inc
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b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
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il y a 11 ans |
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armins.dat
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b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
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il y a 11 ans |
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armnop.inc
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666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
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il y a 12 ans |
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armop.inc
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b67e4fb8b3
added the ADR ARM pseudo instruction to instruction list
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il y a 11 ans |
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armreg.dat
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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armtab.inc
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666332385d
Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)
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il y a 12 ans |
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cgcpu.pas
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1b0a1f4508
ARM: mimic what GNU C does while calling the profiling mcount on ARM
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il y a 11 ans |
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cpubase.pas
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fb52392e20
Reformat and comment is_thumb32_imm
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il y a 11 ans |
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cpuelf.pas
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4a90d7e3de
+ ARM internal linker: very initial support for Thumb mode, helloworld-class programs compiled with "-Cparmv6m -CIthumb" can now run.
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il y a 11 ans |
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cpuinfo.pas
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0dc39b5d63
Applied patch from Michael Ring that adds some startup code for some new stm32f0 and stm32f1 controllers, and fixes naming on some LPC ARMv6m controllers.
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il y a 11 ans |
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cpunode.pas
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b57c95043f
+ support overriding tdef/tsym methods with target-specific functionality:
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il y a 11 ans |
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cpupara.pas
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5053a39501
* moved ARM-specific tprocdef.total_stackframe_size field to cpu-specific
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il y a 11 ans |
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cpupi.pas
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eeb15fc445
* Added virtual method tprocinfo.postprocess_code and moved target-specific processing from base class into target-specific descendant classes (ARM and AVR, other targets still to do).
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il y a 11 ans |
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cputarg.pas
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d26f0552a0
* Sync with trunk r23404.
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il y a 12 ans |
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hlcgcpu.pas
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72e9cfee24
* create/destroy also the high level code generator for all architectures,
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il y a 14 ans |
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itcpugas.pas
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47d43750e4
* remove unused units from uses statements
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il y a 12 ans |
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narmadd.pas
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2fa7171a45
* generate AND for small set comparisons also when only set vars are involved using the cg class, so it works for arm thumb as well
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il y a 11 ans |
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narmcal.pas
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8b8a786823
* moved ARM/x86 ifdef'ed code from ncgcal to virtual methods
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il y a 12 ans |
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narmcnv.pas
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5051453806
+ support for LOC_(C)MMREGISTER in hlcg
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il y a 12 ans |
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narmcon.pas
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196436b7e7
* ARM: Test if range check of floating point constants is necessary in the same way as on other targets. This should have been part of r10940 6 years ago...
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il y a 11 ans |
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narminl.pas
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96b73b0076
Fixed generation of abs calls for thumb and thumb-2 targets.
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il y a 11 ans |
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narmmat.pas
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0cb1a129b3
{ARM} Implement usage of generic division-by-const optimization
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il y a 11 ans |
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narmmem.pas
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d4968e054b
+ arm: tsettings.instructionset
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il y a 12 ans |
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narmset.pas
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db01c50a4f
* fixes jump table generate for arm thumb
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il y a 11 ans |
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pp.lpi.template
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1f032375c3
* improved template with help from Mattias Gaertner
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il y a 19 ans |
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raarm.pas
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780e75bfac
o patch by Jeppe Johansen to fix mantis #17472:
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il y a 14 ans |
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raarmgas.pas
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09608a1c28
* fix warnings when compiling the compiler with DFA optimizer enabled on ARM
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il y a 11 ans |
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rarmcon.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmdwa.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmnor.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmnum.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmrni.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmsri.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmsta.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmstd.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rarmsup.inc
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7150832ec9
+ Cortex-M3 special registers, resolves #23185
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il y a 12 ans |
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rgcpu.pas
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09728a9ae2
* improved r28534: LDR/STR on thumb do not support registers >r7 as destination/source
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il y a 11 ans |
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symcpu.pas
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02495c17bd
Fix a typo. The CPU specific version of "ttypesym" should be called "tcputypesym" and not "tcpuypesym".
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il y a 11 ans |
sergei
a3c439c60f
- No longer insert BlockStart markers into asmlists. The presence of these markers disrupts peephole optimizations and require additional checks all over the place, causing various workarounds/hacks (like TAsmList.Create_without_marker) to start building up.