cpuinfo.pas 24 KB

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  1. {
  2. Copyright (c) 1998-2002 by the Free Pascal development team
  3. Basic Processor information for the ARM
  4. See the file COPYING.FPC, included in this distribution,
  5. for details about the copyright.
  6. This program is distributed in the hope that it will be useful,
  7. but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  9. **********************************************************************}
  10. Unit CPUInfo;
  11. Interface
  12. uses
  13. globtype;
  14. Type
  15. bestreal = double;
  16. ts32real = single;
  17. ts64real = double;
  18. ts80real = type extended;
  19. ts128real = type extended;
  20. ts64comp = comp;
  21. pbestreal=^bestreal;
  22. { possible supported processors for this target }
  23. tcputype =
  24. (cpu_none,
  25. cpu_armv3,
  26. cpu_armv4,
  27. cpu_armv4t,
  28. cpu_armv5,
  29. cpu_armv6,
  30. cpu_armv7,
  31. cpu_armv7m
  32. );
  33. Const
  34. cpu_arm = [cpu_none,cpu_armv3,cpu_armv4,cpu_armv4t,cpu_armv5];
  35. cpu_thumb = [];
  36. cpu_thumb2 = [cpu_armv7m];
  37. Type
  38. tfputype =
  39. (fpu_none,
  40. fpu_soft,
  41. fpu_libgcc,
  42. fpu_fpa,
  43. fpu_fpa10,
  44. fpu_fpa11,
  45. fpu_vfpv2,
  46. fpu_vfpv3
  47. );
  48. tcontrollertype =
  49. (ct_none,
  50. { Phillips }
  51. ct_lpc2114,
  52. ct_lpc2124,
  53. ct_lpc2194,
  54. ct_lpc1768,
  55. { ATMEL }
  56. ct_at91sam7s256,
  57. ct_at91sam7se256,
  58. ct_at91sam7x256,
  59. ct_at91sam7xc256,
  60. { STMicroelectronics }
  61. ct_stm32f103rb,
  62. ct_stm32f103re,
  63. { TI - Fury Class - 64 K Flash, 16 K SRAM Devices }
  64. ct_lm3s1110,
  65. ct_lm3s1133,
  66. ct_lm3s1138,
  67. ct_lm3s1150,
  68. ct_lm3s1162,
  69. ct_lm3s1165,
  70. ct_lm3s1166,
  71. ct_lm3s2110,
  72. ct_lm3s2139,
  73. ct_lm3s6100,
  74. ct_lm3s6110,
  75. { TI - Fury Class - 128K Flash, 32K SRAM devices }
  76. ct_lm3s1601,
  77. ct_lm3s1608,
  78. ct_lm3s1620,
  79. ct_lm3s1635,
  80. ct_lm3s1636,
  81. ct_lm3s1637,
  82. ct_lm3s1651,
  83. ct_lm3s2601,
  84. ct_lm3s2608,
  85. ct_lm3s2620,
  86. ct_lm3s2637,
  87. ct_lm3s2651,
  88. ct_lm3s6610,
  89. ct_lm3s6611,
  90. ct_lm3s6618,
  91. ct_lm3s6633,
  92. ct_lm3s6637,
  93. ct_lm3s8630,
  94. { TI - Fury Class - 256K Flash, 64K SRAM devices }
  95. ct_lm3s1911,
  96. ct_lm3s1918,
  97. ct_lm3s1937,
  98. ct_lm3s1958,
  99. ct_lm3s1960,
  100. ct_lm3s1968,
  101. ct_lm3s1969,
  102. ct_lm3s2911,
  103. ct_lm3s2918,
  104. ct_lm3s2919,
  105. ct_lm3s2939,
  106. ct_lm3s2948,
  107. ct_lm3s2950,
  108. ct_lm3s2965,
  109. ct_lm3s6911,
  110. ct_lm3s6918,
  111. ct_lm3s6938,
  112. ct_lm3s6950,
  113. ct_lm3s6952,
  114. ct_lm3s6965,
  115. ct_lm3s8930,
  116. ct_lm3s8933,
  117. ct_lm3s8938,
  118. ct_lm3s8962,
  119. ct_lm3s8970,
  120. ct_lm3s8971,
  121. { TI - Tempest Tempest - 256 K Flash, 64 K SRAM }
  122. ct_lm3s5951,
  123. ct_lm3s5956,
  124. ct_lm3s1b21,
  125. ct_lm3s2b93,
  126. ct_lm3s5b91,
  127. ct_lm3s9b81,
  128. ct_lm3s9b90,
  129. ct_lm3s9b92,
  130. ct_lm3s9b95,
  131. ct_lm3s9b96,
  132. // generic Thumb2 target
  133. ct_thumb2bare
  134. );
  135. Const
  136. {# Size of native extended floating point type }
  137. extended_size = 12;
  138. {# Size of a multimedia register }
  139. mmreg_size = 16;
  140. { target cpu string (used by compiler options) }
  141. target_cpu_string = 'arm';
  142. { calling conventions supported by the code generator }
  143. supported_calling_conventions : tproccalloptions = [
  144. pocall_internproc,
  145. pocall_safecall,
  146. pocall_stdcall,
  147. { same as stdcall only different name mangling }
  148. pocall_cdecl,
  149. { same as stdcall only different name mangling }
  150. pocall_cppdecl,
  151. { same as stdcall but floating point numbers are handled like equal sized integers }
  152. pocall_softfloat,
  153. { same as stdcall (requires that all const records are passed by
  154. reference, but that's already done for stdcall) }
  155. pocall_mwpascal,
  156. { used for interrupt handling }
  157. pocall_interrupt
  158. ];
  159. cputypestr : array[tcputype] of string[8] = ('',
  160. 'ARMV3',
  161. 'ARMV4',
  162. 'ARMV4T',
  163. 'ARMV5',
  164. 'ARMV6',
  165. 'ARMV7',
  166. 'ARMV7M'
  167. );
  168. fputypestr : array[tfputype] of string[6] = ('',
  169. 'SOFT',
  170. 'LIBGCC',
  171. 'FPA',
  172. 'FPA10',
  173. 'FPA11',
  174. 'VFPV2',
  175. 'VFPV3'
  176. );
  177. { We know that there are fields after sramsize
  178. but we don't care about this warning }
  179. {$WARN 3177 OFF}
  180. embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
  181. ((
  182. controllertypestr:'';
  183. controllerunitstr:'';
  184. interruptvectors:0;
  185. flashbase:0;
  186. flashsize:0;
  187. srambase:0;
  188. sramsize:0
  189. ),
  190. (
  191. controllertypestr:'LPC2114';
  192. controllerunitstr:'LPC21x4';
  193. interruptvectors:8;
  194. flashbase:$00000000;
  195. flashsize:$00040000;
  196. srambase:$40000000;
  197. sramsize:$00004000
  198. ),
  199. (
  200. controllertypestr:'LPC2124';
  201. controllerunitstr:'LPC21x4';
  202. interruptvectors:8;
  203. flashbase:$00000000;
  204. flashsize:$00040000;
  205. srambase:$40000000;
  206. sramsize:$00004000
  207. ),
  208. (
  209. controllertypestr:'LPC2194';
  210. controllerunitstr:'LPC21x4';
  211. interruptvectors:8;
  212. flashbase:$00000000;
  213. flashsize:$00040000;
  214. srambase:$40000000;
  215. sramsize:$00004000
  216. ),
  217. (
  218. controllertypestr:'LPC1768';
  219. controllerunitstr:'LPC1768';
  220. interruptvectors:12;
  221. flashbase:$00000000;
  222. flashsize:$00040000;
  223. srambase:$10000000;
  224. sramsize:$00008000
  225. ),
  226. (
  227. controllertypestr:'AT91SAM7S256';
  228. controllerunitstr:'AT91SAM7x256';
  229. interruptvectors:8;
  230. flashbase:$00000000;
  231. flashsize:$00040000;
  232. srambase:$00200000;
  233. sramsize:$00010000
  234. ),
  235. (
  236. controllertypestr:'AT91SAM7SE256';
  237. controllerunitstr:'AT91SAM7x256';
  238. interruptvectors:8;
  239. flashbase:$00000000;
  240. flashsize:$00040000;
  241. srambase:$00200000;
  242. sramsize:$00010000
  243. ),
  244. (
  245. controllertypestr:'AT91SAM7X256';
  246. controllerunitstr:'AT91SAM7x256';
  247. interruptvectors:8;
  248. flashbase:$00000000;
  249. flashsize:$00040000;
  250. srambase:$00200000;
  251. sramsize:$00010000
  252. ),
  253. (
  254. controllertypestr:'AT91SAM7XC256';
  255. controllerunitstr:'AT91SAM7x256';
  256. interruptvectors:8;
  257. flashbase:$00000000;
  258. flashsize:$00040000;
  259. srambase:$00200000;
  260. sramsize:$00010000
  261. ),
  262. // ct_stm32f103rb,
  263. (
  264. controllertypestr:'STM32F103RB';
  265. controllerunitstr:'STM32F103';
  266. interruptvectors:12;
  267. flashbase:$08000000;
  268. flashsize:$00020000;
  269. srambase:$20000000;
  270. sramsize:$00005000
  271. ),
  272. // ct_stm32f103re,
  273. (
  274. controllertypestr:'STM32F103RE';
  275. controllerunitstr:'STM32F103';
  276. interruptvectors:12;
  277. flashbase:$08000000;
  278. flashsize:$00080000;
  279. srambase:$20000000;
  280. sramsize:$00010000
  281. ),
  282. { TI - 64 K Flash, 16 K SRAM Devices }
  283. // ct_lm3s1110,
  284. (
  285. controllertypestr:'LM3S1110';
  286. controllerunitstr:'LM3FURY';
  287. interruptvectors:72;
  288. flashbase:$00000000;
  289. flashsize:$00010000;
  290. srambase:$20000000;
  291. sramsize:$00004000
  292. ),
  293. // ct_lm3s1133,
  294. (
  295. controllertypestr:'LM3S1133';
  296. controllerunitstr:'LM3FURY';
  297. interruptvectors:72;
  298. flashbase:$00000000;
  299. flashsize:$00010000;
  300. srambase:$20000000;
  301. sramsize:$00004000
  302. ),
  303. // ct_lm3s1138,
  304. (
  305. controllertypestr:'LM3S1138';
  306. controllerunitstr:'LM3FURY';
  307. interruptvectors:72;
  308. flashbase:$00000000;
  309. flashsize:$00010000;
  310. srambase:$20000000;
  311. sramsize:$00004000
  312. ),
  313. // ct_lm3s1150,
  314. (
  315. controllertypestr:'LM3S1150';
  316. controllerunitstr:'LM3FURY';
  317. interruptvectors:72;
  318. flashbase:$00000000;
  319. flashsize:$00010000;
  320. srambase:$20000000;
  321. sramsize:$00004000
  322. ),
  323. // ct_lm3s1162,
  324. (
  325. controllertypestr:'LM3S1162';
  326. controllerunitstr:'LM3FURY';
  327. interruptvectors:72;
  328. flashbase:$00000000;
  329. flashsize:$00010000;
  330. srambase:$20000000;
  331. sramsize:$00004000
  332. ),
  333. // ct_lm3s1165,
  334. (
  335. controllertypestr:'LM3S1165';
  336. controllerunitstr:'LM3FURY';
  337. interruptvectors:72;
  338. flashbase:$00000000;
  339. flashsize:$00010000;
  340. srambase:$20000000;
  341. sramsize:$00004000
  342. ),
  343. // ct_lm3s1166,
  344. (
  345. controllertypestr:'LM3S1166';
  346. controllerunitstr:'LM3FURY';
  347. interruptvectors:72;
  348. flashbase:$00000000;
  349. flashsize:$00010000;
  350. srambase:$20000000;
  351. sramsize:$00004000
  352. ),
  353. // ct_lm3s2110,
  354. (
  355. controllertypestr:'LM3S2110';
  356. controllerunitstr:'LM3FURY';
  357. interruptvectors:72;
  358. flashbase:$00000000;
  359. flashsize:$00010000;
  360. srambase:$20000000;
  361. sramsize:$00004000
  362. ),
  363. // ct_lm3s2139,
  364. (
  365. controllertypestr:'LM3S2139';
  366. controllerunitstr:'LM3FURY';
  367. interruptvectors:72;
  368. flashbase:$00000000;
  369. flashsize:$00010000;
  370. srambase:$20000000;
  371. sramsize:$00004000
  372. ),
  373. // ct_lm3s6100,
  374. (
  375. controllertypestr:'LM3S6100';
  376. controllerunitstr:'LM3FURY';
  377. interruptvectors:72;
  378. flashbase:$00000000;
  379. flashsize:$00010000;
  380. srambase:$20000000;
  381. sramsize:$00004000
  382. ),
  383. // ct_lm3s6110,
  384. (
  385. controllertypestr:'LM3S6110';
  386. controllerunitstr:'LM3FURY';
  387. interruptvectors:72;
  388. flashbase:$00000000;
  389. flashsize:$00010000;
  390. srambase:$20000000;
  391. sramsize:$00004000
  392. ),
  393. { TI - 128K Flash, 32K SRAM devices }
  394. // ct_lm3s1601,
  395. (
  396. controllertypestr:'LM3S1601';
  397. controllerunitstr:'LM3FURY';
  398. interruptvectors:72;
  399. flashbase:$00000000;
  400. flashsize:$00020000;
  401. srambase:$20000000;
  402. sramsize:$00008000
  403. ),
  404. // ct_lm3s1608,
  405. (
  406. controllertypestr:'LM3S1608';
  407. controllerunitstr:'LM3FURY';
  408. interruptvectors:72;
  409. flashbase:$00000000;
  410. flashsize:$00020000;
  411. srambase:$20000000;
  412. sramsize:$00008000
  413. ),
  414. // ct_lm3s1620,
  415. (
  416. controllertypestr:'LM3S1620';
  417. controllerunitstr:'LM3FURY';
  418. interruptvectors:72;
  419. flashbase:$00000000;
  420. flashsize:$00020000;
  421. srambase:$20000000;
  422. sramsize:$00008000
  423. ),
  424. // ct_lm3s1635,
  425. (
  426. controllertypestr:'LM3S1635';
  427. controllerunitstr:'LM3FURY';
  428. interruptvectors:72;
  429. flashbase:$00000000;
  430. flashsize:$00020000;
  431. srambase:$20000000;
  432. sramsize:$00008000
  433. ),
  434. // ct_lm3s1636,
  435. (
  436. controllertypestr:'LM3S1636';
  437. controllerunitstr:'LM3FURY';
  438. interruptvectors:72;
  439. flashbase:$00000000;
  440. flashsize:$00020000;
  441. srambase:$20000000;
  442. sramsize:$00008000
  443. ),
  444. // ct_lm3s1637,
  445. (
  446. controllertypestr:'LM3S1637';
  447. controllerunitstr:'LM3FURY';
  448. interruptvectors:72;
  449. flashbase:$00000000;
  450. flashsize:$00020000;
  451. srambase:$20000000;
  452. sramsize:$00008000
  453. ),
  454. // ct_lm3s1651,
  455. (
  456. controllertypestr:'LM3S1651';
  457. controllerunitstr:'LM3FURY';
  458. interruptvectors:72;
  459. flashbase:$00000000;
  460. flashsize:$00020000;
  461. srambase:$20000000;
  462. sramsize:$00008000
  463. ),
  464. // ct_lm3s2601,
  465. (
  466. controllertypestr:'LM3S2601';
  467. controllerunitstr:'LM3FURY';
  468. interruptvectors:72;
  469. flashbase:$00000000;
  470. flashsize:$00020000;
  471. srambase:$20000000;
  472. sramsize:$00008000
  473. ),
  474. // ct_lm3s2608,
  475. (
  476. controllertypestr:'LM3S2608';
  477. controllerunitstr:'LM3FURY';
  478. interruptvectors:72;
  479. flashbase:$00000000;
  480. flashsize:$00020000;
  481. srambase:$20000000;
  482. sramsize:$00008000
  483. ),
  484. // ct_lm3s2620,
  485. (
  486. controllertypestr:'LM3S2620';
  487. controllerunitstr:'LM3FURY';
  488. interruptvectors:72;
  489. flashbase:$00000000;
  490. flashsize:$00020000;
  491. srambase:$20000000;
  492. sramsize:$00008000
  493. ),
  494. // ct_lm3s2637,
  495. (
  496. controllertypestr:'LM3S2637';
  497. controllerunitstr:'LM3FURY';
  498. interruptvectors:72;
  499. flashbase:$00000000;
  500. flashsize:$00020000;
  501. srambase:$20000000;
  502. sramsize:$00008000
  503. ),
  504. // ct_lm3s2651,
  505. (
  506. controllertypestr:'LM3S2651';
  507. controllerunitstr:'LM3FURY';
  508. interruptvectors:72;
  509. flashbase:$00000000;
  510. flashsize:$00020000;
  511. srambase:$20000000;
  512. sramsize:$00008000
  513. ),
  514. // ct_lm3s6610,
  515. (
  516. controllertypestr:'LM3S6610';
  517. controllerunitstr:'LM3FURY';
  518. interruptvectors:72;
  519. flashbase:$00000000;
  520. flashsize:$00020000;
  521. srambase:$20000000;
  522. sramsize:$00008000
  523. ),
  524. // ct_lm3s6611,
  525. (
  526. controllertypestr:'LM3S6611';
  527. controllerunitstr:'LM3FURY';
  528. interruptvectors:72;
  529. flashbase:$00000000;
  530. flashsize:$00020000;
  531. srambase:$20000000;
  532. sramsize:$00008000
  533. ),
  534. // ct_lm3s6618,
  535. (
  536. controllertypestr:'LM3S6618';
  537. controllerunitstr:'LM3FURY';
  538. interruptvectors:72;
  539. flashbase:$00000000;
  540. flashsize:$00020000;
  541. srambase:$20000000;
  542. sramsize:$00008000
  543. ),
  544. // ct_lm3s6633,
  545. (
  546. controllertypestr:'LM3S6633';
  547. controllerunitstr:'LM3FURY';
  548. interruptvectors:72;
  549. flashbase:$00000000;
  550. flashsize:$00020000;
  551. srambase:$20000000;
  552. sramsize:$00008000
  553. ),
  554. // ct_lm3s6637,
  555. (
  556. controllertypestr:'LM3S6637';
  557. controllerunitstr:'LM3FURY';
  558. interruptvectors:72;
  559. flashbase:$00000000;
  560. flashsize:$00020000;
  561. srambase:$20000000;
  562. sramsize:$00008000
  563. ),
  564. // ct_lm3s8630,
  565. (
  566. controllertypestr:'LM3S8630';
  567. controllerunitstr:'LM3FURY';
  568. interruptvectors:72;
  569. flashbase:$00000000;
  570. flashsize:$00020000;
  571. srambase:$20000000;
  572. sramsize:$00008000
  573. ),
  574. { TI - 256K Flash, 64K SRAM devices }
  575. // ct_lm3s1911,
  576. (
  577. controllertypestr:'LM3S1911';
  578. controllerunitstr:'LM3FURY';
  579. interruptvectors:72;
  580. flashbase:$00000000;
  581. flashsize:$00040000;
  582. srambase:$20000000;
  583. sramsize:$00010000
  584. ),
  585. // ct_lm3s1918,
  586. (
  587. controllertypestr:'LM3S1918';
  588. controllerunitstr:'LM3FURY';
  589. interruptvectors:72;
  590. flashbase:$00000000;
  591. flashsize:$00040000;
  592. srambase:$20000000;
  593. sramsize:$00010000
  594. ),
  595. // ct_lm3s1937,
  596. (
  597. controllertypestr:'LM3S1937';
  598. controllerunitstr:'LM3FURY';
  599. interruptvectors:72;
  600. flashbase:$00000000;
  601. flashsize:$00040000;
  602. srambase:$20000000;
  603. sramsize:$00010000
  604. ),
  605. // ct_lm3s1958,
  606. (
  607. controllertypestr:'LM3S1958';
  608. controllerunitstr:'LM3FURY';
  609. interruptvectors:72;
  610. flashbase:$00000000;
  611. flashsize:$00040000;
  612. srambase:$20000000;
  613. sramsize:$00010000
  614. ),
  615. // ct_lm3s1960,
  616. (
  617. controllertypestr:'LM3S1960';
  618. controllerunitstr:'LM3FURY';
  619. interruptvectors:72;
  620. flashbase:$00000000;
  621. flashsize:$00040000;
  622. srambase:$20000000;
  623. sramsize:$00010000
  624. ),
  625. // ct_lm3s1968,
  626. (
  627. controllertypestr:'LM3S1968';
  628. controllerunitstr:'LM3FURY';
  629. interruptvectors:72;
  630. flashbase:$00000000;
  631. flashsize:$00040000;
  632. srambase:$20000000;
  633. sramsize:$00010000
  634. ),
  635. // ct_lm3s1969,
  636. (
  637. controllertypestr:'LM3S1969';
  638. controllerunitstr:'LM3FURY';
  639. interruptvectors:72;
  640. flashbase:$00000000;
  641. flashsize:$00040000;
  642. srambase:$20000000;
  643. sramsize:$00010000
  644. ),
  645. // ct_lm3s2911,
  646. (
  647. controllertypestr:'LM3S2911';
  648. controllerunitstr:'LM3FURY';
  649. interruptvectors:72;
  650. flashbase:$00000000;
  651. flashsize:$00040000;
  652. srambase:$20000000;
  653. sramsize:$00010000
  654. ),
  655. // ct_lm3s2918,
  656. (
  657. controllertypestr:'LM3S2918';
  658. controllerunitstr:'LM3FURY';
  659. interruptvectors:72;
  660. flashbase:$00000000;
  661. flashsize:$00040000;
  662. srambase:$20000000;
  663. sramsize:$00010000
  664. ),
  665. // ct_lm3s2919,
  666. (
  667. controllertypestr:'LM3S2919';
  668. controllerunitstr:'LM3FURY';
  669. interruptvectors:72;
  670. flashbase:$00000000;
  671. flashsize:$00040000;
  672. srambase:$20000000;
  673. sramsize:$00010000
  674. ),
  675. // ct_lm3s2939,
  676. (
  677. controllertypestr:'LM3S2939';
  678. controllerunitstr:'LM3FURY';
  679. interruptvectors:72;
  680. flashbase:$00000000;
  681. flashsize:$00040000;
  682. srambase:$20000000;
  683. sramsize:$00010000
  684. ),
  685. // ct_lm3s2948,
  686. (
  687. controllertypestr:'LM3S2948';
  688. controllerunitstr:'LM3FURY';
  689. interruptvectors:72;
  690. flashbase:$00000000;
  691. flashsize:$00040000;
  692. srambase:$20000000;
  693. sramsize:$00010000
  694. ),
  695. // ct_lm3s2950,
  696. (
  697. controllertypestr:'LM3S2950';
  698. controllerunitstr:'LM3FURY';
  699. interruptvectors:72;
  700. flashbase:$00000000;
  701. flashsize:$00040000;
  702. srambase:$20000000;
  703. sramsize:$00010000
  704. ),
  705. // ct_lm3s2965,
  706. (
  707. controllertypestr:'LM3S2965';
  708. controllerunitstr:'LM3FURY';
  709. interruptvectors:72;
  710. flashbase:$00000000;
  711. flashsize:$00040000;
  712. srambase:$20000000;
  713. sramsize:$00010000
  714. ),
  715. // ct_lm3s6911,
  716. (
  717. controllertypestr:'LM3S6911';
  718. controllerunitstr:'LM3FURY';
  719. interruptvectors:72;
  720. flashbase:$00000000;
  721. flashsize:$00040000;
  722. srambase:$20000000;
  723. sramsize:$00010000
  724. ),
  725. // ct_lm3s6918,
  726. (
  727. controllertypestr:'LM3S6918';
  728. controllerunitstr:'LM3FURY';
  729. interruptvectors:72;
  730. flashbase:$00000000;
  731. flashsize:$00040000;
  732. srambase:$20000000;
  733. sramsize:$00010000
  734. ),
  735. // ct_lm3s6938,
  736. (
  737. controllertypestr:'LM3S6938';
  738. controllerunitstr:'LM3FURY';
  739. interruptvectors:72;
  740. flashbase:$00000000;
  741. flashsize:$00040000;
  742. srambase:$20000000;
  743. sramsize:$00010000
  744. ),
  745. // ct_lm3s6950,
  746. (
  747. controllertypestr:'LM3S6950';
  748. controllerunitstr:'LM3FURY';
  749. interruptvectors:72;
  750. flashbase:$00000000;
  751. flashsize:$00040000;
  752. srambase:$20000000;
  753. sramsize:$00010000
  754. ),
  755. // ct_lm3s6952,
  756. (
  757. controllertypestr:'LM3S6952';
  758. controllerunitstr:'LM3FURY';
  759. interruptvectors:72;
  760. flashbase:$00000000;
  761. flashsize:$00040000;
  762. srambase:$20000000;
  763. sramsize:$00010000
  764. ),
  765. // ct_lm3s6965,
  766. (
  767. controllertypestr:'LM3S6965';
  768. controllerunitstr:'LM3FURY';
  769. interruptvectors:72;
  770. flashbase:$00000000;
  771. flashsize:$00040000;
  772. srambase:$20000000;
  773. sramsize:$00010000
  774. ),
  775. // ct_lm3s8930,
  776. (
  777. controllertypestr:'LM3S8930';
  778. controllerunitstr:'LM3FURY';
  779. interruptvectors:72;
  780. flashbase:$00000000;
  781. flashsize:$00040000;
  782. srambase:$20000000;
  783. sramsize:$00010000
  784. ),
  785. // ct_lm3s8933,
  786. (
  787. controllertypestr:'LM3S8933';
  788. controllerunitstr:'LM3FURY';
  789. interruptvectors:72;
  790. flashbase:$00000000;
  791. flashsize:$00040000;
  792. srambase:$20000000;
  793. sramsize:$00010000
  794. ),
  795. // ct_lm3s8938,
  796. (
  797. controllertypestr:'LM3S8938';
  798. controllerunitstr:'LM3FURY';
  799. interruptvectors:72;
  800. flashbase:$00000000;
  801. flashsize:$00040000;
  802. srambase:$20000000;
  803. sramsize:$00010000
  804. ),
  805. // ct_lm3s8962,
  806. (
  807. controllertypestr:'LM3S8962';
  808. controllerunitstr:'LM3FURY';
  809. interruptvectors:72;
  810. flashbase:$00000000;
  811. flashsize:$00040000;
  812. srambase:$20000000;
  813. sramsize:$00010000
  814. ),
  815. // ct_lm3s8970,
  816. (
  817. controllertypestr:'LM3S8970';
  818. controllerunitstr:'LM3FURY';
  819. interruptvectors:72;
  820. flashbase:$00000000;
  821. flashsize:$00040000;
  822. srambase:$20000000;
  823. sramsize:$00010000
  824. ),
  825. // ct_lm3s8971,
  826. (
  827. controllertypestr:'LM3S8971';
  828. controllerunitstr:'LM3FURY';
  829. interruptvectors:72;
  830. flashbase:$00000000;
  831. flashsize:$00040000;
  832. srambase:$20000000;
  833. sramsize:$00010000
  834. ),
  835. { TI - Tempest parts - 256 K Flash, 64 K SRAM }
  836. // ct_lm3s5951,
  837. (
  838. controllertypestr:'LM3S5951';
  839. controllerunitstr:'LM3TEMPEST';
  840. interruptvectors:72;
  841. flashbase:$00000000;
  842. flashsize:$00040000;
  843. srambase:$20000000;
  844. sramsize:$00010000
  845. ),
  846. // ct_lm3s5956,
  847. (
  848. controllertypestr:'LM3S5956';
  849. controllerunitstr:'LM3TEMPEST';
  850. interruptvectors:72;
  851. flashbase:$00000000;
  852. flashsize:$00040000;
  853. srambase:$20000000;
  854. sramsize:$00010000
  855. ),
  856. // ct_lm3s1b21,
  857. (
  858. controllertypestr:'LM3S1B21';
  859. controllerunitstr:'LM3TEMPEST';
  860. interruptvectors:72;
  861. flashbase:$00000000;
  862. flashsize:$00040000;
  863. srambase:$20000000;
  864. sramsize:$00010000
  865. ),
  866. // ct_lm3s2b93,
  867. (
  868. controllertypestr:'LM3S2B93';
  869. controllerunitstr:'LM3TEMPEST';
  870. interruptvectors:72;
  871. flashbase:$00000000;
  872. flashsize:$00040000;
  873. srambase:$20000000;
  874. sramsize:$00010000
  875. ),
  876. // ct_lm3s5b91,
  877. (
  878. controllertypestr:'LM3S5B91';
  879. controllerunitstr:'LM3TEMPEST';
  880. interruptvectors:72;
  881. flashbase:$00000000;
  882. flashsize:$00040000;
  883. srambase:$20000000;
  884. sramsize:$00010000
  885. ),
  886. // ct_lm3s9b81,
  887. (
  888. controllertypestr:'LM3S9B81';
  889. controllerunitstr:'LM3TEMPEST';
  890. interruptvectors:72;
  891. flashbase:$00000000;
  892. flashsize:$00040000;
  893. srambase:$20000000;
  894. sramsize:$00010000
  895. ),
  896. // ct_lm3s9b90,
  897. (
  898. controllertypestr:'LM3S9B90';
  899. controllerunitstr:'LM3TEMPEST';
  900. interruptvectors:72;
  901. flashbase:$00000000;
  902. flashsize:$00040000;
  903. srambase:$20000000;
  904. sramsize:$00010000
  905. ),
  906. // ct_lm3s9b92,
  907. (
  908. controllertypestr:'LM3S9B92';
  909. controllerunitstr:'LM3TEMPEST';
  910. interruptvectors:72;
  911. flashbase:$00000000;
  912. flashsize:$00040000;
  913. srambase:$20000000;
  914. sramsize:$00010000
  915. ),
  916. // ct_lm3s9b95,
  917. (
  918. controllertypestr:'LM3S9B95';
  919. controllerunitstr:'LM3TEMPEST';
  920. interruptvectors:72;
  921. flashbase:$00000000;
  922. flashsize:$00040000;
  923. srambase:$20000000;
  924. sramsize:$00010000
  925. ),
  926. // ct_lm3s9b96,
  927. (
  928. controllertypestr:'LM3S9B96';
  929. controllerunitstr:'LM3TEMPEST';
  930. interruptvectors:72;
  931. flashbase:$00000000;
  932. flashsize:$00040000;
  933. srambase:$20000000;
  934. sramsize:$00010000
  935. ),
  936. // bare bones Thumb2
  937. (
  938. controllertypestr:'THUMB2_BARE';
  939. controllerunitstr:'THUMB2_BARE';
  940. interruptvectors:128;
  941. flashbase:$00000000;
  942. flashsize:$00100000;
  943. srambase:$20000000;
  944. sramsize:$00100000
  945. )
  946. );
  947. vfp_scalar = [fpu_vfpv2,fpu_vfpv3];
  948. { Supported optimizations, only used for information }
  949. supported_optimizerswitches = genericlevel1optimizerswitches+
  950. genericlevel2optimizerswitches+
  951. genericlevel3optimizerswitches-
  952. { no need to write info about those }
  953. [cs_opt_level1,cs_opt_level2,cs_opt_level3]+
  954. [cs_opt_regvar,cs_opt_loopunroll,cs_opt_tailrecursion,
  955. cs_opt_stackframe,cs_opt_nodecse];
  956. level1optimizerswitches = genericlevel1optimizerswitches;
  957. level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
  958. [cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
  959. level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
  960. Implementation
  961. end.