cgcpu.pas 59 KB

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  1. {
  2. Copyright (c) 2008 by Florian Klaempfl
  3. Member of the Free Pascal development team
  4. This unit implements the code generator for the AVR
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. ****************************************************************************
  17. }
  18. unit cgcpu;
  19. {$i fpcdefs.inc}
  20. interface
  21. uses
  22. globtype,symtype,symdef,
  23. cgbase,cgutils,cgobj,
  24. aasmbase,aasmcpu,aasmtai,aasmdata,
  25. parabase,
  26. cpubase,cpuinfo,node,cg64f32,rgcpu;
  27. type
  28. { tcgavr }
  29. tcgavr = class(tcg)
  30. { true, if the next arithmetic operation should modify the flags }
  31. cgsetflags : boolean;
  32. procedure init_register_allocators;override;
  33. procedure done_register_allocators;override;
  34. function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
  35. function getaddressregister(list:TAsmList):TRegister;override;
  36. procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
  37. procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
  38. procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
  39. procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
  40. procedure a_call_reg(list : TAsmList;reg: tregister);override;
  41. procedure a_call_ref(list : TAsmList;ref: treference);override;
  42. procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
  43. procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
  44. { move instructions }
  45. procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
  46. procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
  47. procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
  48. procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
  49. { comparison operations }
  50. procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
  51. l : tasmlabel);override;
  52. procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
  53. procedure a_jmp_name(list : TAsmList;const s : string); override;
  54. procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
  55. procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
  56. procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
  57. procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
  58. procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
  59. procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
  60. procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
  61. procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  62. procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
  63. procedure g_save_registers(list : TAsmList);override;
  64. procedure g_restore_registers(list : TAsmList);override;
  65. procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  66. procedure fixref(list : TAsmList;var ref : treference);
  67. function normalize_ref(list : TAsmList;ref : treference;
  68. tmpreg : tregister) : treference;
  69. procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
  70. procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  71. procedure a_adjust_sp(list: TAsmList; value: longint);
  72. function GetLoad(const ref : treference) : tasmop;
  73. function GetStore(const ref: treference): tasmop;
  74. end;
  75. tcg64favr = class(tcg64f32)
  76. procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
  77. procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
  78. end;
  79. procedure create_codegen;
  80. const
  81. TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
  82. A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
  83. A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
  84. implementation
  85. uses
  86. globals,verbose,systems,cutils,
  87. fmodule,
  88. symconst,symsym,
  89. tgobj,rgobj,
  90. procinfo,cpupi,
  91. paramgr;
  92. procedure tcgavr.init_register_allocators;
  93. begin
  94. inherited init_register_allocators;
  95. rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
  96. [RS_R8,RS_R9,
  97. RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
  98. RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
  99. RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
  100. { rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
  101. [RS_R26,RS_R30],first_int_imreg,[]); }
  102. end;
  103. procedure tcgavr.done_register_allocators;
  104. begin
  105. rg[R_INTREGISTER].free;
  106. // rg[R_ADDRESSREGISTER].free;
  107. inherited done_register_allocators;
  108. end;
  109. function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
  110. var
  111. tmp1,tmp2,tmp3 : TRegister;
  112. begin
  113. case size of
  114. OS_8,OS_S8:
  115. Result:=inherited getintregister(list, size);
  116. OS_16,OS_S16:
  117. begin
  118. Result:=inherited getintregister(list, OS_8);
  119. { ensure that the high register can be retrieved by
  120. GetNextReg
  121. }
  122. if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
  123. internalerror(2011021331);
  124. end;
  125. OS_32,OS_S32:
  126. begin
  127. Result:=inherited getintregister(list, OS_8);
  128. tmp1:=inherited getintregister(list, OS_8);
  129. { ensure that the high register can be retrieved by
  130. GetNextReg
  131. }
  132. if tmp1<>GetNextReg(Result) then
  133. internalerror(2011021332);
  134. tmp2:=inherited getintregister(list, OS_8);
  135. { ensure that the upper register can be retrieved by
  136. GetNextReg
  137. }
  138. if tmp2<>GetNextReg(tmp1) then
  139. internalerror(2011021333);
  140. tmp3:=inherited getintregister(list, OS_8);
  141. { ensure that the upper register can be retrieved by
  142. GetNextReg
  143. }
  144. if tmp3<>GetNextReg(tmp2) then
  145. internalerror(2011021334);
  146. end;
  147. else
  148. internalerror(2011021330);
  149. end;
  150. end;
  151. function tcgavr.getaddressregister(list: TAsmList): TRegister;
  152. begin
  153. Result:=getintregister(list,OS_ADDR);
  154. end;
  155. procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
  156. var
  157. ref: treference;
  158. begin
  159. paraloc.check_simple_location;
  160. paramanager.allocparaloc(list,paraloc.location);
  161. case paraloc.location^.loc of
  162. LOC_REGISTER,LOC_CREGISTER:
  163. a_load_const_reg(list,size,a,paraloc.location^.register);
  164. LOC_REFERENCE:
  165. begin
  166. reference_reset(ref,paraloc.alignment);
  167. ref.base:=paraloc.location^.reference.index;
  168. ref.offset:=paraloc.location^.reference.offset;
  169. a_load_const_ref(list,size,a,ref);
  170. end;
  171. else
  172. internalerror(2002081101);
  173. end;
  174. end;
  175. procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
  176. var
  177. tmpref, ref: treference;
  178. location: pcgparalocation;
  179. sizeleft: tcgint;
  180. begin
  181. location := paraloc.location;
  182. tmpref := r;
  183. sizeleft := paraloc.intsize;
  184. while assigned(location) do
  185. begin
  186. paramanager.allocparaloc(list,location);
  187. case location^.loc of
  188. LOC_REGISTER,LOC_CREGISTER:
  189. a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
  190. LOC_REFERENCE:
  191. begin
  192. reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
  193. { doubles in softemu mode have a strange order of registers and references }
  194. if location^.size=OS_32 then
  195. g_concatcopy(list,tmpref,ref,4)
  196. else
  197. begin
  198. g_concatcopy(list,tmpref,ref,sizeleft);
  199. if assigned(location^.next) then
  200. internalerror(2005010710);
  201. end;
  202. end;
  203. LOC_VOID:
  204. begin
  205. // nothing to do
  206. end;
  207. else
  208. internalerror(2002081103);
  209. end;
  210. inc(tmpref.offset,tcgsize2size[location^.size]);
  211. dec(sizeleft,tcgsize2size[location^.size]);
  212. location := location^.next;
  213. end;
  214. end;
  215. procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
  216. var
  217. ref: treference;
  218. tmpreg: tregister;
  219. begin
  220. paraloc.check_simple_location;
  221. paramanager.allocparaloc(list,paraloc.location);
  222. case paraloc.location^.loc of
  223. LOC_REGISTER,LOC_CREGISTER:
  224. a_loadaddr_ref_reg(list,r,paraloc.location^.register);
  225. LOC_REFERENCE:
  226. begin
  227. reference_reset(ref,paraloc.alignment);
  228. ref.base := paraloc.location^.reference.index;
  229. ref.offset := paraloc.location^.reference.offset;
  230. tmpreg := getintregister(list,OS_ADDR);
  231. a_loadaddr_ref_reg(list,r,tmpreg);
  232. a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
  233. end;
  234. else
  235. internalerror(2002080701);
  236. end;
  237. end;
  238. procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
  239. begin
  240. list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
  241. {
  242. the compiler does not properly set this flag anymore in pass 1, and
  243. for now we only need it after pass 2 (I hope) (JM)
  244. if not(pi_do_call in current_procinfo.flags) then
  245. internalerror(2003060703);
  246. }
  247. include(current_procinfo.flags,pi_do_call);
  248. end;
  249. procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
  250. begin
  251. a_reg_alloc(list,NR_ZLO);
  252. a_reg_alloc(list,NR_ZHI);
  253. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
  254. list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
  255. list.concat(taicpu.op_none(A_ICALL));
  256. a_reg_dealloc(list,NR_ZLO);
  257. a_reg_dealloc(list,NR_ZHI);
  258. include(current_procinfo.flags,pi_do_call);
  259. end;
  260. procedure tcgavr.a_call_ref(list : TAsmList;ref: treference);
  261. begin
  262. a_reg_alloc(list,NR_ZLO);
  263. a_reg_alloc(list,NR_ZHI);
  264. a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_ZLO);
  265. list.concat(taicpu.op_none(A_ICALL));
  266. a_reg_dealloc(list,NR_ZLO);
  267. a_reg_dealloc(list,NR_ZHI);
  268. include(current_procinfo.flags,pi_do_call);
  269. end;
  270. procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
  271. var
  272. mask : qword;
  273. shift : byte;
  274. i : byte;
  275. tmpreg : tregister;
  276. begin
  277. mask:=$ff;
  278. shift:=0;
  279. case op of
  280. OP_OR:
  281. begin
  282. for i:=1 to tcgsize2size[size] do
  283. begin
  284. list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
  285. reg:=GetNextReg(reg);
  286. mask:=mask shl 8;
  287. inc(shift,8);
  288. end;
  289. end;
  290. OP_AND:
  291. begin
  292. for i:=1 to tcgsize2size[size] do
  293. begin
  294. list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
  295. reg:=GetNextReg(reg);
  296. mask:=mask shl 8;
  297. inc(shift,8);
  298. end;
  299. end;
  300. OP_SUB:
  301. begin
  302. list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
  303. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  304. begin
  305. for i:=2 to tcgsize2size[size] do
  306. begin
  307. reg:=GetNextReg(reg);
  308. mask:=mask shl 8;
  309. inc(shift,8);
  310. list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
  311. end;
  312. end;
  313. end;
  314. else
  315. begin
  316. tmpreg:=getintregister(list,size);
  317. a_load_const_reg(list,size,a,tmpreg);
  318. a_op_reg_reg(list,op,size,tmpreg,reg);
  319. end;
  320. end;
  321. end;
  322. procedure tcgavr.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
  323. var
  324. countreg,
  325. tmpreg: tregister;
  326. i : integer;
  327. instr : taicpu;
  328. paraloc1,paraloc2,paraloc3 : TCGPara;
  329. l1,l2 : tasmlabel;
  330. begin
  331. case op of
  332. OP_ADD:
  333. begin
  334. list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
  335. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  336. begin
  337. for i:=2 to tcgsize2size[size] do
  338. begin
  339. dst:=GetNextReg(dst);
  340. src:=GetNextReg(src);
  341. list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
  342. end;
  343. end
  344. else
  345. end;
  346. OP_SUB:
  347. begin
  348. list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
  349. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  350. begin
  351. for i:=2 to tcgsize2size[size] do
  352. begin
  353. dst:=GetNextReg(dst);
  354. src:=GetNextReg(src);
  355. list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
  356. end;
  357. end;
  358. end;
  359. OP_NEG:
  360. begin
  361. if src<>dst then
  362. a_load_reg_reg(list,size,size,src,dst);
  363. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  364. begin
  365. tmpreg:=GetNextReg(dst);
  366. for i:=2 to tcgsize2size[size] do
  367. begin
  368. list.concat(taicpu.op_reg(A_COM,tmpreg));
  369. tmpreg:=GetNextReg(tmpreg);
  370. end;
  371. list.concat(taicpu.op_reg(A_NEG,dst));
  372. tmpreg:=GetNextReg(dst);
  373. for i:=2 to tcgsize2size[size] do
  374. begin
  375. list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
  376. tmpreg:=GetNextReg(tmpreg);
  377. end;
  378. end
  379. else
  380. list.concat(taicpu.op_reg(A_NEG,dst));
  381. end;
  382. OP_NOT:
  383. begin
  384. for i:=1 to tcgsize2size[size] do
  385. begin
  386. if src<>dst then
  387. a_load_reg_reg(list,OS_8,OS_8,src,dst);
  388. list.concat(taicpu.op_reg(A_COM,dst));
  389. src:=GetNextReg(src);
  390. dst:=GetNextReg(dst);
  391. end;
  392. end;
  393. OP_MUL,OP_IMUL:
  394. begin
  395. if size in [OS_8,OS_S8] then
  396. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
  397. else if size=OS_16 then
  398. begin
  399. paraloc1.init;
  400. paraloc2.init;
  401. paraloc3.init;
  402. paramanager.getintparaloc(pocall_default,1,paraloc1);
  403. paramanager.getintparaloc(pocall_default,2,paraloc2);
  404. paramanager.getintparaloc(pocall_default,3,paraloc3);
  405. a_load_const_cgpara(list,OS_8,0,paraloc3);
  406. a_load_reg_cgpara(list,OS_16,src,paraloc2);
  407. a_load_reg_cgpara(list,OS_16,dst,paraloc1);
  408. paramanager.freecgpara(list,paraloc3);
  409. paramanager.freecgpara(list,paraloc2);
  410. paramanager.freecgpara(list,paraloc1);
  411. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  412. a_call_name(list,'FPC_MUL_WORD',false);
  413. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  414. cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
  415. cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
  416. paraloc3.done;
  417. paraloc2.done;
  418. paraloc1.done;
  419. end
  420. else
  421. internalerror(2011022002);
  422. end;
  423. OP_DIV,OP_IDIV:
  424. { special stuff, needs separate handling inside code }
  425. { generator }
  426. internalerror(2011022001);
  427. OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
  428. begin
  429. current_asmdata.getjumplabel(l1);
  430. current_asmdata.getjumplabel(l2);
  431. countreg:=getintregister(list,OS_8);
  432. a_load_reg_reg(list,size,OS_8,src,countreg);
  433. list.concat(taicpu.op_reg_const(A_CP,countreg,0));
  434. a_jmp_flags(list,F_EQ,l2);
  435. cg.a_label(list,l1);
  436. case op of
  437. OP_SHR:
  438. list.concat(taicpu.op_reg(A_LSR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  439. OP_SHL:
  440. list.concat(taicpu.op_reg(A_LSL,dst));
  441. OP_SAR:
  442. list.concat(taicpu.op_reg(A_ASR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  443. OP_ROR:
  444. begin
  445. { load carry? }
  446. if not(size in [OS_8,OS_S8]) then
  447. begin
  448. list.concat(taicpu.op_none(A_CLC));
  449. list.concat(taicpu.op_reg_const(A_SBRC,src,0));
  450. list.concat(taicpu.op_none(A_SEC));
  451. end;
  452. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-1)));
  453. end;
  454. OP_ROL:
  455. begin
  456. { load carry? }
  457. if not(size in [OS_8,OS_S8]) then
  458. begin
  459. list.concat(taicpu.op_none(A_CLC));
  460. list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg(dst,tcgsize2size[size]-1),7));
  461. list.concat(taicpu.op_none(A_SEC));
  462. end;
  463. list.concat(taicpu.op_reg(A_ROL,dst))
  464. end;
  465. else
  466. internalerror(2011030901);
  467. end;
  468. if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
  469. begin
  470. for i:=2 to tcgsize2size[size] do
  471. begin
  472. case op of
  473. OP_ROR,
  474. OP_SHR:
  475. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  476. OP_ROL,
  477. OP_SHL:
  478. list.concat(taicpu.op_reg(A_ROL,GetOffsetReg(dst,i-1)));
  479. OP_SAR:
  480. list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
  481. else
  482. internalerror(2011030902);
  483. end;
  484. end;
  485. end;
  486. a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
  487. a_jmp_flags(list,F_NE,l1);
  488. // keep registers alive
  489. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  490. cg.a_label(list,l2);
  491. end;
  492. OP_AND,OP_OR,OP_XOR:
  493. begin
  494. for i:=1 to tcgsize2size[size] do
  495. begin
  496. list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
  497. dst:=GetNextReg(dst);
  498. src:=GetNextReg(src);
  499. end;
  500. end;
  501. else
  502. internalerror(2011022004);
  503. end;
  504. end;
  505. procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
  506. var
  507. mask : qword;
  508. shift : byte;
  509. i : byte;
  510. begin
  511. mask:=$ff;
  512. shift:=0;
  513. for i:=1 to tcgsize2size[size] do
  514. begin
  515. if ((qword(a) and mask) shr shift)=0 then
  516. emit_mov(list,reg,NR_R1)
  517. else
  518. list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
  519. mask:=mask shl 8;
  520. inc(shift,8);
  521. reg:=GetNextReg(reg);
  522. end;
  523. end;
  524. function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
  525. procedure maybegetcpuregister(list:tasmlist;reg : tregister);
  526. begin
  527. { allocate the register only, if a cpu register is passed }
  528. if getsupreg(reg)<first_int_imreg then
  529. getcpuregister(list,reg);
  530. end;
  531. var
  532. tmpref : treference;
  533. l : tasmlabel;
  534. begin
  535. Result:=ref;
  536. if ref.addressmode<>AM_UNCHANGED then
  537. internalerror(2011021701);
  538. { Be sure to have a base register }
  539. if (ref.base=NR_NO) then
  540. begin
  541. { only symbol+offset? }
  542. if ref.index=NR_NO then
  543. exit;
  544. ref.base:=ref.index;
  545. ref.index:=NR_NO;
  546. end;
  547. if assigned(ref.symbol) or (ref.offset<>0) then
  548. begin
  549. reference_reset(tmpref,0);
  550. tmpref.symbol:=ref.symbol;
  551. tmpref.offset:=ref.offset;
  552. tmpref.refaddr:=addr_lo8;
  553. maybegetcpuregister(list,tmpreg);
  554. list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
  555. tmpref.refaddr:=addr_hi8;
  556. maybegetcpuregister(list,GetNextReg(tmpreg));
  557. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
  558. if (ref.base<>NR_NO) then
  559. begin
  560. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  561. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  562. end;
  563. if (ref.index<>NR_NO) then
  564. begin
  565. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
  566. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
  567. end;
  568. ref.symbol:=nil;
  569. ref.offset:=0;
  570. ref.base:=tmpreg;
  571. ref.index:=NR_NO;
  572. end
  573. else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
  574. begin
  575. maybegetcpuregister(list,tmpreg);
  576. emit_mov(list,tmpreg,ref.index);
  577. maybegetcpuregister(list,GetNextReg(tmpreg));
  578. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  579. list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
  580. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
  581. ref.base:=tmpreg;
  582. ref.index:=NR_NO;
  583. end
  584. else if (ref.base<>NR_NO) then
  585. begin
  586. maybegetcpuregister(list,tmpreg);
  587. emit_mov(list,tmpreg,ref.base);
  588. maybegetcpuregister(list,GetNextReg(tmpreg));
  589. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
  590. ref.base:=tmpreg;
  591. ref.index:=NR_NO;
  592. end
  593. else if (ref.index<>NR_NO) then
  594. begin
  595. maybegetcpuregister(list,tmpreg);
  596. emit_mov(list,tmpreg,ref.index);
  597. maybegetcpuregister(list,GetNextReg(tmpreg));
  598. emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
  599. ref.base:=tmpreg;
  600. ref.index:=NR_NO;
  601. end;
  602. Result:=ref;
  603. end;
  604. procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
  605. var
  606. href : treference;
  607. conv_done: boolean;
  608. tmpreg : tregister;
  609. i : integer;
  610. QuickRef : Boolean;
  611. begin
  612. QuickRef:=false;
  613. if not((Ref.addressmode=AM_UNCHANGED) and
  614. (Ref.symbol=nil) and
  615. ((Ref.base=NR_R28) or
  616. (Ref.base=NR_R29)) and
  617. (Ref.Index=NR_No) and
  618. (Ref.Offset in [0..64-tcgsize2size[tosize]])) and
  619. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  620. href:=normalize_ref(list,Ref,NR_R30)
  621. else
  622. begin
  623. QuickRef:=true;
  624. href:=Ref;
  625. end;
  626. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  627. internalerror(2011021307);
  628. conv_done:=false;
  629. if tosize<>fromsize then
  630. begin
  631. conv_done:=true;
  632. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  633. fromsize:=tosize;
  634. case fromsize of
  635. OS_8:
  636. begin
  637. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  638. href.addressmode:=AM_POSTINCREMENT;
  639. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  640. for i:=2 to tcgsize2size[tosize] do
  641. begin
  642. if QuickRef then
  643. inc(href.offset);
  644. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  645. href.addressmode:=AM_POSTINCREMENT
  646. else
  647. href.addressmode:=AM_UNCHANGED;
  648. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  649. end;
  650. end;
  651. OS_S8:
  652. begin
  653. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  654. href.addressmode:=AM_POSTINCREMENT;
  655. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  656. if tcgsize2size[tosize]>1 then
  657. begin
  658. tmpreg:=getintregister(list,OS_8);
  659. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  660. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  661. list.concat(taicpu.op_reg(A_COM,tmpreg));
  662. for i:=2 to tcgsize2size[tosize] do
  663. begin
  664. if QuickRef then
  665. inc(href.offset);
  666. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  667. href.addressmode:=AM_POSTINCREMENT
  668. else
  669. href.addressmode:=AM_UNCHANGED;
  670. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  671. end;
  672. end;
  673. end;
  674. OS_16:
  675. begin
  676. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  677. href.addressmode:=AM_POSTINCREMENT;
  678. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  679. if QuickRef then
  680. inc(href.offset)
  681. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  682. href.addressmode:=AM_POSTINCREMENT
  683. else
  684. href.addressmode:=AM_UNCHANGED;
  685. reg:=GetNextReg(reg);
  686. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  687. for i:=3 to tcgsize2size[tosize] do
  688. begin
  689. if QuickRef then
  690. inc(href.offset);
  691. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  692. href.addressmode:=AM_POSTINCREMENT
  693. else
  694. href.addressmode:=AM_UNCHANGED;
  695. list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
  696. end;
  697. end;
  698. OS_S16:
  699. begin
  700. if not(QuickRef) and (tcgsize2size[tosize]>1) then
  701. href.addressmode:=AM_POSTINCREMENT;
  702. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  703. if QuickRef then
  704. inc(href.offset)
  705. else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
  706. href.addressmode:=AM_POSTINCREMENT
  707. else
  708. href.addressmode:=AM_UNCHANGED;
  709. reg:=GetNextReg(reg);
  710. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  711. if tcgsize2size[tosize]>2 then
  712. begin
  713. tmpreg:=getintregister(list,OS_8);
  714. list.concat(taicpu.op_reg(A_CLR,tmpreg));
  715. list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
  716. list.concat(taicpu.op_reg(A_COM,tmpreg));
  717. for i:=3 to tcgsize2size[tosize] do
  718. begin
  719. if QuickRef then
  720. inc(href.offset);
  721. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  722. href.addressmode:=AM_POSTINCREMENT
  723. else
  724. href.addressmode:=AM_UNCHANGED;
  725. list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
  726. end;
  727. end;
  728. end;
  729. else
  730. conv_done:=false;
  731. end;
  732. end;
  733. if not conv_done then
  734. begin
  735. for i:=1 to tcgsize2size[fromsize] do
  736. begin
  737. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  738. href.addressmode:=AM_POSTINCREMENT
  739. else
  740. href.addressmode:=AM_UNCHANGED;
  741. list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
  742. if QuickRef then
  743. inc(href.offset);
  744. reg:=GetNextReg(reg);
  745. end;
  746. end;
  747. if not(QuickRef) then
  748. begin
  749. ungetcpuregister(list,href.base);
  750. ungetcpuregister(list,GetNextReg(href.base));
  751. end;
  752. end;
  753. procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
  754. const Ref : treference;reg : tregister);
  755. var
  756. href : treference;
  757. conv_done: boolean;
  758. tmpreg : tregister;
  759. i : integer;
  760. QuickRef : boolean;
  761. begin
  762. QuickRef:=false;
  763. if not((Ref.addressmode=AM_UNCHANGED) and
  764. (Ref.symbol=nil) and
  765. ((Ref.base=NR_R28) or
  766. (Ref.base=NR_R29)) and
  767. (Ref.Index=NR_No) and
  768. (Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
  769. not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
  770. href:=normalize_ref(list,Ref,NR_R30)
  771. else
  772. begin
  773. QuickRef:=true;
  774. href:=Ref;
  775. end;
  776. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  777. internalerror(2011021307);
  778. conv_done:=false;
  779. if tosize<>fromsize then
  780. begin
  781. conv_done:=true;
  782. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  783. fromsize:=tosize;
  784. case fromsize of
  785. OS_8:
  786. begin
  787. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  788. for i:=2 to tcgsize2size[tosize] do
  789. begin
  790. reg:=GetNextReg(reg);
  791. list.concat(taicpu.op_reg(A_CLR,reg));
  792. end;
  793. end;
  794. OS_S8:
  795. begin
  796. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  797. tmpreg:=reg;
  798. if tcgsize2size[tosize]>1 then
  799. begin
  800. reg:=GetNextReg(reg);
  801. list.concat(taicpu.op_reg(A_CLR,reg));
  802. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  803. list.concat(taicpu.op_reg(A_COM,reg));
  804. tmpreg:=reg;
  805. for i:=3 to tcgsize2size[tosize] do
  806. begin
  807. reg:=GetNextReg(reg);
  808. emit_mov(list,reg,tmpreg);
  809. end;
  810. end;
  811. end;
  812. OS_16:
  813. begin
  814. if not(QuickRef) then
  815. href.addressmode:=AM_POSTINCREMENT;
  816. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  817. if QuickRef then
  818. inc(href.offset);
  819. href.addressmode:=AM_UNCHANGED;
  820. reg:=GetNextReg(reg);
  821. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  822. for i:=3 to tcgsize2size[tosize] do
  823. begin
  824. reg:=GetNextReg(reg);
  825. list.concat(taicpu.op_reg(A_CLR,reg));
  826. end;
  827. end;
  828. OS_S16:
  829. begin
  830. if not(QuickRef) then
  831. href.addressmode:=AM_POSTINCREMENT;
  832. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  833. if QuickRef then
  834. inc(href.offset);
  835. href.addressmode:=AM_UNCHANGED;
  836. reg:=GetNextReg(reg);
  837. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  838. tmpreg:=reg;
  839. reg:=GetNextReg(reg);
  840. list.concat(taicpu.op_reg(A_CLR,reg));
  841. list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
  842. list.concat(taicpu.op_reg(A_COM,reg));
  843. tmpreg:=reg;
  844. for i:=4 to tcgsize2size[tosize] do
  845. begin
  846. reg:=GetNextReg(reg);
  847. emit_mov(list,reg,tmpreg);
  848. end;
  849. end;
  850. else
  851. conv_done:=false;
  852. end;
  853. end;
  854. if not conv_done then
  855. begin
  856. for i:=1 to tcgsize2size[fromsize] do
  857. begin
  858. if not(QuickRef) and (i<tcgsize2size[fromsize]) then
  859. href.addressmode:=AM_POSTINCREMENT
  860. else
  861. href.addressmode:=AM_UNCHANGED;
  862. list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
  863. if QuickRef then
  864. inc(href.offset);
  865. reg:=GetNextReg(reg);
  866. end;
  867. end;
  868. if not(QuickRef) then
  869. begin
  870. ungetcpuregister(list,href.base);
  871. ungetcpuregister(list,GetNextReg(href.base));
  872. end;
  873. end;
  874. procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
  875. var
  876. conv_done: boolean;
  877. tmpreg : tregister;
  878. i : integer;
  879. begin
  880. if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
  881. internalerror(2011021310);
  882. conv_done:=false;
  883. if tosize<>fromsize then
  884. begin
  885. conv_done:=true;
  886. if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
  887. fromsize:=tosize;
  888. case fromsize of
  889. OS_8:
  890. begin
  891. emit_mov(list,reg2,reg1);
  892. for i:=2 to tcgsize2size[tosize] do
  893. begin
  894. reg2:=GetNextReg(reg2);
  895. list.concat(taicpu.op_reg(A_CLR,reg2));
  896. end;
  897. end;
  898. OS_S8:
  899. begin
  900. { dest is always at least 16 bit at this point }
  901. emit_mov(list,reg2,reg1);
  902. reg2:=GetNextReg(reg2);
  903. list.concat(taicpu.op_reg(A_CLR,reg2));
  904. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  905. list.concat(taicpu.op_reg(A_COM,reg2));
  906. tmpreg:=reg2;
  907. for i:=3 to tcgsize2size[tosize] do
  908. begin
  909. reg2:=GetNextReg(reg2);
  910. emit_mov(list,reg2,tmpreg);
  911. end;
  912. end;
  913. OS_16:
  914. begin
  915. emit_mov(list,reg2,reg1);
  916. reg1:=GetNextReg(reg1);
  917. reg2:=GetNextReg(reg2);
  918. emit_mov(list,reg2,reg1);
  919. for i:=3 to tcgsize2size[tosize] do
  920. begin
  921. reg2:=GetNextReg(reg2);
  922. list.concat(taicpu.op_reg(A_CLR,reg2));
  923. end;
  924. end;
  925. OS_S16:
  926. begin
  927. { dest is always at least 32 bit at this point }
  928. emit_mov(list,reg2,reg1);
  929. reg1:=GetNextReg(reg1);
  930. reg2:=GetNextReg(reg2);
  931. emit_mov(list,reg2,reg1);
  932. reg2:=GetNextReg(reg2);
  933. list.concat(taicpu.op_reg(A_CLR,reg2));
  934. list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
  935. list.concat(taicpu.op_reg(A_COM,reg2));
  936. tmpreg:=reg2;
  937. for i:=4 to tcgsize2size[tosize] do
  938. begin
  939. reg2:=GetNextReg(reg2);
  940. emit_mov(list,reg2,tmpreg);
  941. end;
  942. end;
  943. else
  944. conv_done:=false;
  945. end;
  946. end;
  947. if not conv_done and (reg1<>reg2) then
  948. begin
  949. for i:=1 to tcgsize2size[fromsize] do
  950. begin
  951. emit_mov(list,reg2,reg1);
  952. reg1:=GetNextReg(reg1);
  953. reg2:=GetNextReg(reg2);
  954. end;
  955. end;
  956. end;
  957. { comparison operations }
  958. procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
  959. cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
  960. var
  961. swapped : boolean;
  962. tmpreg : tregister;
  963. i : byte;
  964. begin
  965. if a=0 then
  966. begin
  967. { swap parameters? }
  968. case cmp_op of
  969. OC_GT:
  970. begin
  971. swapped:=true;
  972. cmp_op:=OC_LT;
  973. end;
  974. OC_LTE:
  975. begin
  976. swapped:=true;
  977. cmp_op:=OC_GTE;
  978. end;
  979. OC_BE:
  980. begin
  981. swapped:=true;
  982. cmp_op:=OC_AE;
  983. end;
  984. OC_A:
  985. begin
  986. swapped:=true;
  987. cmp_op:=OC_A;
  988. end;
  989. end;
  990. if swapped then
  991. list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
  992. else
  993. list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
  994. for i:=2 to tcgsize2size[size] do
  995. begin
  996. reg:=GetNextReg(reg);
  997. if swapped then
  998. list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
  999. else
  1000. list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
  1001. end;
  1002. a_jmp_cond(list,cmp_op,l);
  1003. end
  1004. else
  1005. inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
  1006. end;
  1007. procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
  1008. cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
  1009. var
  1010. swapped : boolean;
  1011. tmpreg : tregister;
  1012. i : byte;
  1013. begin
  1014. { swap parameters? }
  1015. case cmp_op of
  1016. OC_GT:
  1017. begin
  1018. swapped:=true;
  1019. cmp_op:=OC_LT;
  1020. end;
  1021. OC_LTE:
  1022. begin
  1023. swapped:=true;
  1024. cmp_op:=OC_GTE;
  1025. end;
  1026. OC_BE:
  1027. begin
  1028. swapped:=true;
  1029. cmp_op:=OC_AE;
  1030. end;
  1031. OC_A:
  1032. begin
  1033. swapped:=true;
  1034. cmp_op:=OC_A;
  1035. end;
  1036. end;
  1037. if swapped then
  1038. begin
  1039. tmpreg:=reg1;
  1040. reg1:=reg2;
  1041. reg2:=tmpreg;
  1042. end;
  1043. list.concat(taicpu.op_reg_reg(A_CP,reg1,reg2));
  1044. for i:=2 to tcgsize2size[size] do
  1045. begin
  1046. reg1:=GetNextReg(reg1);
  1047. reg2:=GetNextReg(reg2);
  1048. list.concat(taicpu.op_reg_reg(A_CPC,reg1,reg2));
  1049. end;
  1050. a_jmp_cond(list,cmp_op,l);
  1051. end;
  1052. procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
  1053. var
  1054. ai : taicpu;
  1055. begin
  1056. ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
  1057. ai.is_jmp:=true;
  1058. list.concat(ai);
  1059. end;
  1060. procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
  1061. var
  1062. ai : taicpu;
  1063. begin
  1064. ai:=taicpu.op_sym(A_JMP,l);
  1065. ai.is_jmp:=true;
  1066. list.concat(ai);
  1067. end;
  1068. procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
  1069. var
  1070. ai : taicpu;
  1071. begin
  1072. ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
  1073. ai.is_jmp:=true;
  1074. list.concat(ai);
  1075. end;
  1076. procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
  1077. var
  1078. l : TAsmLabel;
  1079. tmpflags : TResFlags;
  1080. begin
  1081. current_asmdata.getjumplabel(l);
  1082. {
  1083. if flags_to_cond(f) then
  1084. begin
  1085. tmpflags:=f;
  1086. inverse_flags(tmpflags);
  1087. list.concat(taicpu.op_reg(A_CLR,reg));
  1088. a_jmp_flags(list,tmpflags,l);
  1089. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1090. end
  1091. else
  1092. }
  1093. begin
  1094. list.concat(taicpu.op_reg_const(A_LDI,reg,1));
  1095. a_jmp_flags(list,f,l);
  1096. list.concat(taicpu.op_reg(A_CLR,reg));
  1097. end;
  1098. cg.a_label(list,l);
  1099. end;
  1100. procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
  1101. var
  1102. i : integer;
  1103. begin
  1104. case value of
  1105. 0:
  1106. ;
  1107. -14..-1:
  1108. begin
  1109. if ((-value) mod 2)<>0 then
  1110. list.concat(taicpu.op_reg(A_PUSH,NR_R0));
  1111. for i:=1 to (-value) div 2 do
  1112. list.concat(taicpu.op_const(A_RCALL,0));
  1113. end;
  1114. 1..7:
  1115. begin
  1116. for i:=1 to value do
  1117. list.concat(taicpu.op_reg(A_POP,NR_R0));
  1118. end;
  1119. else
  1120. begin
  1121. list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
  1122. list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
  1123. // get SREG
  1124. list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
  1125. // block interrupts
  1126. list.concat(taicpu.op_none(A_CLI));
  1127. // write high SP
  1128. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
  1129. // release interrupts
  1130. list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
  1131. // write low SP
  1132. list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
  1133. end;
  1134. end;
  1135. end;
  1136. function tcgavr.GetLoad(const ref: treference) : tasmop;
  1137. begin
  1138. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1139. result:=A_LDS
  1140. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1141. result:=A_LDD
  1142. else
  1143. result:=A_LD;
  1144. end;
  1145. function tcgavr.GetStore(const ref: treference) : tasmop;
  1146. begin
  1147. if (ref.base=NR_NO) and (ref.index=NR_NO) then
  1148. result:=A_STS
  1149. else if (ref.base<>NR_NO) and (ref.offset<>0) then
  1150. result:=A_STD
  1151. else
  1152. result:=A_ST;
  1153. end;
  1154. procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
  1155. var
  1156. regs : tcpuregisterset;
  1157. reg : tsuperregister;
  1158. begin
  1159. if not(nostackframe) then
  1160. begin
  1161. { save int registers }
  1162. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1163. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1164. regs:=regs+[RS_R28,RS_R29];
  1165. for reg:=RS_R31 downto RS_R0 do
  1166. if reg in regs then
  1167. list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1168. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1169. begin
  1170. list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
  1171. list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
  1172. end
  1173. else
  1174. { the framepointer cannot be omitted on avr because sp
  1175. is not a register but part of the i/o map
  1176. }
  1177. internalerror(2011021901);
  1178. a_adjust_sp(list,-localsize);
  1179. end;
  1180. end;
  1181. procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
  1182. var
  1183. regs : tcpuregisterset;
  1184. reg : TSuperRegister;
  1185. LocalSize : longint;
  1186. begin
  1187. if not(nostackframe) then
  1188. begin
  1189. if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
  1190. begin
  1191. LocalSize:=current_procinfo.calc_stackframe_size;
  1192. a_adjust_sp(list,LocalSize);
  1193. regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
  1194. for reg:=RS_R0 to RS_R31 do
  1195. if reg in regs then
  1196. list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
  1197. end
  1198. else
  1199. { the framepointer cannot be omitted on avr because sp
  1200. is not a register but part of the i/o map
  1201. }
  1202. internalerror(2011021902);
  1203. end;
  1204. list.concat(taicpu.op_none(A_RET));
  1205. end;
  1206. procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
  1207. var
  1208. tmpref : treference;
  1209. begin
  1210. if ref.addressmode<>AM_UNCHANGED then
  1211. internalerror(2011021701);
  1212. if assigned(ref.symbol) or (ref.offset<>0) then
  1213. begin
  1214. reference_reset(tmpref,0);
  1215. tmpref.symbol:=ref.symbol;
  1216. tmpref.offset:=ref.offset;
  1217. tmpref.refaddr:=addr_lo8;
  1218. list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
  1219. tmpref.refaddr:=addr_hi8;
  1220. list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
  1221. if (ref.base<>NR_NO) then
  1222. begin
  1223. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
  1224. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
  1225. end;
  1226. if (ref.index<>NR_NO) then
  1227. begin
  1228. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1229. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1230. end;
  1231. end
  1232. else if (ref.base<>NR_NO)then
  1233. begin
  1234. emit_mov(list,r,ref.base);
  1235. emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
  1236. if (ref.index<>NR_NO) then
  1237. begin
  1238. list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
  1239. list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
  1240. end;
  1241. end
  1242. else if (ref.index<>NR_NO) then
  1243. begin
  1244. emit_mov(list,r,ref.index);
  1245. emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
  1246. end;
  1247. end;
  1248. procedure tcgavr.fixref(list : TAsmList;var ref : treference);
  1249. begin
  1250. internalerror(2011021320);
  1251. end;
  1252. procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
  1253. var
  1254. paraloc1,paraloc2,paraloc3 : TCGPara;
  1255. begin
  1256. paraloc1.init;
  1257. paraloc2.init;
  1258. paraloc3.init;
  1259. paramanager.getintparaloc(pocall_default,1,paraloc1);
  1260. paramanager.getintparaloc(pocall_default,2,paraloc2);
  1261. paramanager.getintparaloc(pocall_default,3,paraloc3);
  1262. a_load_const_cgpara(list,OS_INT,len,paraloc3);
  1263. a_loadaddr_ref_cgpara(list,dest,paraloc2);
  1264. a_loadaddr_ref_cgpara(list,source,paraloc1);
  1265. paramanager.freecgpara(list,paraloc3);
  1266. paramanager.freecgpara(list,paraloc2);
  1267. paramanager.freecgpara(list,paraloc1);
  1268. alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1269. a_call_name_static(list,'FPC_MOVE');
  1270. dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
  1271. paraloc3.done;
  1272. paraloc2.done;
  1273. paraloc1.done;
  1274. end;
  1275. procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
  1276. var
  1277. countreg,tmpreg : tregister;
  1278. srcref,dstref : treference;
  1279. copysize,countregsize : tcgsize;
  1280. l : TAsmLabel;
  1281. i : longint;
  1282. SrcQuickRef, DestQuickRef : Boolean;
  1283. begin
  1284. if len>16 then
  1285. begin
  1286. current_asmdata.getjumplabel(l);
  1287. reference_reset(srcref,0);
  1288. reference_reset(dstref,0);
  1289. srcref.base:=NR_R30;
  1290. srcref.addressmode:=AM_POSTINCREMENT;
  1291. dstref.base:=NR_R26;
  1292. dstref.addressmode:=AM_POSTINCREMENT;
  1293. copysize:=OS_8;
  1294. if len<256 then
  1295. countregsize:=OS_8
  1296. else if len<65536 then
  1297. countregsize:=OS_16
  1298. else
  1299. internalerror(2011022007);
  1300. countreg:=getintregister(list,countregsize);
  1301. a_load_const_reg(list,countregsize,len,countreg);
  1302. a_loadaddr_ref_reg(list,source,NR_R30);
  1303. tmpreg:=getaddressregister(list);
  1304. a_loadaddr_ref_reg(list,dest,tmpreg);
  1305. { X is used for spilling code so we can load it
  1306. only by a push/pop sequence, this can be
  1307. optimized later on by the peephole optimizer
  1308. }
  1309. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1310. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1311. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1312. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1313. cg.a_label(list,l);
  1314. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1315. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1316. a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
  1317. a_jmp_flags(list,F_NE,l);
  1318. // keep registers alive
  1319. list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
  1320. end
  1321. else
  1322. begin
  1323. SrcQuickRef:=false;
  1324. DestQuickRef:=false;
  1325. if not((source.addressmode=AM_UNCHANGED) and
  1326. (source.symbol=nil) and
  1327. ((source.base=NR_R28) or
  1328. (source.base=NR_R29)) and
  1329. (source.Index=NR_NO) and
  1330. (source.Offset in [0..64-len])) and
  1331. not((source.Base=NR_NO) and (source.Index=NR_NO)) then
  1332. srcref:=normalize_ref(list,source,NR_R30)
  1333. else
  1334. begin
  1335. SrcQuickRef:=true;
  1336. srcref:=source;
  1337. end;
  1338. if not((dest.addressmode=AM_UNCHANGED) and
  1339. (dest.symbol=nil) and
  1340. ((dest.base=NR_R28) or
  1341. (dest.base=NR_R29)) and
  1342. (dest.Index=NR_No) and
  1343. (dest.Offset in [0..64-len])) and
  1344. not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
  1345. begin
  1346. if not(SrcQuickRef) then
  1347. begin
  1348. tmpreg:=getaddressregister(list);
  1349. dstref:=normalize_ref(list,dest,tmpreg);
  1350. { X is used for spilling code so we can load it
  1351. only by a push/pop sequence, this can be
  1352. optimized later on by the peephole optimizer
  1353. }
  1354. list.concat(taicpu.op_reg(A_PUSH,tmpreg));
  1355. list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
  1356. list.concat(taicpu.op_reg(A_POP,NR_R27));
  1357. list.concat(taicpu.op_reg(A_POP,NR_R26));
  1358. dstref.base:=NR_R26;
  1359. end
  1360. else
  1361. dstref:=normalize_ref(list,dest,NR_R30);
  1362. end
  1363. else
  1364. begin
  1365. DestQuickRef:=true;
  1366. dstref:=dest;
  1367. end;
  1368. for i:=1 to len do
  1369. begin
  1370. if not(SrcQuickRef) and (i<len) then
  1371. srcref.addressmode:=AM_POSTINCREMENT
  1372. else
  1373. srcref.addressmode:=AM_UNCHANGED;
  1374. if not(DestQuickRef) and (i<len) then
  1375. dstref.addressmode:=AM_POSTINCREMENT
  1376. else
  1377. dstref.addressmode:=AM_UNCHANGED;
  1378. list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
  1379. list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
  1380. if SrcQuickRef then
  1381. inc(srcref.offset);
  1382. if DestQuickRef then
  1383. inc(dstref.offset);
  1384. end;
  1385. if not(SrcQuickRef) then
  1386. begin
  1387. ungetcpuregister(list,srcref.base);
  1388. ungetcpuregister(list,GetNextReg(srcref.base));
  1389. end;
  1390. end;
  1391. end;
  1392. procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
  1393. var
  1394. hl : tasmlabel;
  1395. ai : taicpu;
  1396. cond : TAsmCond;
  1397. begin
  1398. if not(cs_check_overflow in current_settings.localswitches) then
  1399. exit;
  1400. current_asmdata.getjumplabel(hl);
  1401. if not ((def.typ=pointerdef) or
  1402. ((def.typ=orddef) and
  1403. (torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
  1404. pasbool8,pasbool16,pasbool32,pasbool64]))) then
  1405. cond:=C_VC
  1406. else
  1407. cond:=C_CC;
  1408. ai:=Taicpu.Op_Sym(A_BRxx,hl);
  1409. ai.SetCondition(cond);
  1410. ai.is_jmp:=true;
  1411. list.concat(ai);
  1412. a_call_name(list,'FPC_OVERFLOW',false);
  1413. a_label(list,hl);
  1414. end;
  1415. procedure tcgavr.g_save_registers(list: TAsmList);
  1416. begin
  1417. { this is done by the entry code }
  1418. end;
  1419. procedure tcgavr.g_restore_registers(list: TAsmList);
  1420. begin
  1421. { this is done by the exit code }
  1422. end;
  1423. procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
  1424. var
  1425. ai1,ai2 : taicpu;
  1426. hl : TAsmLabel;
  1427. begin
  1428. ai1:=Taicpu.Op_sym(A_BRxx,l);
  1429. ai1.is_jmp:=true;
  1430. hl:=nil;
  1431. case cond of
  1432. OC_EQ:
  1433. ai1.SetCondition(C_EQ);
  1434. OC_GT:
  1435. begin
  1436. { emulate GT }
  1437. current_asmdata.getjumplabel(hl);
  1438. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1439. ai2.SetCondition(C_EQ);
  1440. ai2.is_jmp:=true;
  1441. list.concat(ai2);
  1442. ai1.SetCondition(C_GE);
  1443. end;
  1444. OC_LT:
  1445. ai1.SetCondition(C_LT);
  1446. OC_GTE:
  1447. ai1.SetCondition(C_GE);
  1448. OC_LTE:
  1449. begin
  1450. { emulate LTE }
  1451. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1452. ai2.SetCondition(C_EQ);
  1453. ai2.is_jmp:=true;
  1454. list.concat(ai2);
  1455. ai1.SetCondition(C_LT);
  1456. end;
  1457. OC_NE:
  1458. ai1.SetCondition(C_NE);
  1459. OC_BE:
  1460. begin
  1461. { emulate BE }
  1462. ai2:=Taicpu.Op_Sym(A_BRxx,l);
  1463. ai2.SetCondition(C_EQ);
  1464. ai2.is_jmp:=true;
  1465. list.concat(ai2);
  1466. ai1.SetCondition(C_LO);
  1467. end;
  1468. OC_B:
  1469. ai1.SetCondition(C_LO);
  1470. OC_AE:
  1471. ai1.SetCondition(C_SH);
  1472. OC_A:
  1473. begin
  1474. { emulate A (unsigned GT) }
  1475. current_asmdata.getjumplabel(hl);
  1476. ai2:=Taicpu.Op_Sym(A_BRxx,hl);
  1477. ai2.SetCondition(C_EQ);
  1478. ai2.is_jmp:=true;
  1479. list.concat(ai2);
  1480. ai1.SetCondition(C_SH);
  1481. end;
  1482. else
  1483. internalerror(2011082501);
  1484. end;
  1485. list.concat(ai1);
  1486. if assigned(hl) then
  1487. a_label(list,hl);
  1488. end;
  1489. procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
  1490. begin
  1491. internalerror(2011021324);
  1492. end;
  1493. procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
  1494. var
  1495. instr: taicpu;
  1496. begin
  1497. instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
  1498. list.Concat(instr);
  1499. { Notify the register allocator that we have written a move instruction so
  1500. it can try to eliminate it. }
  1501. add_move_instruction(instr);
  1502. end;
  1503. procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
  1504. begin
  1505. { TODO : a_op64_reg_reg }
  1506. end;
  1507. procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
  1508. begin
  1509. { TODO : a_op64_const_reg }
  1510. end;
  1511. procedure create_codegen;
  1512. begin
  1513. cg:=tcgavr.create;
  1514. cg64:=tcg64favr.create;
  1515. end;
  1516. end.