arm.inc 17 KB

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  1. {
  2. This file is part of the Free Pascal run time library.
  3. Copyright (c) 2003 by the Free Pascal development team.
  4. Processor dependent implementation for the system unit for
  5. ARM
  6. See the file COPYING.FPC, included in this distribution,
  7. for details about the copyright.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  11. **********************************************************************}
  12. {$asmmode gas}
  13. {$ifndef FPC_SYSTEM_HAS_MOVE}
  14. {$define FPC_SYSTEM_FPC_MOVE}
  15. {$endif FPC_SYSTEM_HAS_MOVE}
  16. {$ifdef FPC_SYSTEM_FPC_MOVE}
  17. const
  18. cpu_has_edsp : boolean = false;
  19. in_edsp_test : boolean = false;
  20. {$endif FPC_SYSTEM_FPC_MOVE}
  21. {$if not(defined(wince)) and not(defined(gba)) and not(defined(nds)) and not(defined(FPUSOFT)) and not(defined(FPULIBGCC))}
  22. {$define FPC_SYSTEM_HAS_SYSINITFPU}
  23. {$if not defined(darwin) and not defined(FPUVFPV2) and not defined(FPUVFPV3)}
  24. Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  25. begin
  26. { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
  27. asm
  28. rfs r0
  29. and r0,r0,#0xffe0ffff
  30. orr r0,r0,#0x00070000
  31. wfs r0
  32. end;
  33. end;
  34. {$else}
  35. Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  36. begin
  37. { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
  38. asm
  39. fmrx r0,fpscr
  40. // set "round to nearest" mode
  41. and r0,r0,#0xff3fffff
  42. // mask "exception happened" and overflow flags
  43. and r0,r0,#0xffffff20
  44. // mask exception flags
  45. and r0,r0,#0xffff40ff
  46. {$ifndef darwin}
  47. // Floating point exceptions cause kernel panics on iPhoneOS 2.2.1...
  48. // disable flush-to-zero mode (IEEE math compliant)
  49. and r0,r0,#0xfeffffff
  50. // enable invalid operation, div-by-zero and overflow exceptions
  51. orr r0,r0,#0x00000700
  52. {$endif}
  53. fmxr fpscr,r0
  54. end;
  55. end;
  56. {$endif}
  57. {$endif}
  58. procedure fpc_cpuinit;
  59. begin
  60. { don't let libraries influence the FPU cw set by the host program }
  61. if not IsLibrary then
  62. SysInitFPU;
  63. end;
  64. {$ifdef wince}
  65. function _controlfp(new: DWORD; mask: DWORD): DWORD; cdecl; external 'coredll';
  66. {$define FPC_SYSTEM_HAS_SYSRESETFPU}
  67. Procedure SysResetFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  68. begin
  69. softfloat_exception_flags:=0;
  70. end;
  71. {$define FPC_SYSTEM_HAS_SYSINITFPU}
  72. Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
  73. begin
  74. softfloat_exception_mask:=float_flag_underflow or float_flag_inexact or float_flag_denormal;
  75. { Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
  76. { FPU precision 64 bit, rounding to nearest, affine infinity }
  77. _controlfp($000C0003, $030F031F);
  78. end;
  79. {$endif wince}
  80. {****************************************************************************
  81. stack frame related stuff
  82. ****************************************************************************}
  83. {$IFNDEF INTERNAL_BACKTRACE}
  84. {$define FPC_SYSTEM_HAS_GET_FRAME}
  85. function get_frame:pointer;assembler;nostackframe;
  86. asm
  87. mov r0,r11
  88. end;
  89. {$ENDIF not INTERNAL_BACKTRACE}
  90. {$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
  91. function get_caller_addr(framebp:pointer):pointer;assembler;
  92. asm
  93. movs r0,r0
  94. beq .Lg_a_null
  95. ldr r0,[r0,#-4]
  96. .Lg_a_null:
  97. end;
  98. {$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
  99. function get_caller_frame(framebp:pointer):pointer;assembler;
  100. asm
  101. movs r0,r0
  102. beq .Lgnf_null
  103. // see comments in arm/cgcpu.pas, g_proc_entry
  104. ldr r0,[r0,#-12]
  105. .Lgnf_null:
  106. end;
  107. {$define FPC_SYSTEM_HAS_SPTR}
  108. Function Sptr : pointer;assembler;
  109. asm
  110. mov r0,sp
  111. end;
  112. {$ifndef FPC_SYSTEM_HAS_FILLCHAR}
  113. {$define FPC_SYSTEM_HAS_FILLCHAR}
  114. Procedure FillChar(var x;count:longint;value:byte);assembler;nostackframe;
  115. asm
  116. // less than 0?
  117. cmp r1,#0
  118. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  119. movlt pc,lr
  120. {$else}
  121. bxlt lr
  122. {$endif}
  123. mov r3,r0
  124. cmp r1,#8 // at least 8 bytes to do?
  125. blt .LFillchar2
  126. orr r2,r2,r2,lsl #8
  127. orr r2,r2,r2,lsl #16
  128. .LFillchar0:
  129. tst r3,#3 // aligned yet?
  130. strneb r2,[r3],#1
  131. subne r1,r1,#1
  132. bne .LFillchar0
  133. mov ip,r2
  134. .LFillchar1:
  135. cmp r1,#8 // 8 bytes still to do?
  136. blt .LFillchar2
  137. stmia r3!,{r2,ip}
  138. sub r1,r1,#8
  139. cmp r1,#8 // 8 bytes still to do?
  140. blt .LFillchar2
  141. stmia r3!,{r2,ip}
  142. sub r1,r1,#8
  143. cmp r1,#8 // 8 bytes still to do?
  144. blt .LFillchar2
  145. stmia r3!,{r2,ip}
  146. sub r1,r1,#8
  147. cmp r1,#8 // 8 bytes still to do?
  148. stmgeia r3!,{r2,ip}
  149. subge r1,r1,#8
  150. bge .LFillchar1
  151. .LFillchar2:
  152. movs r1,r1 // anything left?
  153. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  154. moveq pc,lr
  155. {$else}
  156. bxeq lr
  157. {$endif}
  158. rsb r1,r1,#7
  159. add pc,pc,r1,lsl #2
  160. mov r0,r0
  161. strb r2,[r3],#1
  162. strb r2,[r3],#1
  163. strb r2,[r3],#1
  164. strb r2,[r3],#1
  165. strb r2,[r3],#1
  166. strb r2,[r3],#1
  167. strb r2,[r3],#1
  168. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  169. mov pc,lr
  170. {$else}
  171. bx lr
  172. {$endif}
  173. end;
  174. {$endif FPC_SYSTEM_HAS_FILLCHAR}
  175. {$ifndef FPC_SYSTEM_HAS_MOVE}
  176. {$define FPC_SYSTEM_HAS_MOVE}
  177. procedure Move_pld(const source;var dest;count:longint);assembler;nostackframe;
  178. asm
  179. pld [r0]
  180. // count <=0 ?
  181. cmp r2,#0
  182. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  183. movle pc,lr
  184. {$else}
  185. bxle lr
  186. {$endif}
  187. // overlap?
  188. cmp r1,r0
  189. bls .Lnooverlap
  190. add r3,r0,r2
  191. cmp r3,r1
  192. bls .Lnooverlap
  193. // overlap, copy backward
  194. .Loverlapped:
  195. subs r2,r2,#1
  196. ldrb r3,[r0,r2]
  197. strb r3,[r1,r2]
  198. bne .Loverlapped
  199. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  200. mov pc,lr
  201. {$else}
  202. bx lr
  203. {$endif}
  204. .Lnooverlap:
  205. // less then 16 bytes to copy?
  206. cmp r2,#8
  207. // yes, the forget about the whole optimizations
  208. // and do a bytewise copy
  209. blt .Lbyteloop
  210. // both aligned?
  211. orr r3,r0,r1
  212. tst r3,#3
  213. bne .Lbyteloop
  214. (*
  215. // yes, then align
  216. // alignment to 4 byte boundries is enough
  217. ldrb ip,[r0],#1
  218. sub r2,r2,#1
  219. stb ip,[r1],#1
  220. tst r3,#2
  221. bne .Ldifferentaligned
  222. ldrh ip,[r0],#2
  223. sub r2,r2,#2
  224. sth ip,[r1],#2
  225. .Ldifferentaligned
  226. // qword aligned?
  227. orrs r3,r0,r1
  228. tst r3,#7
  229. bne .Ldwordloop
  230. *)
  231. pld [r0,#32]
  232. .Ldwordloop:
  233. sub r2,r2,#4
  234. ldr r3,[r0],#4
  235. // preload
  236. pld [r0,#64]
  237. cmp r2,#4
  238. str r3,[r1],#4
  239. bcs .Ldwordloop
  240. cmp r2,#0
  241. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  242. moveq pc,lr
  243. {$else}
  244. bxeq lr
  245. {$endif}
  246. .Lbyteloop:
  247. subs r2,r2,#1
  248. ldrb r3,[r0],#1
  249. strb r3,[r1],#1
  250. bne .Lbyteloop
  251. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  252. mov pc,lr
  253. {$else}
  254. bx lr
  255. {$endif}
  256. end;
  257. procedure Move_blended(const source;var dest;count:longint);assembler;nostackframe;
  258. asm
  259. // count <=0 ?
  260. cmp r2,#0
  261. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  262. movle pc,lr
  263. {$else}
  264. bxle lr
  265. {$endif}
  266. // overlap?
  267. cmp r1,r0
  268. bls .Lnooverlap
  269. add r3,r0,r2
  270. cmp r3,r1
  271. bls .Lnooverlap
  272. // overlap, copy backward
  273. .Loverlapped:
  274. subs r2,r2,#1
  275. ldrb r3,[r0,r2]
  276. strb r3,[r1,r2]
  277. bne .Loverlapped
  278. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  279. mov pc,lr
  280. {$else}
  281. bx lr
  282. {$endif}
  283. .Lnooverlap:
  284. // less then 16 bytes to copy?
  285. cmp r2,#8
  286. // yes, the forget about the whole optimizations
  287. // and do a bytewise copy
  288. blt .Lbyteloop
  289. // both aligned?
  290. orr r3,r0,r1
  291. tst r3,#3
  292. bne .Lbyteloop
  293. (*
  294. // yes, then align
  295. // alignment to 4 byte boundries is enough
  296. ldrb ip,[r0],#1
  297. sub r2,r2,#1
  298. stb ip,[r1],#1
  299. tst r3,#2
  300. bne .Ldifferentaligned
  301. ldrh ip,[r0],#2
  302. sub r2,r2,#2
  303. sth ip,[r1],#2
  304. .Ldifferentaligned
  305. // qword aligned?
  306. orrs r3,r0,r1
  307. tst r3,#7
  308. bne .Ldwordloop
  309. *)
  310. .Ldwordloop:
  311. sub r2,r2,#4
  312. ldr r3,[r0],#4
  313. cmp r2,#4
  314. str r3,[r1],#4
  315. bcs .Ldwordloop
  316. cmp r2,#0
  317. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  318. moveq pc,lr
  319. {$else}
  320. bxeq lr
  321. {$endif}
  322. .Lbyteloop:
  323. subs r2,r2,#1
  324. ldrb r3,[r0],#1
  325. strb r3,[r1],#1
  326. bne .Lbyteloop
  327. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  328. mov pc,lr
  329. {$else}
  330. bx lr
  331. {$endif}
  332. end;
  333. const
  334. moveproc : pointer = @move_blended;
  335. procedure Move(const source;var dest;count:longint);[public, alias: 'FPC_MOVE'];assembler;nostackframe;
  336. asm
  337. ldr ip,.Lmoveproc
  338. ldr pc,[ip]
  339. .Lmoveproc:
  340. .long moveproc
  341. end;
  342. {$endif FPC_SYSTEM_HAS_MOVE}
  343. {****************************************************************************
  344. String
  345. ****************************************************************************}
  346. {$ifndef FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  347. {$define FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  348. {$ifndef FPC_STRTOSHORTSTRINGPROC}
  349. function fpc_shortstr_to_shortstr(len:longint;const sstr:shortstring):shortstring;assembler;nostackframe;[public,alias: 'FPC_SHORTSTR_TO_SHORTSTR'];compilerproc;
  350. {$else}
  351. procedure fpc_shortstr_to_shortstr(out res:shortstring;const sstr:shortstring);assembler;nostackframe;[public,alias: 'FPC_SHORTSTR_TO_SHORTSTR'];compilerproc;
  352. {$endif}
  353. {r0: __RESULT
  354. r1: len
  355. r2: sstr}
  356. asm
  357. ldrb r12,[r2],#1
  358. cmp r12,r1
  359. movgt r12,r1
  360. strb r12,[r0],#1
  361. cmp r12,#6 (* 6 seems to be the break even point. *)
  362. blt .LStartTailCopy
  363. (* Align destination on 32bits. This is the only place where unrolling
  364. really seems to help, since in the common case, sstr is aligned on
  365. 32 bits, therefore in the common case we need to copy 3 bytes to
  366. align, i.e. in the case of a loop, you wouldn't branch out early.*)
  367. rsb r3,r0,#0
  368. ands r3,r3,#3
  369. sub r12,r12,r3
  370. ldrneb r1,[r2],#1
  371. strneb r1,[r0],#1
  372. subnes r3,r3,#1
  373. ldrneb r1,[r2],#1
  374. strneb r1,[r0],#1
  375. subnes r3,r3,#1
  376. ldrneb r1,[r2],#1
  377. strneb r1,[r0],#1
  378. subnes r3,r3,#1
  379. .LDoneAlign:
  380. (* Destination should be aligned now, but source might not be aligned,
  381. if this is the case, do a byte-per-byte copy. *)
  382. tst r2,#3
  383. bne .LStartTailCopy
  384. (* Start the main copy, 32 bit at a time. *)
  385. movs r3,r12,lsr #2
  386. and r12,r12,#3
  387. beq .LStartTailCopy
  388. .LNext4bytes:
  389. (* Unrolling this loop would save a little bit of time for long strings
  390. (>20 chars), but alas, it hurts for short strings and they are the
  391. common case.*)
  392. ldrne r1,[r2],#4
  393. strne r1,[r0],#4
  394. subnes r3,r3,#1
  395. bne .LNext4bytes
  396. .LStartTailCopy:
  397. (* Do remaining bytes. *)
  398. cmp r12,#0
  399. beq .LDoneTail
  400. .LNextChar3:
  401. ldrb r1,[r2],#1
  402. strb r1,[r0],#1
  403. subs r12,r12,#1
  404. bne .LNextChar3
  405. .LDoneTail:
  406. end;
  407. procedure fpc_shortstr_assign(len:longint;sstr,dstr:pointer);assembler;nostackframe;[public,alias:'FPC_SHORTSTR_ASSIGN'];compilerproc;
  408. {r0: len
  409. r1: sstr
  410. r2: dstr}
  411. asm
  412. ldrb r12,[r1],#1
  413. cmp r12,r0
  414. movgt r12,r0
  415. strb r12,[r2],#1
  416. cmp r12,#6 (* 6 seems to be the break even point. *)
  417. blt .LStartTailCopy
  418. (* Align destination on 32bits. This is the only place where unrolling
  419. really seems to help, since in the common case, sstr is aligned on
  420. 32 bits, therefore in the common case we need to copy 3 bytes to
  421. align, i.e. in the case of a loop, you wouldn't branch out early.*)
  422. rsb r3,r2,#0
  423. ands r3,r3,#3
  424. sub r12,r12,r3
  425. ldrneb r0,[r1],#1
  426. strneb r0,[r2],#1
  427. subnes r3,r3,#1
  428. ldrneb r0,[r1],#1
  429. strneb r0,[r2],#1
  430. subnes r3,r3,#1
  431. ldrneb r0,[r1],#1
  432. strneb r0,[r2],#1
  433. subnes r3,r3,#1
  434. .LDoneAlign:
  435. (* Destination should be aligned now, but source might not be aligned,
  436. if this is the case, do a byte-per-byte copy. *)
  437. tst r1,#3
  438. bne .LStartTailCopy
  439. (* Start the main copy, 32 bit at a time. *)
  440. movs r3,r12,lsr #2
  441. and r12,r12,#3
  442. beq .LStartTailCopy
  443. .LNext4bytes:
  444. (* Unrolling this loop would save a little bit of time for long strings
  445. (>20 chars), but alas, it hurts for short strings and they are the
  446. common case.*)
  447. ldrne r0,[r1],#4
  448. strne r0,[r2],#4
  449. subnes r3,r3,#1
  450. bne .LNext4bytes
  451. .LStartTailCopy:
  452. (* Do remaining bytes. *)
  453. cmp r12,#0
  454. beq .LDoneTail
  455. .LNextChar3:
  456. ldrb r0,[r1],#1
  457. strb r0,[r2],#1
  458. subs r12,r12,#1
  459. bne .LNextChar3
  460. .LDoneTail:
  461. end;
  462. {$endif FPC_SYSTEM_HAS_FPC_SHORTSTR_ASSIGN}
  463. {$ifndef FPC_SYSTEM_HAS_FPC_PCHAR_LENGTH}
  464. {$define FPC_SYSTEM_HAS_FPC_PCHAR_LENGTH}
  465. function fpc_Pchar_length(p:Pchar):sizeint;assembler;nostackframe;[public,alias:'FPC_PCHAR_LENGTH'];compilerproc;
  466. asm
  467. cmp r0,#0
  468. mov r1,r0
  469. beq .Ldone
  470. .Lnextchar:
  471. (*Are we aligned?*)
  472. tst r1,#3
  473. bne .Ltest_unaligned (*No, do byte per byte.*)
  474. ldr r3,.L01010101
  475. .Ltest_aligned:
  476. (*Aligned, load 4 bytes at a time.*)
  477. ldr r12,[r1],#4
  478. (*Check wether r12 contains a 0 byte.*)
  479. sub r2,r12,r3
  480. mvn r12,r12
  481. and r2,r2,r12
  482. ands r2,r2,r3,lsl #7 (*r3 lsl 7 = $80808080*)
  483. beq .Ltest_aligned (*No 0 byte, repeat.*)
  484. sub r1,r1,#4
  485. .Ltest_unaligned:
  486. ldrb r12,[r1],#1
  487. cmp r12,#1 (*r12<1 same as r12=0, but result in carry flag*)
  488. bcs .Lnextchar
  489. (*Dirty trick: we need to subtract 1 extra because we have counted the
  490. terminating 0, due to the known carry flag sbc can do this.*)
  491. sbc r0,r1,r0
  492. .Ldone:
  493. {$if defined(cpuarmv3) or defined(cpuarmv4) or defined(cpuarmv5)}
  494. mov pc,lr
  495. {$else}
  496. bx lr
  497. {$endif}
  498. .L01010101:
  499. .long 0x01010101
  500. end;
  501. {$endif}
  502. var
  503. fpc_system_lock: longint; export name 'fpc_system_lock';
  504. function InterLockedDecrement (var Target: longint) : longint; assembler; nostackframe;
  505. asm
  506. {$if defined(cpuarmv6) or defined(cpuarmv7m) or defined(cpucortexm3)}
  507. .Lloop:
  508. ldrex r1, [r0]
  509. sub r1, r1, #1
  510. strex r2, r1, [r0]
  511. cmp r2, #0
  512. bne .Lloop
  513. mov r0, r1
  514. bx lr
  515. {$else}
  516. // lock
  517. ldr r3, .Lfpc_system_lock
  518. mov r1, #1
  519. .Lloop:
  520. swp r2, r1, [r3]
  521. cmp r2, #0
  522. bne .Lloop
  523. // do the job
  524. ldr r1, [r0]
  525. sub r1, r1, #1
  526. str r1, [r0]
  527. mov r0, r1
  528. // unlock and return
  529. str r2, [r3]
  530. bx lr
  531. .Lfpc_system_lock:
  532. .long fpc_system_lock
  533. {$endif}
  534. end;
  535. function InterLockedIncrement (var Target: longint) : longint; assembler; nostackframe;
  536. asm
  537. {$if defined(cpuarmv6) or defined(cpuarmv7m) or defined(cpucortexm3)}
  538. .Lloop:
  539. ldrex r1, [r0]
  540. add r1, r1, #1
  541. strex r2, r1, [r0]
  542. cmp r2, #0
  543. bne .Lloop
  544. mov r0, r1
  545. bx lr
  546. {$else}
  547. // lock
  548. ldr r3, .Lfpc_system_lock
  549. mov r1, #1
  550. .Lloop:
  551. swp r2, r1, [r3]
  552. cmp r2, #0
  553. bne .Lloop
  554. // do the job
  555. ldr r1, [r0]
  556. add r1, r1, #1
  557. str r1, [r0]
  558. mov r0, r1
  559. // unlock and return
  560. str r2, [r3]
  561. bx lr
  562. .Lfpc_system_lock:
  563. .long fpc_system_lock
  564. {$endif}
  565. end;
  566. function InterLockedExchange (var Target: longint;Source : longint) : longint; assembler; nostackframe;
  567. asm
  568. {$if defined(cpuarmv6) or defined(cpuarmv7m) or defined(cpucortexm3)}
  569. // swp is deprecated on ARMv6 and above
  570. .Lloop:
  571. ldrex r2, [r0]
  572. strex r3, r1, [r0]
  573. cmp r3, #0
  574. bne .Lloop
  575. mov r0, r2
  576. bx lr
  577. {$else}
  578. swp r1, r1, [r0]
  579. mov r0,r1
  580. {$endif}
  581. end;
  582. function InterLockedExchangeAdd (var Target: longint;Source : longint) : longint; assembler; nostackframe;
  583. asm
  584. {$if defined(cpuarmv6) or defined(cpuarmv7m) or defined(cpucortexm3)}
  585. .Lloop:
  586. ldrex r2, [r0]
  587. add r12, r1, r2
  588. strex r3, r12, [r0]
  589. cmp r3, #0
  590. bne .Lloop
  591. mov r0, r2
  592. bx lr
  593. {$else}
  594. // lock
  595. ldr r3, .Lfpc_system_lock
  596. mov r2, #1
  597. .Lloop:
  598. swp r2, r2, [r3]
  599. cmp r2, #0
  600. bne .Lloop
  601. // do the job
  602. ldr r2, [r0]
  603. add r1, r1, r2
  604. str r1, [r0]
  605. mov r0, r2
  606. // unlock and return
  607. mov r2, #0
  608. str r2, [r3]
  609. bx lr
  610. .Lfpc_system_lock:
  611. .long fpc_system_lock
  612. {$endif}
  613. end;
  614. function InterlockedCompareExchange(var Target: longint; NewValue: longint; Comperand: longint): longint; assembler; nostackframe;
  615. asm
  616. {$if defined(cpuarmv6) or defined(cpuarmv7m) or defined(cpucortexm3)}
  617. .Lloop:
  618. ldrex r3, [r0]
  619. mov r12, #0
  620. cmp r3, r2
  621. strexeq r12, r1, [r0]
  622. cmp r12, #0
  623. bne .Lloop
  624. mov r0, r3
  625. bx lr
  626. {$else}
  627. // lock
  628. ldr r12, .Lfpc_system_lock
  629. mov r3, #1
  630. .Lloop:
  631. swp r3, r3, [r12]
  632. cmp r3, #0
  633. bne .Lloop
  634. // do the job
  635. ldr r3, [r0]
  636. cmp r3, r2
  637. streq r1, [r0]
  638. mov r0, r3
  639. // unlock and return
  640. mov r3, #0
  641. str r3, [r12]
  642. bx lr
  643. .Lfpc_system_lock:
  644. .long fpc_system_lock
  645. {$endif}
  646. end;
  647. {$define FPC_SYSTEM_HAS_DECLOCKED_LONGINT}
  648. function declocked(var l: longint) : boolean; inline;
  649. begin
  650. Result:=InterLockedDecrement(l) = 0;
  651. end;
  652. {$define FPC_SYSTEM_HAS_INCLOCKED_LONGINT}
  653. procedure inclocked(var l: longint); inline;
  654. begin
  655. InterLockedIncrement(l);
  656. end;
  657. procedure fpc_cpucodeinit;
  658. begin
  659. {$ifdef FPC_SYSTEM_FPC_MOVE}
  660. cpu_has_edsp:=true;
  661. in_edsp_test:=true;
  662. asm
  663. bic r0,sp,#7
  664. ldrd r0,[r0]
  665. end;
  666. in_edsp_test:=false;
  667. if cpu_has_edsp then
  668. moveproc:=@move_pld
  669. else
  670. moveproc:=@move_blended;
  671. {$endif FPC_SYSTEM_FPC_MOVE}
  672. end;
  673. {include hand-optimized assembler division code}
  674. {$i divide.inc}