popt386.pas 105 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090
  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
  3. This unit contains the peephole optimizer.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. ****************************************************************************
  16. }
  17. unit popt386;
  18. {$i fpcdefs.inc}
  19. interface
  20. uses Aasmbase,aasmtai,aasmdata,aasmcpu,verbose;
  21. procedure PrePeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  22. procedure PeepHoleOptPass1(asml: TAsmList; BlockStart, BlockEnd: tai);
  23. procedure PeepHoleOptPass2(asml: TAsmList; BlockStart, BlockEnd: tai);
  24. procedure PostPeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  25. implementation
  26. uses
  27. globtype,systems,
  28. globals,cgbase,procinfo,
  29. symsym,
  30. {$ifdef finaldestdebug}
  31. cobjects,
  32. {$endif finaldestdebug}
  33. cpuinfo,cpubase,cgutils,daopt386;
  34. function RegUsedAfterInstruction(reg: Tregister; p: tai; var UsedRegs: TRegSet): Boolean;
  35. var
  36. supreg: tsuperregister;
  37. begin
  38. supreg := getsupreg(reg);
  39. UpdateUsedRegs(UsedRegs, tai(p.Next));
  40. RegUsedAfterInstruction :=
  41. (supreg in UsedRegs) and
  42. (not(getNextInstruction(p,p)) or
  43. not(regLoadedWithNewValue(supreg,false,p)));
  44. end;
  45. function doFpuLoadStoreOpt(asmL: TAsmList; var p: tai): boolean;
  46. { returns true if a "continue" should be done after this optimization }
  47. var hp1, hp2: tai;
  48. begin
  49. doFpuLoadStoreOpt := false;
  50. if (taicpu(p).oper[0]^.typ = top_ref) and
  51. getNextInstruction(p, hp1) and
  52. (hp1.typ = ait_instruction) and
  53. (((taicpu(hp1).opcode = A_FLD) and
  54. (taicpu(p).opcode = A_FSTP)) or
  55. ((taicpu(p).opcode = A_FISTP) and
  56. (taicpu(hp1).opcode = A_FILD))) and
  57. (taicpu(hp1).oper[0]^.typ = top_ref) and
  58. (taicpu(hp1).opsize = taicpu(p).opsize) and
  59. refsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  60. begin
  61. { replacing fstp f;fld f by fst f is only valid for extended because of rounding }
  62. if (taicpu(p).opsize=S_FX) and
  63. getNextInstruction(hp1, hp2) and
  64. (hp2.typ = ait_instruction) and
  65. ((taicpu(hp2).opcode = A_LEAVE) or
  66. (taicpu(hp2).opcode = A_RET)) and
  67. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  68. not(assigned(current_procinfo.procdef.funcretsym) and
  69. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  70. (taicpu(p).oper[0]^.ref^.index = NR_NO) then
  71. begin
  72. asml.remove(p);
  73. asml.remove(hp1);
  74. p.free;
  75. hp1.free;
  76. p := hp2;
  77. removeLastDeallocForFuncRes(asmL, p);
  78. doFPULoadStoreOpt := true;
  79. end
  80. { can't be done because the store operation rounds
  81. else
  82. { fst can't store an extended value! }
  83. if (taicpu(p).opsize <> S_FX) and
  84. (taicpu(p).opsize <> S_IQ) then
  85. begin
  86. if (taicpu(p).opcode = A_FSTP) then
  87. taicpu(p).opcode := A_FST
  88. else taicpu(p).opcode := A_FIST;
  89. asml.remove(hp1);
  90. hp1.free;
  91. end
  92. }
  93. end;
  94. end;
  95. procedure PrePeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  96. var
  97. p,hp1: tai;
  98. l: aint;
  99. tmpRef: treference;
  100. begin
  101. p := BlockStart;
  102. while (p <> BlockEnd) Do
  103. begin
  104. case p.Typ Of
  105. Ait_Instruction:
  106. begin
  107. case taicpu(p).opcode Of
  108. A_IMUL:
  109. {changes certain "imul const, %reg"'s to lea sequences}
  110. begin
  111. if (taicpu(p).oper[0]^.typ = Top_Const) and
  112. (taicpu(p).oper[1]^.typ = Top_Reg) and
  113. (taicpu(p).opsize = S_L) then
  114. if (taicpu(p).oper[0]^.val = 1) then
  115. if (taicpu(p).ops = 2) then
  116. {remove "imul $1, reg"}
  117. begin
  118. hp1 := tai(p.Next);
  119. asml.remove(p);
  120. p.free;
  121. p := hp1;
  122. continue;
  123. end
  124. else
  125. {change "imul $1, reg1, reg2" to "mov reg1, reg2"}
  126. begin
  127. hp1 := taicpu.Op_Reg_Reg(A_MOV, S_L, taicpu(p).oper[1]^.reg,taicpu(p).oper[2]^.reg);
  128. InsertLLItem(asml, p.previous, p.next, hp1);
  129. p.free;
  130. p := hp1;
  131. end
  132. else if
  133. ((taicpu(p).ops <= 2) or
  134. (taicpu(p).oper[2]^.typ = Top_Reg)) and
  135. (current_settings.optimizecputype < cpu_Pentium2) and
  136. (taicpu(p).oper[0]^.val <= 12) and
  137. not(cs_opt_size in current_settings.optimizerswitches) and
  138. (not(GetNextInstruction(p, hp1)) or
  139. {GetNextInstruction(p, hp1) and}
  140. not((tai(hp1).typ = ait_instruction) and
  141. ((taicpu(hp1).opcode=A_Jcc) and
  142. (taicpu(hp1).condition in [C_O,C_NO])))) then
  143. begin
  144. reference_reset(tmpref);
  145. case taicpu(p).oper[0]^.val Of
  146. 3: begin
  147. {imul 3, reg1, reg2 to
  148. lea (reg1,reg1,2), reg2
  149. imul 3, reg1 to
  150. lea (reg1,reg1,2), reg1}
  151. TmpRef.base := taicpu(p).oper[1]^.reg;
  152. TmpRef.index := taicpu(p).oper[1]^.reg;
  153. TmpRef.ScaleFactor := 2;
  154. if (taicpu(p).ops = 2) then
  155. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  156. else
  157. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  158. InsertLLItem(asml,p.previous, p.next, hp1);
  159. p.free;
  160. p := hp1;
  161. end;
  162. 5: begin
  163. {imul 5, reg1, reg2 to
  164. lea (reg1,reg1,4), reg2
  165. imul 5, reg1 to
  166. lea (reg1,reg1,4), reg1}
  167. TmpRef.base := taicpu(p).oper[1]^.reg;
  168. TmpRef.index := taicpu(p).oper[1]^.reg;
  169. TmpRef.ScaleFactor := 4;
  170. if (taicpu(p).ops = 2) then
  171. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  172. else
  173. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  174. InsertLLItem(asml,p.previous, p.next, hp1);
  175. p.free;
  176. p := hp1;
  177. end;
  178. 6: begin
  179. {imul 6, reg1, reg2 to
  180. lea (,reg1,2), reg2
  181. lea (reg2,reg1,4), reg2
  182. imul 6, reg1 to
  183. lea (reg1,reg1,2), reg1
  184. add reg1, reg1}
  185. if (current_settings.optimizecputype <= cpu_386) then
  186. begin
  187. TmpRef.index := taicpu(p).oper[1]^.reg;
  188. if (taicpu(p).ops = 3) then
  189. begin
  190. TmpRef.base := taicpu(p).oper[2]^.reg;
  191. TmpRef.ScaleFactor := 4;
  192. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  193. end
  194. else
  195. begin
  196. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  197. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  198. end;
  199. InsertLLItem(asml,p, p.next, hp1);
  200. reference_reset(tmpref);
  201. TmpRef.index := taicpu(p).oper[1]^.reg;
  202. TmpRef.ScaleFactor := 2;
  203. if (taicpu(p).ops = 3) then
  204. begin
  205. TmpRef.base := NR_NO;
  206. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  207. taicpu(p).oper[2]^.reg);
  208. end
  209. else
  210. begin
  211. TmpRef.base := taicpu(p).oper[1]^.reg;
  212. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  213. end;
  214. InsertLLItem(asml,p.previous, p.next, hp1);
  215. p.free;
  216. p := tai(hp1.next);
  217. end
  218. end;
  219. 9: begin
  220. {imul 9, reg1, reg2 to
  221. lea (reg1,reg1,8), reg2
  222. imul 9, reg1 to
  223. lea (reg1,reg1,8), reg1}
  224. TmpRef.base := taicpu(p).oper[1]^.reg;
  225. TmpRef.index := taicpu(p).oper[1]^.reg;
  226. TmpRef.ScaleFactor := 8;
  227. if (taicpu(p).ops = 2) then
  228. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg)
  229. else
  230. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  231. InsertLLItem(asml,p.previous, p.next, hp1);
  232. p.free;
  233. p := hp1;
  234. end;
  235. 10: begin
  236. {imul 10, reg1, reg2 to
  237. lea (reg1,reg1,4), reg2
  238. add reg2, reg2
  239. imul 10, reg1 to
  240. lea (reg1,reg1,4), reg1
  241. add reg1, reg1}
  242. if (current_settings.optimizecputype <= cpu_386) then
  243. begin
  244. if (taicpu(p).ops = 3) then
  245. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  246. taicpu(p).oper[2]^.reg,taicpu(p).oper[2]^.reg)
  247. else
  248. hp1 := taicpu.op_reg_reg(A_ADD, S_L,
  249. taicpu(p).oper[1]^.reg,taicpu(p).oper[1]^.reg);
  250. InsertLLItem(asml,p, p.next, hp1);
  251. TmpRef.base := taicpu(p).oper[1]^.reg;
  252. TmpRef.index := taicpu(p).oper[1]^.reg;
  253. TmpRef.ScaleFactor := 4;
  254. if (taicpu(p).ops = 3) then
  255. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg)
  256. else
  257. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  258. InsertLLItem(asml,p.previous, p.next, hp1);
  259. p.free;
  260. p := tai(hp1.next);
  261. end
  262. end;
  263. 12: begin
  264. {imul 12, reg1, reg2 to
  265. lea (,reg1,4), reg2
  266. lea (,reg1,8) reg2
  267. imul 12, reg1 to
  268. lea (reg1,reg1,2), reg1
  269. lea (,reg1,4), reg1}
  270. if (current_settings.optimizecputype <= cpu_386)
  271. then
  272. begin
  273. TmpRef.index := taicpu(p).oper[1]^.reg;
  274. if (taicpu(p).ops = 3) then
  275. begin
  276. TmpRef.base := taicpu(p).oper[2]^.reg;
  277. TmpRef.ScaleFactor := 8;
  278. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  279. end
  280. else
  281. begin
  282. TmpRef.base := NR_NO;
  283. TmpRef.ScaleFactor := 4;
  284. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  285. end;
  286. InsertLLItem(asml,p, p.next, hp1);
  287. reference_reset(tmpref);
  288. TmpRef.index := taicpu(p).oper[1]^.reg;
  289. if (taicpu(p).ops = 3) then
  290. begin
  291. TmpRef.base := NR_NO;
  292. TmpRef.ScaleFactor := 4;
  293. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[2]^.reg);
  294. end
  295. else
  296. begin
  297. TmpRef.base := taicpu(p).oper[1]^.reg;
  298. TmpRef.ScaleFactor := 2;
  299. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef, taicpu(p).oper[1]^.reg);
  300. end;
  301. InsertLLItem(asml,p.previous, p.next, hp1);
  302. p.free;
  303. p := tai(hp1.next);
  304. end
  305. end
  306. end;
  307. end;
  308. end;
  309. A_SAR, A_SHR:
  310. {changes the code sequence
  311. shr/sar const1, x
  312. shl const2, x
  313. to either "sar/and", "shl/and" or just "and" depending on const1 and const2}
  314. begin
  315. if GetNextInstruction(p, hp1) and
  316. (tai(hp1).typ = ait_instruction) and
  317. (taicpu(hp1).opcode = A_SHL) and
  318. (taicpu(p).oper[0]^.typ = top_const) and
  319. (taicpu(hp1).oper[0]^.typ = top_const) and
  320. (taicpu(hp1).opsize = taicpu(p).opsize) and
  321. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[1]^.typ) and
  322. OpsEqual(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^) then
  323. if (taicpu(p).oper[0]^.val > taicpu(hp1).oper[0]^.val) and
  324. not(cs_opt_size in current_settings.optimizerswitches) then
  325. { shr/sar const1, %reg
  326. shl const2, %reg
  327. with const1 > const2 }
  328. begin
  329. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  330. taicpu(hp1).opcode := A_AND;
  331. l := (1 shl (taicpu(hp1).oper[0]^.val)) - 1;
  332. case taicpu(p).opsize Of
  333. S_L: taicpu(hp1).loadConst(0,l Xor aint($ffffffff));
  334. S_B: taicpu(hp1).loadConst(0,l Xor $ff);
  335. S_W: taicpu(hp1).loadConst(0,l Xor $ffff);
  336. end;
  337. end
  338. else if (taicpu(p).oper[0]^.val<taicpu(hp1).oper[0]^.val) and
  339. not(cs_opt_size in current_settings.optimizerswitches) then
  340. { shr/sar const1, %reg
  341. shl const2, %reg
  342. with const1 < const2 }
  343. begin
  344. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val-taicpu(p).oper[0]^.val);
  345. taicpu(p).opcode := A_AND;
  346. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  347. case taicpu(p).opsize Of
  348. S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
  349. S_B: taicpu(p).loadConst(0,l Xor $ff);
  350. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  351. end;
  352. end
  353. else
  354. { shr/sar const1, %reg
  355. shl const2, %reg
  356. with const1 = const2 }
  357. if (taicpu(p).oper[0]^.val = taicpu(hp1).oper[0]^.val) then
  358. begin
  359. taicpu(p).opcode := A_AND;
  360. l := (1 shl (taicpu(p).oper[0]^.val))-1;
  361. case taicpu(p).opsize Of
  362. S_B: taicpu(p).loadConst(0,l Xor $ff);
  363. S_W: taicpu(p).loadConst(0,l Xor $ffff);
  364. S_L: taicpu(p).loadConst(0,l Xor aint($ffffffff));
  365. end;
  366. asml.remove(hp1);
  367. hp1.free;
  368. end;
  369. end;
  370. A_XOR:
  371. if (taicpu(p).oper[0]^.typ = top_reg) and
  372. (taicpu(p).oper[1]^.typ = top_reg) and
  373. (taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  374. { temporarily change this to 'mov reg,0' to make it easier }
  375. { for the CSE. Will be changed back in pass 2 }
  376. begin
  377. taicpu(p).opcode := A_MOV;
  378. taicpu(p).loadConst(0,0);
  379. end;
  380. end;
  381. end;
  382. end;
  383. p := tai(p.next)
  384. end;
  385. end;
  386. procedure PeepHoleOptPass1(Asml: TAsmList; BlockStart, BlockEnd: tai);
  387. {First pass of peepholeoptimizations}
  388. var
  389. l : longint;
  390. p,hp1,hp2 : tai;
  391. hp3,hp4: tai;
  392. v:aint;
  393. TmpRef: TReference;
  394. UsedRegs, TmpUsedRegs: TRegSet;
  395. TmpBool1, TmpBool2: Boolean;
  396. function SkipLabels(hp: tai; var hp2: tai): boolean;
  397. {skips all labels and returns the next "real" instruction}
  398. begin
  399. while assigned(hp.next) and
  400. (tai(hp.next).typ in SkipInstr + [ait_label,ait_align]) Do
  401. hp := tai(hp.next);
  402. if assigned(hp.next) then
  403. begin
  404. SkipLabels := True;
  405. hp2 := tai(hp.next)
  406. end
  407. else
  408. begin
  409. hp2 := hp;
  410. SkipLabels := False
  411. end;
  412. end;
  413. function GetFinalDestination(asml: TAsmList; hp: taicpu; level: longint): boolean;
  414. {traces sucessive jumps to their final destination and sets it, e.g.
  415. je l1 je l3
  416. <code> <code>
  417. l1: becomes l1:
  418. je l2 je l3
  419. <code> <code>
  420. l2: l2:
  421. jmp l3 jmp l3
  422. the level parameter denotes how deeep we have already followed the jump,
  423. to avoid endless loops with constructs such as "l5: ; jmp l5" }
  424. var p1, p2: tai;
  425. l: tasmlabel;
  426. function FindAnyLabel(hp: tai; var l: tasmlabel): Boolean;
  427. begin
  428. FindAnyLabel := false;
  429. while assigned(hp.next) and
  430. (tai(hp.next).typ in (SkipInstr+[ait_align])) Do
  431. hp := tai(hp.next);
  432. if assigned(hp.next) and
  433. (tai(hp.next).typ = ait_label) then
  434. begin
  435. FindAnyLabel := true;
  436. l := tai_label(hp.next).labsym;
  437. end
  438. end;
  439. begin
  440. GetfinalDestination := false;
  441. if level > 20 then
  442. exit;
  443. p1 := dfa.getlabelwithsym(tasmlabel(hp.oper[0]^.ref^.symbol));
  444. if assigned(p1) then
  445. begin
  446. SkipLabels(p1,p1);
  447. if (tai(p1).typ = ait_instruction) and
  448. (taicpu(p1).is_jmp) then
  449. if { the next instruction after the label where the jump hp arrives}
  450. { is unconditional or of the same type as hp, so continue }
  451. (taicpu(p1).condition in [C_None,hp.condition]) or
  452. { the next instruction after the label where the jump hp arrives}
  453. { is the opposite of hp (so this one is never taken), but after }
  454. { that one there is a branch that will be taken, so perform a }
  455. { little hack: set p1 equal to this instruction (that's what the}
  456. { last SkipLabels is for, only works with short bool evaluation)}
  457. ((taicpu(p1).condition = inverse_cond(hp.condition)) and
  458. SkipLabels(p1,p2) and
  459. (p2.typ = ait_instruction) and
  460. (taicpu(p2).is_jmp) and
  461. (taicpu(p2).condition in [C_None,hp.condition]) and
  462. SkipLabels(p1,p1)) then
  463. begin
  464. { quick check for loops of the form "l5: ; jmp l5 }
  465. if (tasmlabel(taicpu(p1).oper[0]^.ref^.symbol).labelnr =
  466. tasmlabel(hp.oper[0]^.ref^.symbol).labelnr) then
  467. exit;
  468. if not GetFinalDestination(asml, taicpu(p1),succ(level)) then
  469. exit;
  470. tasmlabel(hp.oper[0]^.ref^.symbol).decrefs;
  471. hp.oper[0]^.ref^.symbol:=taicpu(p1).oper[0]^.ref^.symbol;
  472. tasmlabel(hp.oper[0]^.ref^.symbol).increfs;
  473. end
  474. else
  475. if (taicpu(p1).condition = inverse_cond(hp.condition)) then
  476. if not FindAnyLabel(p1,l) then
  477. begin
  478. {$ifdef finaldestdebug}
  479. insertllitem(asml,p1,p1.next,tai_comment.Create(
  480. strpnew('previous label inserted'))));
  481. {$endif finaldestdebug}
  482. current_asmdata.getjumplabel(l);
  483. insertllitem(asml,p1,p1.next,tai_label.Create(l));
  484. tasmlabel(taicpu(hp).oper[0]^.ref^.symbol).decrefs;
  485. hp.oper[0]^.ref^.symbol := l;
  486. l.increfs;
  487. { this won't work, since the new label isn't in the labeltable }
  488. { so it will fail the rangecheck. Labeltable should become a }
  489. { hashtable to support this: }
  490. { GetFinalDestination(asml, hp); }
  491. end
  492. else
  493. begin
  494. {$ifdef finaldestdebug}
  495. insertllitem(asml,p1,p1.next,tai_comment.Create(
  496. strpnew('next label reused'))));
  497. {$endif finaldestdebug}
  498. l.increfs;
  499. hp.oper[0]^.ref^.symbol := l;
  500. if not GetFinalDestination(asml, hp,succ(level)) then
  501. exit;
  502. end;
  503. end;
  504. GetFinalDestination := true;
  505. end;
  506. function DoSubAddOpt(var p: tai): Boolean;
  507. begin
  508. DoSubAddOpt := False;
  509. if GetLastInstruction(p, hp1) and
  510. (hp1.typ = ait_instruction) and
  511. (taicpu(hp1).opsize = taicpu(p).opsize) then
  512. case taicpu(hp1).opcode Of
  513. A_DEC:
  514. if (taicpu(hp1).oper[0]^.typ = top_reg) and
  515. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  516. begin
  517. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+1);
  518. asml.remove(hp1);
  519. hp1.free;
  520. end;
  521. A_SUB:
  522. if (taicpu(hp1).oper[0]^.typ = top_const) and
  523. (taicpu(hp1).oper[1]^.typ = top_reg) and
  524. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  525. begin
  526. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val+taicpu(hp1).oper[0]^.val);
  527. asml.remove(hp1);
  528. hp1.free;
  529. end;
  530. A_ADD:
  531. if (taicpu(hp1).oper[0]^.typ = top_const) and
  532. (taicpu(hp1).oper[1]^.typ = top_reg) and
  533. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  534. begin
  535. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val-taicpu(hp1).oper[0]^.val);
  536. asml.remove(hp1);
  537. hp1.free;
  538. if (taicpu(p).oper[0]^.val = 0) then
  539. begin
  540. hp1 := tai(p.next);
  541. asml.remove(p);
  542. p.free;
  543. if not GetLastInstruction(hp1, p) then
  544. p := hp1;
  545. DoSubAddOpt := True;
  546. end
  547. end;
  548. end;
  549. end;
  550. begin
  551. p := BlockStart;
  552. UsedRegs := [];
  553. while (p <> BlockEnd) Do
  554. begin
  555. UpDateUsedRegs(UsedRegs, tai(p.next));
  556. case p.Typ Of
  557. ait_instruction:
  558. begin
  559. { Handle Jmp Optimizations }
  560. if taicpu(p).is_jmp then
  561. begin
  562. {the following if-block removes all code between a jmp and the next label,
  563. because it can never be executed}
  564. if (taicpu(p).opcode = A_JMP) then
  565. begin
  566. while GetNextInstruction(p, hp1) and
  567. (hp1.typ <> ait_label) do
  568. if not(hp1.typ in ([ait_label,ait_align]+skipinstr)) then
  569. begin
  570. asml.remove(hp1);
  571. hp1.free;
  572. end
  573. else break;
  574. end;
  575. { remove jumps to a label coming right after them }
  576. if GetNextInstruction(p, hp1) then
  577. begin
  578. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp1) and
  579. {$warning FIXME removing the first instruction fails}
  580. (p<>blockstart) then
  581. begin
  582. hp2:=tai(hp1.next);
  583. asml.remove(p);
  584. p.free;
  585. p:=hp2;
  586. continue;
  587. end
  588. else
  589. begin
  590. if hp1.typ = ait_label then
  591. SkipLabels(hp1,hp1);
  592. if (tai(hp1).typ=ait_instruction) and
  593. (taicpu(hp1).opcode=A_JMP) and
  594. GetNextInstruction(hp1, hp2) and
  595. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp2) then
  596. begin
  597. if taicpu(p).opcode=A_Jcc then
  598. begin
  599. taicpu(p).condition:=inverse_cond(taicpu(p).condition);
  600. tai_label(hp2).labsym.decrefs;
  601. taicpu(p).oper[0]^.ref^.symbol:=taicpu(hp1).oper[0]^.ref^.symbol;
  602. { when free'ing hp1, the ref. isn't decresed, so we don't
  603. increase it (FK)
  604. taicpu(p).oper[0]^.ref^.symbol.increfs;
  605. }
  606. asml.remove(hp1);
  607. hp1.free;
  608. GetFinalDestination(asml, taicpu(p),0);
  609. end
  610. else
  611. begin
  612. GetFinalDestination(asml, taicpu(p),0);
  613. p:=tai(p.next);
  614. continue;
  615. end;
  616. end
  617. else
  618. GetFinalDestination(asml, taicpu(p),0);
  619. end;
  620. end;
  621. end
  622. else
  623. { All other optimizes }
  624. begin
  625. for l := 0 to taicpu(p).ops-1 Do
  626. if (taicpu(p).oper[l]^.typ = top_ref) then
  627. With taicpu(p).oper[l]^.ref^ Do
  628. begin
  629. if (base = NR_NO) and
  630. (index <> NR_NO) and
  631. (scalefactor in [0,1]) then
  632. begin
  633. base := index;
  634. index := NR_NO
  635. end
  636. end;
  637. case taicpu(p).opcode Of
  638. A_AND:
  639. begin
  640. if (taicpu(p).oper[0]^.typ = top_const) and
  641. (taicpu(p).oper[1]^.typ = top_reg) and
  642. GetNextInstruction(p, hp1) and
  643. (tai(hp1).typ = ait_instruction) and
  644. (taicpu(hp1).opcode = A_AND) and
  645. (taicpu(hp1).oper[0]^.typ = top_const) and
  646. (taicpu(hp1).oper[1]^.typ = top_reg) and
  647. (taicpu(p).oper[1]^.reg = taicpu(hp1).oper[1]^.reg) then
  648. {change "and const1, reg; and const2, reg" to "and (const1 and const2), reg"}
  649. begin
  650. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val and taicpu(hp1).oper[0]^.val);
  651. asml.remove(hp1);
  652. hp1.free;
  653. end
  654. else
  655. {change "and x, reg; jxx" to "test x, reg", if reg is deallocated before the
  656. jump, but only if it's a conditional jump (PFV) }
  657. if (taicpu(p).oper[1]^.typ = top_reg) and
  658. GetNextInstruction(p, hp1) and
  659. (hp1.typ = ait_instruction) and
  660. (taicpu(hp1).is_jmp) and
  661. (taicpu(hp1).opcode<>A_JMP) and
  662. not(getsupreg(taicpu(p).oper[1]^.reg) in UsedRegs) then
  663. taicpu(p).opcode := A_TEST;
  664. end;
  665. A_CMP:
  666. begin
  667. { cmp register,$8000 neg register
  668. je target --> jo target
  669. .... only if register is deallocated before jump.}
  670. case Taicpu(p).opsize of
  671. S_B: v:=$80;
  672. S_W: v:=$8000;
  673. S_L: v:=aint($80000000);
  674. end;
  675. if (taicpu(p).oper[0]^.typ=Top_const) and
  676. (taicpu(p).oper[0]^.val=v) and
  677. (Taicpu(p).oper[1]^.typ=top_reg) and
  678. GetNextInstruction(p, hp1) and
  679. (hp1.typ=ait_instruction) and
  680. (taicpu(hp1).opcode=A_Jcc) and
  681. (Taicpu(hp1).condition in [C_E,C_NE]) and
  682. not(getsupreg(Taicpu(p).oper[1]^.reg) in usedregs) then
  683. begin
  684. Taicpu(p).opcode:=A_NEG;
  685. Taicpu(p).loadoper(0,Taicpu(p).oper[1]^);
  686. Taicpu(p).clearop(1);
  687. Taicpu(p).ops:=1;
  688. if Taicpu(hp1).condition=C_E then
  689. Taicpu(hp1).condition:=C_O
  690. else
  691. Taicpu(hp1).condition:=C_NO;
  692. continue;
  693. end;
  694. {
  695. @@2: @@2:
  696. .... ....
  697. cmp operand1,0
  698. jle/jbe @@1
  699. dec operand1 --> sub operand1,1
  700. jmp @@2 jge/jae @@2
  701. @@1: @@1:
  702. ... ....}
  703. if (taicpu(p).oper[0]^.typ = top_const) and
  704. (taicpu(p).oper[1]^.typ in [top_reg,top_ref]) and
  705. (taicpu(p).oper[0]^.val = 0) and
  706. GetNextInstruction(p, hp1) and
  707. (hp1.typ = ait_instruction) and
  708. (taicpu(hp1).is_jmp) and
  709. (taicpu(hp1).opcode=A_Jcc) and
  710. (taicpu(hp1).condition in [C_LE,C_BE]) and
  711. GetNextInstruction(hp1,hp2) and
  712. (hp2.typ = ait_instruction) and
  713. (taicpu(hp2).opcode = A_DEC) and
  714. OpsEqual(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
  715. GetNextInstruction(hp2, hp3) and
  716. (hp3.typ = ait_instruction) and
  717. (taicpu(hp3).is_jmp) and
  718. (taicpu(hp3).opcode = A_JMP) and
  719. GetNextInstruction(hp3, hp4) and
  720. FindLabel(tasmlabel(taicpu(hp1).oper[0]^.ref^.symbol),hp4) then
  721. begin
  722. taicpu(hp2).Opcode := A_SUB;
  723. taicpu(hp2).loadoper(1,taicpu(hp2).oper[0]^);
  724. taicpu(hp2).loadConst(0,1);
  725. taicpu(hp2).ops:=2;
  726. taicpu(hp3).Opcode := A_Jcc;
  727. case taicpu(hp1).condition of
  728. C_LE: taicpu(hp3).condition := C_GE;
  729. C_BE: taicpu(hp3).condition := C_AE;
  730. end;
  731. asml.remove(p);
  732. asml.remove(hp1);
  733. p.free;
  734. hp1.free;
  735. p := hp2;
  736. continue;
  737. end
  738. end;
  739. A_FLD:
  740. begin
  741. if (taicpu(p).oper[0]^.typ = top_reg) and
  742. GetNextInstruction(p, hp1) and
  743. (hp1.typ = Ait_Instruction) and
  744. (taicpu(hp1).oper[0]^.typ = top_reg) and
  745. (taicpu(hp1).oper[1]^.typ = top_reg) and
  746. (taicpu(hp1).oper[0]^.reg = NR_ST) and
  747. (taicpu(hp1).oper[1]^.reg = NR_ST1) then
  748. { change to
  749. fld reg fxxx reg,st
  750. fxxxp st, st1 (hp1)
  751. Remark: non commutative operations must be reversed!
  752. }
  753. begin
  754. case taicpu(hp1).opcode Of
  755. A_FMULP,A_FADDP,
  756. A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  757. begin
  758. case taicpu(hp1).opcode Of
  759. A_FADDP: taicpu(hp1).opcode := A_FADD;
  760. A_FMULP: taicpu(hp1).opcode := A_FMUL;
  761. A_FSUBP: taicpu(hp1).opcode := A_FSUBR;
  762. A_FSUBRP: taicpu(hp1).opcode := A_FSUB;
  763. A_FDIVP: taicpu(hp1).opcode := A_FDIVR;
  764. A_FDIVRP: taicpu(hp1).opcode := A_FDIV;
  765. end;
  766. taicpu(hp1).oper[0]^.reg := taicpu(p).oper[0]^.reg;
  767. taicpu(hp1).oper[1]^.reg := NR_ST;
  768. asml.remove(p);
  769. p.free;
  770. p := hp1;
  771. continue;
  772. end;
  773. end;
  774. end
  775. else
  776. if (taicpu(p).oper[0]^.typ = top_ref) and
  777. GetNextInstruction(p, hp2) and
  778. (hp2.typ = Ait_Instruction) and
  779. (taicpu(hp2).ops = 2) and
  780. (taicpu(hp2).oper[0]^.typ = top_reg) and
  781. (taicpu(hp2).oper[1]^.typ = top_reg) and
  782. (taicpu(p).opsize in [S_FS, S_FL]) and
  783. (taicpu(hp2).oper[0]^.reg = NR_ST) and
  784. (taicpu(hp2).oper[1]^.reg = NR_ST1) then
  785. if GetLastInstruction(p, hp1) and
  786. (hp1.typ = Ait_Instruction) and
  787. ((taicpu(hp1).opcode = A_FLD) or
  788. (taicpu(hp1).opcode = A_FST)) and
  789. (taicpu(hp1).opsize = taicpu(p).opsize) and
  790. (taicpu(hp1).oper[0]^.typ = top_ref) and
  791. RefsEqual(taicpu(p).oper[0]^.ref^, taicpu(hp1).oper[0]^.ref^) then
  792. if ((taicpu(hp2).opcode = A_FMULP) or
  793. (taicpu(hp2).opcode = A_FADDP)) then
  794. { change to
  795. fld/fst mem1 (hp1) fld/fst mem1
  796. fld mem1 (p) fadd/
  797. faddp/ fmul st, st
  798. fmulp st, st1 (hp2) }
  799. begin
  800. asml.remove(p);
  801. p.free;
  802. p := hp1;
  803. if (taicpu(hp2).opcode = A_FADDP) then
  804. taicpu(hp2).opcode := A_FADD
  805. else
  806. taicpu(hp2).opcode := A_FMUL;
  807. taicpu(hp2).oper[1]^.reg := NR_ST;
  808. end
  809. else
  810. { change to
  811. fld/fst mem1 (hp1) fld/fst mem1
  812. fld mem1 (p) fld st}
  813. begin
  814. taicpu(p).changeopsize(S_FL);
  815. taicpu(p).loadreg(0,NR_ST);
  816. end
  817. else
  818. begin
  819. case taicpu(hp2).opcode Of
  820. A_FMULP,A_FADDP,A_FSUBP,A_FDIVP,A_FSUBRP,A_FDIVRP:
  821. { change to
  822. fld/fst mem1 (hp1) fld/fst mem1
  823. fld mem2 (p) fxxx mem2
  824. fxxxp st, st1 (hp2) }
  825. begin
  826. case taicpu(hp2).opcode Of
  827. A_FADDP: taicpu(p).opcode := A_FADD;
  828. A_FMULP: taicpu(p).opcode := A_FMUL;
  829. A_FSUBP: taicpu(p).opcode := A_FSUBR;
  830. A_FSUBRP: taicpu(p).opcode := A_FSUB;
  831. A_FDIVP: taicpu(p).opcode := A_FDIVR;
  832. A_FDIVRP: taicpu(p).opcode := A_FDIV;
  833. end;
  834. asml.remove(hp2);
  835. hp2.free;
  836. end
  837. end
  838. end
  839. end;
  840. A_FSTP,A_FISTP:
  841. if doFpuLoadStoreOpt(asmL,p) then
  842. continue;
  843. A_LEA:
  844. begin
  845. {removes seg register prefixes from LEA operations, as they
  846. don't do anything}
  847. taicpu(p).oper[0]^.ref^.Segment := NR_NO;
  848. {changes "lea (%reg1), %reg2" into "mov %reg1, %reg2"}
  849. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  850. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX..RS_ESP]) and
  851. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  852. (not(Assigned(taicpu(p).oper[0]^.ref^.Symbol))) then
  853. if (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  854. (taicpu(p).oper[0]^.ref^.offset = 0) then
  855. begin
  856. hp1 := taicpu.op_reg_reg(A_MOV, S_L,taicpu(p).oper[0]^.ref^.base,
  857. taicpu(p).oper[1]^.reg);
  858. InsertLLItem(asml,p.previous,p.next, hp1);
  859. p.free;
  860. p := hp1;
  861. continue;
  862. end
  863. else if (taicpu(p).oper[0]^.ref^.offset = 0) then
  864. begin
  865. hp1 := tai(p.Next);
  866. asml.remove(p);
  867. p.free;
  868. p := hp1;
  869. continue;
  870. end
  871. else
  872. with taicpu(p).oper[0]^.ref^ do
  873. if (base = taicpu(p).oper[1]^.reg) then
  874. begin
  875. l := offset;
  876. if (l=1) then
  877. begin
  878. taicpu(p).opcode := A_INC;
  879. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  880. taicpu(p).ops := 1
  881. end
  882. else if (l=-1) then
  883. begin
  884. taicpu(p).opcode := A_DEC;
  885. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  886. taicpu(p).ops := 1;
  887. end
  888. else
  889. begin
  890. taicpu(p).opcode := A_ADD;
  891. taicpu(p).loadConst(0,l);
  892. end;
  893. end;
  894. end;
  895. A_MOV:
  896. begin
  897. TmpUsedRegs := UsedRegs;
  898. if (taicpu(p).oper[1]^.typ = top_reg) and
  899. (getsupreg(taicpu(p).oper[1]^.reg) in [RS_EAX, RS_EBX, RS_ECX, RS_EDX, RS_ESI, RS_EDI]) and
  900. GetNextInstruction(p, hp1) and
  901. (tai(hp1).typ = ait_instruction) and
  902. (taicpu(hp1).opcode = A_MOV) and
  903. (taicpu(hp1).oper[0]^.typ = top_reg) and
  904. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  905. begin
  906. {we have "mov x, %treg; mov %treg, y}
  907. if not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg, hp1, TmpUsedRegs)) then
  908. {we've got "mov x, %treg; mov %treg, y; with %treg is not used after }
  909. case taicpu(p).oper[0]^.typ Of
  910. top_reg:
  911. begin
  912. { change "mov %reg, %treg; mov %treg, y"
  913. to "mov %reg, y" }
  914. taicpu(p).loadOper(1,taicpu(hp1).oper[1]^);
  915. asml.remove(hp1);
  916. hp1.free;
  917. continue;
  918. end;
  919. top_ref:
  920. if (taicpu(hp1).oper[1]^.typ = top_reg) then
  921. begin
  922. { change "mov mem, %treg; mov %treg, %reg"
  923. to "mov mem, %reg" }
  924. taicpu(p).loadoper(1,taicpu(hp1).oper[1]^);
  925. asml.remove(hp1);
  926. hp1.free;
  927. continue;
  928. end;
  929. end
  930. end
  931. else
  932. {Change "mov %reg1, %reg2; xxx %reg2, ???" to
  933. "mov %reg1, %reg2; xxx %reg1, ???" to avoid a write/read
  934. penalty}
  935. if (taicpu(p).oper[0]^.typ = top_reg) and
  936. (taicpu(p).oper[1]^.typ = top_reg) and
  937. GetNextInstruction(p,hp1) and
  938. (tai(hp1).typ = ait_instruction) and
  939. (taicpu(hp1).ops >= 1) and
  940. (taicpu(hp1).oper[0]^.typ = top_reg) and
  941. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
  942. {we have "mov %reg1, %reg2; XXX %reg2, ???"}
  943. begin
  944. if ((taicpu(hp1).opcode = A_OR) or
  945. (taicpu(hp1).opcode = A_TEST)) and
  946. (taicpu(hp1).oper[1]^.typ = top_reg) and
  947. (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) then
  948. {we have "mov %reg1, %reg2; test/or %reg2, %reg2"}
  949. begin
  950. TmpUsedRegs := UsedRegs;
  951. { reg1 will be used after the first instruction, }
  952. { so update the allocation info }
  953. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  954. if GetNextInstruction(hp1, hp2) and
  955. (hp2.typ = ait_instruction) and
  956. taicpu(hp2).is_jmp and
  957. not(RegUsedAfterInstruction(taicpu(hp1).oper[0]^.reg, hp1, TmpUsedRegs)) then
  958. { change "mov %reg1, %reg2; test/or %reg2, %reg2; jxx" to
  959. "test %reg1, %reg1; jxx" }
  960. begin
  961. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  962. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  963. asml.remove(p);
  964. p.free;
  965. p := hp1;
  966. continue
  967. end
  968. else
  969. {change "mov %reg1, %reg2; test/or %reg2, %reg2" to
  970. "mov %reg1, %reg2; test/or %reg1, %reg1"}
  971. begin
  972. taicpu(hp1).loadoper(0,taicpu(p).oper[0]^);
  973. taicpu(hp1).loadoper(1,taicpu(p).oper[0]^);
  974. end;
  975. end
  976. { else
  977. if (taicpu(p.next)^.opcode
  978. in [A_PUSH, A_OR, A_XOR, A_AND, A_TEST])}
  979. {change "mov %reg1, %reg2; push/or/xor/... %reg2, ???" to
  980. "mov %reg1, %reg2; push/or/xor/... %reg1, ???"}
  981. end
  982. else
  983. {leave out the mov from "mov reg, x(%frame_pointer); leave/ret" (with
  984. x >= RetOffset) as it doesn't do anything (it writes either to a
  985. parameter or to the temporary storage room for the function
  986. result)}
  987. if GetNextInstruction(p, hp1) and
  988. (tai(hp1).typ = ait_instruction) then
  989. if ((taicpu(hp1).opcode = A_LEAVE) or
  990. (taicpu(hp1).opcode = A_RET)) and
  991. (taicpu(p).oper[1]^.typ = top_ref) and
  992. (taicpu(p).oper[1]^.ref^.base = current_procinfo.FramePointer) and
  993. not(assigned(current_procinfo.procdef.funcretsym) and
  994. (taicpu(p).oper[1]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  995. (taicpu(p).oper[1]^.ref^.index = NR_NO) and
  996. (taicpu(p).oper[0]^.typ = top_reg) then
  997. begin
  998. asml.remove(p);
  999. p.free;
  1000. p := hp1;
  1001. RemoveLastDeallocForFuncRes(asmL,p);
  1002. end
  1003. else
  1004. if (taicpu(p).oper[0]^.typ = top_reg) and
  1005. (taicpu(p).oper[1]^.typ = top_ref) and
  1006. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1007. (taicpu(hp1).opcode = A_CMP) and
  1008. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1009. RefsEqual(taicpu(p).oper[1]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1010. {change "mov reg1, mem1; cmp x, mem1" to "mov reg, mem1; cmp x, reg1"}
  1011. begin
  1012. taicpu(hp1).loadreg(1,taicpu(p).oper[0]^.reg);
  1013. allocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1014. end;
  1015. { Next instruction is also a MOV ? }
  1016. if GetNextInstruction(p, hp1) and
  1017. (tai(hp1).typ = ait_instruction) and
  1018. (taicpu(hp1).opcode = A_MOV) and
  1019. (taicpu(hp1).opsize = taicpu(p).opsize) then
  1020. begin
  1021. if (taicpu(hp1).oper[0]^.typ = taicpu(p).oper[1]^.typ) and
  1022. (taicpu(hp1).oper[1]^.typ = taicpu(p).oper[0]^.typ) then
  1023. {mov reg1, mem1 or mov mem1, reg1
  1024. mov mem2, reg2 mov reg2, mem2}
  1025. begin
  1026. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) then
  1027. {mov reg1, mem1 or mov mem1, reg1
  1028. mov mem2, reg1 mov reg2, mem1}
  1029. begin
  1030. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[1]^) then
  1031. { Removes the second statement from
  1032. mov reg1, mem1/reg2
  1033. mov mem1/reg2, reg1 }
  1034. begin
  1035. if (taicpu(p).oper[0]^.typ = top_reg) then
  1036. AllocRegBetween(asmL,taicpu(p).oper[0]^.reg,p,hp1,usedregs);
  1037. asml.remove(hp1);
  1038. hp1.free;
  1039. end
  1040. else
  1041. begin
  1042. TmpUsedRegs := UsedRegs;
  1043. UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
  1044. if (taicpu(p).oper[1]^.typ = top_ref) and
  1045. { mov reg1, mem1
  1046. mov mem2, reg1 }
  1047. (taicpu(hp1).oper[0]^.ref^.refaddr = addr_no) and
  1048. GetNextInstruction(hp1, hp2) and
  1049. (hp2.typ = ait_instruction) and
  1050. (taicpu(hp2).opcode = A_CMP) and
  1051. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1052. (taicpu(hp2).oper[0]^.typ = TOp_Ref) and
  1053. (taicpu(hp2).oper[1]^.typ = TOp_Reg) and
  1054. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(p).oper[1]^.ref^) and
  1055. (taicpu(hp2).oper[1]^.reg= taicpu(p).oper[0]^.reg) and
  1056. not(RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs)) then
  1057. { change to
  1058. mov reg1, mem1 mov reg1, mem1
  1059. mov mem2, reg1 cmp reg1, mem2
  1060. cmp mem1, reg1 }
  1061. begin
  1062. asml.remove(hp2);
  1063. hp2.free;
  1064. taicpu(hp1).opcode := A_CMP;
  1065. taicpu(hp1).loadref(1,taicpu(hp1).oper[0]^.ref^);
  1066. taicpu(hp1).loadreg(0,taicpu(p).oper[0]^.reg);
  1067. end;
  1068. end;
  1069. end
  1070. else
  1071. begin
  1072. tmpUsedRegs := UsedRegs;
  1073. if GetNextInstruction(hp1, hp2) and
  1074. (taicpu(p).oper[0]^.typ = top_ref) and
  1075. (taicpu(p).oper[1]^.typ = top_reg) and
  1076. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1077. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  1078. (taicpu(hp1).oper[1]^.typ = top_ref) and
  1079. (tai(hp2).typ = ait_instruction) and
  1080. (taicpu(hp2).opcode = A_MOV) and
  1081. (taicpu(hp2).opsize = taicpu(p).opsize) and
  1082. (taicpu(hp2).oper[1]^.typ = top_reg) and
  1083. (taicpu(hp2).oper[0]^.typ = top_ref) and
  1084. RefsEqual(taicpu(hp2).oper[0]^.ref^, taicpu(hp1).oper[1]^.ref^) then
  1085. if not regInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^) and
  1086. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,hp1,tmpUsedRegs)) then
  1087. { mov mem1, %reg1
  1088. mov %reg1, mem2
  1089. mov mem2, reg2
  1090. to:
  1091. mov mem1, reg2
  1092. mov reg2, mem2}
  1093. begin
  1094. AllocRegBetween(asmL,taicpu(hp2).oper[1]^.reg,p,hp2,usedregs);
  1095. taicpu(p).loadoper(1,taicpu(hp2).oper[1]^);
  1096. taicpu(hp1).loadoper(0,taicpu(hp2).oper[1]^);
  1097. asml.remove(hp2);
  1098. hp2.free;
  1099. end
  1100. else
  1101. if (taicpu(p).oper[1]^.reg <> taicpu(hp2).oper[1]^.reg) and
  1102. not(RegInRef(getsupreg(taicpu(p).oper[1]^.reg),taicpu(p).oper[0]^.ref^)) and
  1103. not(RegInRef(getsupreg(taicpu(hp2).oper[1]^.reg),taicpu(hp2).oper[0]^.ref^)) then
  1104. { mov mem1, reg1 mov mem1, reg1
  1105. mov reg1, mem2 mov reg1, mem2
  1106. mov mem2, reg2 mov mem2, reg1
  1107. to: to:
  1108. mov mem1, reg1 mov mem1, reg1
  1109. mov mem1, reg2 mov reg1, mem2
  1110. mov reg1, mem2
  1111. or (if mem1 depends on reg1
  1112. and/or if mem2 depends on reg2)
  1113. to:
  1114. mov mem1, reg1
  1115. mov reg1, mem2
  1116. mov reg1, reg2
  1117. }
  1118. begin
  1119. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^);
  1120. taicpu(hp1).loadReg(1,taicpu(hp2).oper[1]^.reg);
  1121. taicpu(hp2).loadRef(1,taicpu(hp2).oper[0]^.ref^);
  1122. taicpu(hp2).loadReg(0,taicpu(p).oper[1]^.reg);
  1123. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1124. if (taicpu(p).oper[0]^.ref^.base <> NR_NO) and
  1125. (getsupreg(taicpu(p).oper[0]^.ref^.base) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1126. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.base,p,hp2,usedregs);
  1127. if (taicpu(p).oper[0]^.ref^.index <> NR_NO) and
  1128. (getsupreg(taicpu(p).oper[0]^.ref^.index) in [RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI]) then
  1129. allocRegBetween(asmL,taicpu(p).oper[0]^.ref^.index,p,hp2,usedregs);
  1130. end
  1131. else
  1132. if (taicpu(hp1).Oper[0]^.reg <> taicpu(hp2).Oper[1]^.reg) then
  1133. begin
  1134. taicpu(hp2).loadReg(0,taicpu(hp1).Oper[0]^.reg);
  1135. allocRegBetween(asmL,taicpu(p).oper[1]^.reg,p,hp2,usedregs);
  1136. end
  1137. else
  1138. begin
  1139. asml.remove(hp2);
  1140. hp2.free;
  1141. end
  1142. end
  1143. end
  1144. else
  1145. (* {movl [mem1],reg1
  1146. movl [mem1],reg2
  1147. to:
  1148. movl [mem1],reg1
  1149. movl reg1,reg2 }
  1150. if (taicpu(p).oper[0]^.typ = top_ref) and
  1151. (taicpu(p).oper[1]^.typ = top_reg) and
  1152. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1153. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1154. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1155. RefsEqual(TReference(taicpu(p).oper[0]^^),taicpu(hp1).oper[0]^^.ref^) and
  1156. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.base) and
  1157. (taicpu(p).oper[1]^.reg<>taicpu(hp1).oper[0]^^.ref^.index) then
  1158. taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg)
  1159. else*)
  1160. { movl const1,[mem1]
  1161. movl [mem1],reg1
  1162. to:
  1163. movl const1,reg1
  1164. movl reg1,[mem1] }
  1165. if (taicpu(p).oper[0]^.typ = top_const) and
  1166. (taicpu(p).oper[1]^.typ = top_ref) and
  1167. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1168. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1169. (taicpu(p).opsize = taicpu(hp1).opsize) and
  1170. RefsEqual(taicpu(hp1).oper[0]^.ref^,taicpu(p).oper[1]^.ref^) and
  1171. not(reginref(getsupreg(taicpu(hp1).oper[1]^.reg),taicpu(hp1).oper[0]^.ref^)) then
  1172. begin
  1173. allocregbetween(asml,taicpu(hp1).oper[1]^.reg,p,hp1,usedregs);
  1174. taicpu(hp1).loadReg(0,taicpu(hp1).oper[1]^.reg);
  1175. taicpu(hp1).loadRef(1,taicpu(p).oper[1]^.ref^);
  1176. taicpu(p).loadReg(1,taicpu(hp1).oper[0]^.reg);
  1177. end
  1178. end;
  1179. end;
  1180. A_MOVZX:
  1181. begin
  1182. {removes superfluous And's after movzx's}
  1183. if (taicpu(p).oper[1]^.typ = top_reg) and
  1184. GetNextInstruction(p, hp1) and
  1185. (tai(hp1).typ = ait_instruction) and
  1186. (taicpu(hp1).opcode = A_AND) and
  1187. (taicpu(hp1).oper[0]^.typ = top_const) and
  1188. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1189. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1190. case taicpu(p).opsize Of
  1191. S_BL, S_BW:
  1192. if (taicpu(hp1).oper[0]^.val = $ff) then
  1193. begin
  1194. asml.remove(hp1);
  1195. hp1.free;
  1196. end;
  1197. S_WL:
  1198. if (taicpu(hp1).oper[0]^.val = $ffff) then
  1199. begin
  1200. asml.remove(hp1);
  1201. hp1.free;
  1202. end;
  1203. end;
  1204. {changes some movzx constructs to faster synonims (all examples
  1205. are given with eax/ax, but are also valid for other registers)}
  1206. if (taicpu(p).oper[1]^.typ = top_reg) then
  1207. if (taicpu(p).oper[0]^.typ = top_reg) then
  1208. case taicpu(p).opsize of
  1209. S_BW:
  1210. begin
  1211. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1212. not(cs_opt_size in current_settings.optimizerswitches) then
  1213. {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
  1214. begin
  1215. taicpu(p).opcode := A_AND;
  1216. taicpu(p).changeopsize(S_W);
  1217. taicpu(p).loadConst(0,$ff);
  1218. end
  1219. else if GetNextInstruction(p, hp1) and
  1220. (tai(hp1).typ = ait_instruction) and
  1221. (taicpu(hp1).opcode = A_AND) and
  1222. (taicpu(hp1).oper[0]^.typ = top_const) and
  1223. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1224. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1225. {Change "movzbw %reg1, %reg2; andw $const, %reg2"
  1226. to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
  1227. begin
  1228. taicpu(p).opcode := A_MOV;
  1229. taicpu(p).changeopsize(S_W);
  1230. setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
  1231. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1232. end;
  1233. end;
  1234. S_BL:
  1235. begin
  1236. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1237. not(cs_opt_size in current_settings.optimizerswitches) then
  1238. {Change "movzbl %al, %eax" to "andl $0x0ffh, %eax"}
  1239. begin
  1240. taicpu(p).opcode := A_AND;
  1241. taicpu(p).changeopsize(S_L);
  1242. taicpu(p).loadConst(0,$ff)
  1243. end
  1244. else if GetNextInstruction(p, hp1) and
  1245. (tai(hp1).typ = ait_instruction) and
  1246. (taicpu(hp1).opcode = A_AND) and
  1247. (taicpu(hp1).oper[0]^.typ = top_const) and
  1248. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1249. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1250. {Change "movzbl %reg1, %reg2; andl $const, %reg2"
  1251. to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
  1252. begin
  1253. taicpu(p).opcode := A_MOV;
  1254. taicpu(p).changeopsize(S_L);
  1255. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1256. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1257. end
  1258. end;
  1259. S_WL:
  1260. begin
  1261. if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
  1262. not(cs_opt_size in current_settings.optimizerswitches) then
  1263. {Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax"}
  1264. begin
  1265. taicpu(p).opcode := A_AND;
  1266. taicpu(p).changeopsize(S_L);
  1267. taicpu(p).loadConst(0,$ffff);
  1268. end
  1269. else if GetNextInstruction(p, hp1) and
  1270. (tai(hp1).typ = ait_instruction) and
  1271. (taicpu(hp1).opcode = A_AND) and
  1272. (taicpu(hp1).oper[0]^.typ = top_const) and
  1273. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1274. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1275. {Change "movzwl %reg1, %reg2; andl $const, %reg2"
  1276. to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
  1277. begin
  1278. taicpu(p).opcode := A_MOV;
  1279. taicpu(p).changeopsize(S_L);
  1280. setsubreg(taicpu(p).oper[0]^.reg,R_SUBWHOLE);
  1281. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1282. end;
  1283. end;
  1284. end
  1285. else if (taicpu(p).oper[0]^.typ = top_ref) then
  1286. begin
  1287. if GetNextInstruction(p, hp1) and
  1288. (tai(hp1).typ = ait_instruction) and
  1289. (taicpu(hp1).opcode = A_AND) and
  1290. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1291. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1292. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1293. begin
  1294. taicpu(p).opcode := A_MOV;
  1295. case taicpu(p).opsize Of
  1296. S_BL:
  1297. begin
  1298. taicpu(p).changeopsize(S_L);
  1299. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1300. end;
  1301. S_WL:
  1302. begin
  1303. taicpu(p).changeopsize(S_L);
  1304. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
  1305. end;
  1306. S_BW:
  1307. begin
  1308. taicpu(p).changeopsize(S_W);
  1309. taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
  1310. end;
  1311. end;
  1312. end;
  1313. end;
  1314. end;
  1315. (* should not be generated anymore by the current code generator
  1316. A_POP:
  1317. begin
  1318. if target_info.system=system_i386_go32v2 then
  1319. begin
  1320. { Transform a series of pop/pop/pop/push/push/push to }
  1321. { 'movl x(%esp),%reg' for go32v2 (not for the rest, }
  1322. { because I'm not sure whether they can cope with }
  1323. { 'movl x(%esp),%reg' with x > 0, I believe we had }
  1324. { such a problem when using esp as frame pointer (JM) }
  1325. if (taicpu(p).oper[0]^.typ = top_reg) then
  1326. begin
  1327. hp1 := p;
  1328. hp2 := p;
  1329. l := 0;
  1330. while getNextInstruction(hp1,hp1) and
  1331. (hp1.typ = ait_instruction) and
  1332. (taicpu(hp1).opcode = A_POP) and
  1333. (taicpu(hp1).oper[0]^.typ = top_reg) do
  1334. begin
  1335. hp2 := hp1;
  1336. inc(l,4);
  1337. end;
  1338. getLastInstruction(p,hp3);
  1339. l1 := 0;
  1340. while (hp2 <> hp3) and
  1341. assigned(hp1) and
  1342. (hp1.typ = ait_instruction) and
  1343. (taicpu(hp1).opcode = A_PUSH) and
  1344. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1345. (taicpu(hp1).oper[0]^.reg.enum = taicpu(hp2).oper[0]^.reg.enum) do
  1346. begin
  1347. { change it to a two op operation }
  1348. taicpu(hp2).oper[1]^.typ:=top_none;
  1349. taicpu(hp2).ops:=2;
  1350. taicpu(hp2).opcode := A_MOV;
  1351. taicpu(hp2).loadoper(1,taicpu(hp1).oper[0]^);
  1352. reference_reset(tmpref);
  1353. tmpRef.base.enum:=R_INTREGISTER;
  1354. tmpRef.base.number:=NR_STACK_POINTER_REG;
  1355. convert_register_to_enum(tmpref.base);
  1356. tmpRef.offset := l;
  1357. taicpu(hp2).loadRef(0,tmpRef);
  1358. hp4 := hp1;
  1359. getNextInstruction(hp1,hp1);
  1360. asml.remove(hp4);
  1361. hp4.free;
  1362. getLastInstruction(hp2,hp2);
  1363. dec(l,4);
  1364. inc(l1);
  1365. end;
  1366. if l <> -4 then
  1367. begin
  1368. inc(l,4);
  1369. for l1 := l1 downto 1 do
  1370. begin
  1371. getNextInstruction(hp2,hp2);
  1372. dec(taicpu(hp2).oper[0]^.ref^.offset,l);
  1373. end
  1374. end
  1375. end
  1376. end
  1377. else
  1378. begin
  1379. if (taicpu(p).oper[0]^.typ = top_reg) and
  1380. GetNextInstruction(p, hp1) and
  1381. (tai(hp1).typ=ait_instruction) and
  1382. (taicpu(hp1).opcode=A_PUSH) and
  1383. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1384. (taicpu(hp1).oper[0]^.reg.enum=taicpu(p).oper[0]^.reg.enum) then
  1385. begin
  1386. { change it to a two op operation }
  1387. taicpu(p).oper[1]^.typ:=top_none;
  1388. taicpu(p).ops:=2;
  1389. taicpu(p).opcode := A_MOV;
  1390. taicpu(p).loadoper(1,taicpu(p).oper[0]^);
  1391. reference_reset(tmpref);
  1392. TmpRef.base.enum := R_ESP;
  1393. taicpu(p).loadRef(0,TmpRef);
  1394. asml.remove(hp1);
  1395. hp1.free;
  1396. end;
  1397. end;
  1398. end;
  1399. *)
  1400. A_PUSH:
  1401. begin
  1402. if (taicpu(p).opsize = S_W) and
  1403. (taicpu(p).oper[0]^.typ = Top_Const) and
  1404. GetNextInstruction(p, hp1) and
  1405. (tai(hp1).typ = ait_instruction) and
  1406. (taicpu(hp1).opcode = A_PUSH) and
  1407. (taicpu(hp1).oper[0]^.typ = Top_Const) and
  1408. (taicpu(hp1).opsize = S_W) then
  1409. begin
  1410. taicpu(p).changeopsize(S_L);
  1411. taicpu(p).loadConst(0,taicpu(p).oper[0]^.val shl 16 + word(taicpu(hp1).oper[0]^.val));
  1412. asml.remove(hp1);
  1413. hp1.free;
  1414. end;
  1415. end;
  1416. A_SHL, A_SAL:
  1417. begin
  1418. if (taicpu(p).oper[0]^.typ = Top_Const) and
  1419. (taicpu(p).oper[1]^.typ = Top_Reg) and
  1420. (taicpu(p).opsize = S_L) and
  1421. (taicpu(p).oper[0]^.val <= 3) then
  1422. {Changes "shl const, %reg32; add const/reg, %reg32" to one lea statement}
  1423. begin
  1424. TmpBool1 := True; {should we check the next instruction?}
  1425. TmpBool2 := False; {have we found an add/sub which could be
  1426. integrated in the lea?}
  1427. reference_reset(tmpref);
  1428. TmpRef.index := taicpu(p).oper[1]^.reg;
  1429. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1430. while TmpBool1 and
  1431. GetNextInstruction(p, hp1) and
  1432. (tai(hp1).typ = ait_instruction) and
  1433. ((((taicpu(hp1).opcode = A_ADD) or
  1434. (taicpu(hp1).opcode = A_SUB)) and
  1435. (taicpu(hp1).oper[1]^.typ = Top_Reg) and
  1436. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg)) or
  1437. (((taicpu(hp1).opcode = A_INC) or
  1438. (taicpu(hp1).opcode = A_DEC)) and
  1439. (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1440. (taicpu(hp1).oper[0]^.reg = taicpu(p).oper[1]^.reg))) and
  1441. (not GetNextInstruction(hp1,hp2) or
  1442. not instrReadsFlags(hp2)) Do
  1443. begin
  1444. TmpBool1 := False;
  1445. if (taicpu(hp1).oper[0]^.typ = Top_Const) then
  1446. begin
  1447. TmpBool1 := True;
  1448. TmpBool2 := True;
  1449. case taicpu(hp1).opcode of
  1450. A_ADD:
  1451. inc(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1452. A_SUB:
  1453. dec(TmpRef.offset, longint(taicpu(hp1).oper[0]^.val));
  1454. end;
  1455. asml.remove(hp1);
  1456. hp1.free;
  1457. end
  1458. else
  1459. if (taicpu(hp1).oper[0]^.typ = Top_Reg) and
  1460. (((taicpu(hp1).opcode = A_ADD) and
  1461. (TmpRef.base = NR_NO)) or
  1462. (taicpu(hp1).opcode = A_INC) or
  1463. (taicpu(hp1).opcode = A_DEC)) then
  1464. begin
  1465. TmpBool1 := True;
  1466. TmpBool2 := True;
  1467. case taicpu(hp1).opcode of
  1468. A_ADD:
  1469. TmpRef.base := taicpu(hp1).oper[0]^.reg;
  1470. A_INC:
  1471. inc(TmpRef.offset);
  1472. A_DEC:
  1473. dec(TmpRef.offset);
  1474. end;
  1475. asml.remove(hp1);
  1476. hp1.free;
  1477. end;
  1478. end;
  1479. if TmpBool2 or
  1480. ((current_settings.optimizecputype < cpu_Pentium2) and
  1481. (taicpu(p).oper[0]^.val <= 3) and
  1482. not(cs_opt_size in current_settings.optimizerswitches)) then
  1483. begin
  1484. if not(TmpBool2) and
  1485. (taicpu(p).oper[0]^.val = 1) then
  1486. begin
  1487. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1488. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg)
  1489. end
  1490. else
  1491. hp1 := taicpu.op_ref_reg(A_LEA, S_L, TmpRef,
  1492. taicpu(p).oper[1]^.reg);
  1493. InsertLLItem(asml,p.previous, p.next, hp1);
  1494. p.free;
  1495. p := hp1;
  1496. end;
  1497. end
  1498. else
  1499. if (current_settings.optimizecputype < cpu_Pentium2) and
  1500. (taicpu(p).oper[0]^.typ = top_const) and
  1501. (taicpu(p).oper[1]^.typ = top_reg) then
  1502. if (taicpu(p).oper[0]^.val = 1) then
  1503. {changes "shl $1, %reg" to "add %reg, %reg", which is the same on a 386,
  1504. but faster on a 486, and Tairable in both U and V pipes on the Pentium
  1505. (unlike shl, which is only Tairable in the U pipe)}
  1506. begin
  1507. hp1 := taicpu.Op_reg_reg(A_ADD,taicpu(p).opsize,
  1508. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  1509. InsertLLItem(asml,p.previous, p.next, hp1);
  1510. p.free;
  1511. p := hp1;
  1512. end
  1513. else if (taicpu(p).opsize = S_L) and
  1514. (taicpu(p).oper[0]^.val<= 3) then
  1515. {changes "shl $2, %reg" to "lea (,%reg,4), %reg"
  1516. "shl $3, %reg" to "lea (,%reg,8), %reg}
  1517. begin
  1518. reference_reset(tmpref);
  1519. TmpRef.index := taicpu(p).oper[1]^.reg;
  1520. TmpRef.scalefactor := 1 shl taicpu(p).oper[0]^.val;
  1521. hp1 := taicpu.Op_ref_reg(A_LEA,S_L,TmpRef, taicpu(p).oper[1]^.reg);
  1522. InsertLLItem(asml,p.previous, p.next, hp1);
  1523. p.free;
  1524. p := hp1;
  1525. end
  1526. end;
  1527. A_SETcc :
  1528. { changes
  1529. setcc (funcres) setcc reg
  1530. movb (funcres), reg to leave/ret
  1531. leave/ret }
  1532. begin
  1533. if (taicpu(p).oper[0]^.typ = top_ref) and
  1534. GetNextInstruction(p, hp1) and
  1535. GetNextInstruction(hp1, hp2) and
  1536. (hp2.typ = ait_instruction) and
  1537. ((taicpu(hp2).opcode = A_LEAVE) or
  1538. (taicpu(hp2).opcode = A_RET)) and
  1539. (taicpu(p).oper[0]^.ref^.base = current_procinfo.FramePointer) and
  1540. (taicpu(p).oper[0]^.ref^.index = NR_NO) and
  1541. not(assigned(current_procinfo.procdef.funcretsym) and
  1542. (taicpu(p).oper[0]^.ref^.offset < tabstractnormalvarsym(current_procinfo.procdef.funcretsym).localloc.reference.offset)) and
  1543. (hp1.typ = ait_instruction) and
  1544. (taicpu(hp1).opcode = A_MOV) and
  1545. (taicpu(hp1).opsize = S_B) and
  1546. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1547. RefsEqual(taicpu(hp1).oper[0]^.ref^, taicpu(p).oper[0]^.ref^) then
  1548. begin
  1549. taicpu(p).loadReg(0,taicpu(hp1).oper[1]^.reg);
  1550. asml.remove(hp1);
  1551. hp1.free;
  1552. end
  1553. end;
  1554. A_SUB:
  1555. { * change "subl $2, %esp; pushw x" to "pushl x"}
  1556. { * change "sub/add const1, reg" or "dec reg" followed by
  1557. "sub const2, reg" to one "sub ..., reg" }
  1558. begin
  1559. if (taicpu(p).oper[0]^.typ = top_const) and
  1560. (taicpu(p).oper[1]^.typ = top_reg) then
  1561. if (taicpu(p).oper[0]^.val = 2) and
  1562. (taicpu(p).oper[1]^.reg = NR_ESP) and
  1563. { Don't do the sub/push optimization if the sub }
  1564. { comes from setting up the stack frame (JM) }
  1565. (not getLastInstruction(p,hp1) or
  1566. (hp1.typ <> ait_instruction) or
  1567. (taicpu(hp1).opcode <> A_MOV) or
  1568. (taicpu(hp1).oper[0]^.typ <> top_reg) or
  1569. (taicpu(hp1).oper[0]^.reg <> NR_ESP) or
  1570. (taicpu(hp1).oper[1]^.typ <> top_reg) or
  1571. (taicpu(hp1).oper[1]^.reg <> NR_EBP)) then
  1572. begin
  1573. hp1 := tai(p.next);
  1574. while Assigned(hp1) and
  1575. (tai(hp1).typ in [ait_instruction]+SkipInstr) and
  1576. not regReadByInstruction(RS_ESP,hp1) and
  1577. not regModifiedByInstruction(RS_ESP,hp1) do
  1578. hp1 := tai(hp1.next);
  1579. if Assigned(hp1) and
  1580. (tai(hp1).typ = ait_instruction) and
  1581. (taicpu(hp1).opcode = A_PUSH) and
  1582. (taicpu(hp1).opsize = S_W) then
  1583. begin
  1584. taicpu(hp1).changeopsize(S_L);
  1585. if taicpu(hp1).oper[0]^.typ=top_reg then
  1586. setsubreg(taicpu(hp1).oper[0]^.reg,R_SUBWHOLE);
  1587. hp1 := tai(p.next);
  1588. asml.remove(p);
  1589. p.free;
  1590. p := hp1;
  1591. continue
  1592. end;
  1593. if DoSubAddOpt(p) then
  1594. continue;
  1595. end
  1596. else if DoSubAddOpt(p) then
  1597. continue
  1598. end;
  1599. end;
  1600. end; { if is_jmp }
  1601. end;
  1602. end;
  1603. updateUsedRegs(UsedRegs,p);
  1604. p:=tai(p.next);
  1605. end;
  1606. end;
  1607. function isFoldableArithOp(hp1: taicpu; reg: tregister): boolean;
  1608. begin
  1609. isFoldableArithOp := False;
  1610. case hp1.opcode of
  1611. A_ADD,A_SUB,A_OR,A_XOR,A_AND,A_SHL,A_SHR,A_SAR:
  1612. isFoldableArithOp :=
  1613. ((taicpu(hp1).oper[0]^.typ = top_const) or
  1614. ((taicpu(hp1).oper[0]^.typ = top_reg) and
  1615. (taicpu(hp1).oper[0]^.reg <> reg))) and
  1616. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1617. (taicpu(hp1).oper[1]^.reg = reg);
  1618. A_INC,A_DEC:
  1619. isFoldableArithOp :=
  1620. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1621. (taicpu(hp1).oper[0]^.reg = reg);
  1622. end;
  1623. end;
  1624. procedure PeepHoleOptPass2(asml: TAsmList; BlockStart, BlockEnd: tai);
  1625. {$ifdef USECMOV}
  1626. function CanBeCMOV(p : tai) : boolean;
  1627. begin
  1628. CanBeCMOV:=assigned(p) and (p.typ=ait_instruction) and
  1629. (taicpu(p).opcode=A_MOV) and
  1630. (taicpu(p).opsize in [S_L,S_W]) and
  1631. ((taicpu(p).oper[0]^.typ = top_reg)
  1632. { we can't use cmov ref,reg because
  1633. ref could be nil and cmov still throws an exception
  1634. if ref=nil but the mov isn't done (FK)
  1635. or ((taicpu(p).oper[0]^.typ = top_ref) and
  1636. (taicpu(p).oper[0]^.ref^.refaddr = addr_no))
  1637. }
  1638. ) and
  1639. (taicpu(p).oper[1]^.typ in [top_reg]);
  1640. end;
  1641. {$endif USECMOV}
  1642. var
  1643. p,hp1,hp2: tai;
  1644. {$ifdef USECMOV}
  1645. l : longint;
  1646. condition : tasmcond;
  1647. hp3: tai;
  1648. {$endif USECMOV}
  1649. UsedRegs, TmpUsedRegs: TRegSet;
  1650. begin
  1651. p := BlockStart;
  1652. UsedRegs := [];
  1653. while (p <> BlockEnd) Do
  1654. begin
  1655. UpdateUsedRegs(UsedRegs, tai(p.next));
  1656. case p.Typ Of
  1657. Ait_Instruction:
  1658. begin
  1659. case taicpu(p).opcode Of
  1660. {$ifdef USECMOV}
  1661. A_Jcc:
  1662. if (current_settings.cputype>=cpu_Pentium2) then
  1663. begin
  1664. { check for
  1665. jCC xxx
  1666. <several movs>
  1667. xxx:
  1668. }
  1669. l:=0;
  1670. GetNextInstruction(p, hp1);
  1671. while assigned(hp1) and
  1672. CanBeCMOV(hp1) and
  1673. { stop on labels }
  1674. not(hp1.typ=ait_label) do
  1675. begin
  1676. inc(l);
  1677. GetNextInstruction(hp1,hp1);
  1678. end;
  1679. if assigned(hp1) then
  1680. begin
  1681. if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1682. begin
  1683. if (l<=4) and (l>0) then
  1684. begin
  1685. condition:=inverse_cond(taicpu(p).condition);
  1686. hp2:=p;
  1687. GetNextInstruction(p,hp1);
  1688. p:=hp1;
  1689. repeat
  1690. taicpu(hp1).opcode:=A_CMOVcc;
  1691. taicpu(hp1).condition:=condition;
  1692. GetNextInstruction(hp1,hp1);
  1693. until not(assigned(hp1)) or
  1694. not(CanBeCMOV(hp1));
  1695. { wait with removing else GetNextInstruction could
  1696. ignore the label if it was the only usage in the
  1697. jump moved away }
  1698. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1699. asml.remove(hp2);
  1700. hp2.free;
  1701. continue;
  1702. end;
  1703. end
  1704. else
  1705. begin
  1706. { check further for
  1707. jCC xxx
  1708. <several movs 1>
  1709. jmp yyy
  1710. xxx:
  1711. <several movs 2>
  1712. yyy:
  1713. }
  1714. { hp2 points to jmp yyy }
  1715. hp2:=hp1;
  1716. { skip hp1 to xxx }
  1717. GetNextInstruction(hp1, hp1);
  1718. if assigned(hp2) and
  1719. assigned(hp1) and
  1720. (l<=3) and
  1721. (hp2.typ=ait_instruction) and
  1722. (taicpu(hp2).is_jmp) and
  1723. (taicpu(hp2).condition=C_None) and
  1724. { real label and jump, no further references to the
  1725. label are allowed }
  1726. (tasmlabel(taicpu(p).oper[0]^.ref^.symbol).getrefs=2) and
  1727. FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
  1728. begin
  1729. l:=0;
  1730. { skip hp1 to <several moves 2> }
  1731. GetNextInstruction(hp1, hp1);
  1732. while assigned(hp1) and
  1733. CanBeCMOV(hp1) do
  1734. begin
  1735. inc(l);
  1736. GetNextInstruction(hp1, hp1);
  1737. end;
  1738. { hp1 points to yyy: }
  1739. if assigned(hp1) and
  1740. FindLabel(tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol),hp1) then
  1741. begin
  1742. condition:=inverse_cond(taicpu(p).condition);
  1743. GetNextInstruction(p,hp1);
  1744. hp3:=p;
  1745. p:=hp1;
  1746. repeat
  1747. taicpu(hp1).opcode:=A_CMOVcc;
  1748. taicpu(hp1).condition:=condition;
  1749. GetNextInstruction(hp1,hp1);
  1750. until not(assigned(hp1)) or
  1751. not(CanBeCMOV(hp1));
  1752. { hp2 is still at jmp yyy }
  1753. GetNextInstruction(hp2,hp1);
  1754. { hp2 is now at xxx: }
  1755. condition:=inverse_cond(condition);
  1756. GetNextInstruction(hp1,hp1);
  1757. { hp1 is now at <several movs 2> }
  1758. repeat
  1759. taicpu(hp1).opcode:=A_CMOVcc;
  1760. taicpu(hp1).condition:=condition;
  1761. GetNextInstruction(hp1,hp1);
  1762. until not(assigned(hp1)) or
  1763. not(CanBeCMOV(hp1));
  1764. {
  1765. asml.remove(hp1.next)
  1766. hp1.next.free;
  1767. asml.remove(hp1);
  1768. hp1.free;
  1769. }
  1770. { remove jCC }
  1771. tasmlabel(taicpu(hp3).oper[0]^.ref^.symbol).decrefs;
  1772. asml.remove(hp3);
  1773. hp3.free;
  1774. { remove jmp }
  1775. tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
  1776. asml.remove(hp2);
  1777. hp2.free;
  1778. continue;
  1779. end;
  1780. end;
  1781. end;
  1782. end;
  1783. end;
  1784. {$endif USECMOV}
  1785. A_FSTP,A_FISTP:
  1786. if doFpuLoadStoreOpt(asmL,p) then
  1787. continue;
  1788. A_IMUL:
  1789. begin
  1790. if (taicpu(p).ops >= 2) and
  1791. ((taicpu(p).oper[0]^.typ = top_const) or
  1792. ((taicpu(p).oper[0]^.typ = top_ref) and (taicpu(p).oper[0]^.ref^.refaddr=addr_full))) and
  1793. (taicpu(p).oper[1]^.typ = top_reg) and
  1794. ((taicpu(p).ops = 2) or
  1795. ((taicpu(p).oper[2]^.typ = top_reg) and
  1796. (taicpu(p).oper[2]^.reg = taicpu(p).oper[1]^.reg))) and
  1797. getLastInstruction(p,hp1) and
  1798. (hp1.typ = ait_instruction) and
  1799. (taicpu(hp1).opcode = A_MOV) and
  1800. (taicpu(hp1).oper[0]^.typ = top_reg) and
  1801. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1802. (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
  1803. { change "mov reg1,reg2; imul y,reg2" to "imul y,reg1,reg2" }
  1804. begin
  1805. taicpu(p).ops := 3;
  1806. taicpu(p).loadreg(1,taicpu(hp1).oper[0]^.reg);
  1807. taicpu(p).loadreg(2,taicpu(hp1).oper[1]^.reg);
  1808. asml.remove(hp1);
  1809. hp1.free;
  1810. end;
  1811. end;
  1812. A_MOV:
  1813. begin
  1814. if (taicpu(p).oper[0]^.typ = top_reg) and
  1815. (taicpu(p).oper[1]^.typ = top_reg) and
  1816. GetNextInstruction(p, hp1) and
  1817. (hp1.typ = ait_Instruction) and
  1818. ((taicpu(hp1).opcode = A_MOV) or
  1819. (taicpu(hp1).opcode = A_MOVZX) or
  1820. (taicpu(hp1).opcode = A_MOVSX)) and
  1821. (taicpu(hp1).oper[0]^.typ = top_ref) and
  1822. (taicpu(hp1).oper[1]^.typ = top_reg) and
  1823. ((taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) or
  1824. (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg)) and
  1825. (getsupreg(taicpu(hp1).oper[1]^.reg) = getsupreg(taicpu(p).oper[1]^.reg)) then
  1826. {mov reg1, reg2
  1827. mov/zx/sx (reg2, ..), reg2 to mov/zx/sx (reg1, ..), reg2}
  1828. begin
  1829. if (taicpu(hp1).oper[0]^.ref^.base = taicpu(p).oper[1]^.reg) then
  1830. taicpu(hp1).oper[0]^.ref^.base := taicpu(p).oper[0]^.reg;
  1831. if (taicpu(hp1).oper[0]^.ref^.index = taicpu(p).oper[1]^.reg) then
  1832. taicpu(hp1).oper[0]^.ref^.index := taicpu(p).oper[0]^.reg;
  1833. asml.remove(p);
  1834. p.free;
  1835. p := hp1;
  1836. continue;
  1837. end
  1838. else if (taicpu(p).oper[0]^.typ = top_ref) and
  1839. GetNextInstruction(p,hp1) and
  1840. (hp1.typ = ait_instruction) and
  1841. IsFoldableArithOp(taicpu(hp1),taicpu(p).oper[1]^.reg) and
  1842. GetNextInstruction(hp1,hp2) and
  1843. (hp2.typ = ait_instruction) and
  1844. (taicpu(hp2).opcode = A_MOV) and
  1845. (taicpu(hp2).oper[0]^.typ = top_reg) and
  1846. (taicpu(hp2).oper[0]^.reg = taicpu(p).oper[1]^.reg) and
  1847. (taicpu(hp2).oper[1]^.typ = top_ref) then
  1848. begin
  1849. TmpUsedRegs := UsedRegs;
  1850. UpdateUsedRegs(TmpUsedRegs,tai(hp1.next));
  1851. if (RefsEqual(taicpu(hp2).oper[1]^.ref^, taicpu(p).oper[0]^.ref^) and
  1852. not(RegUsedAfterInstruction(taicpu(p).oper[1]^.reg,
  1853. hp2, TmpUsedRegs))) then
  1854. { change mov (ref), reg }
  1855. { add/sub/or/... reg2/$const, reg }
  1856. { mov reg, (ref) }
  1857. { # release reg }
  1858. { to add/sub/or/... reg2/$const, (ref) }
  1859. begin
  1860. case taicpu(hp1).opcode of
  1861. A_INC,A_DEC:
  1862. taicpu(hp1).loadRef(0,taicpu(p).oper[0]^.ref^)
  1863. else
  1864. taicpu(hp1).loadRef(1,taicpu(p).oper[0]^.ref^);
  1865. end;
  1866. asml.remove(p);
  1867. asml.remove(hp2);
  1868. p.free;
  1869. hp2.free;
  1870. p := hp1
  1871. end;
  1872. end
  1873. end;
  1874. end;
  1875. end;
  1876. end;
  1877. p := tai(p.next)
  1878. end;
  1879. end;
  1880. procedure PostPeepHoleOpts(asml: TAsmList; BlockStart, BlockEnd: tai);
  1881. var
  1882. p,hp1,hp2: tai;
  1883. begin
  1884. p := BlockStart;
  1885. while (p <> BlockEnd) Do
  1886. begin
  1887. case p.Typ Of
  1888. Ait_Instruction:
  1889. begin
  1890. case taicpu(p).opcode Of
  1891. A_CALL:
  1892. if (current_settings.optimizecputype < cpu_Pentium2) and
  1893. GetNextInstruction(p, hp1) and
  1894. (hp1.typ = ait_instruction) and
  1895. (taicpu(hp1).opcode = A_JMP) and
  1896. ((taicpu(hp1).oper[0]^.typ=top_ref) and (taicpu(hp1).oper[0]^.ref^.refaddr=addr_full)) then
  1897. begin
  1898. hp2 := taicpu.Op_sym(A_PUSH,S_L,taicpu(hp1).oper[0]^.ref^.symbol);
  1899. InsertLLItem(asml, p.previous, p, hp2);
  1900. taicpu(p).opcode := A_JMP;
  1901. taicpu(p).is_jmp := true;
  1902. asml.remove(hp1);
  1903. hp1.free;
  1904. end;
  1905. A_CMP:
  1906. begin
  1907. if (taicpu(p).oper[0]^.typ = top_const) and
  1908. (taicpu(p).oper[0]^.val = 0) and
  1909. (taicpu(p).oper[1]^.typ = top_reg) then
  1910. {change "cmp $0, %reg" to "test %reg, %reg"}
  1911. begin
  1912. taicpu(p).opcode := A_TEST;
  1913. taicpu(p).loadreg(0,taicpu(p).oper[1]^.reg);
  1914. continue;
  1915. end;
  1916. end;
  1917. (*
  1918. Optimization is not safe; xor clears the carry flag.
  1919. See test/tgadint64 in the test suite.
  1920. A_MOV:
  1921. if (taicpu(p).oper[0]^.typ = Top_Const) and
  1922. (taicpu(p).oper[0]^.val = 0) and
  1923. (taicpu(p).oper[1]^.typ = Top_Reg) then
  1924. { change "mov $0, %reg" into "xor %reg, %reg" }
  1925. begin
  1926. taicpu(p).opcode := A_XOR;
  1927. taicpu(p).loadReg(0,taicpu(p).oper[1]^.reg);
  1928. end;
  1929. *)
  1930. A_MOVZX:
  1931. { if register vars are on, it's possible there is code like }
  1932. { "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx" }
  1933. { so we can't safely replace the movzx then with xor/mov, }
  1934. { since that would change the flags (JM) }
  1935. if not(cs_opt_regvar in current_settings.optimizerswitches) then
  1936. begin
  1937. if (taicpu(p).oper[1]^.typ = top_reg) then
  1938. if (taicpu(p).oper[0]^.typ = top_reg)
  1939. then
  1940. case taicpu(p).opsize of
  1941. S_BL:
  1942. begin
  1943. if IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  1944. not(cs_opt_size in current_settings.optimizerswitches) and
  1945. (current_settings.optimizecputype = cpu_Pentium) then
  1946. {Change "movzbl %reg1, %reg2" to
  1947. "xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
  1948. PentiumMMX}
  1949. begin
  1950. hp1 := taicpu.op_reg_reg(A_XOR, S_L,
  1951. taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
  1952. InsertLLItem(asml,p.previous, p, hp1);
  1953. taicpu(p).opcode := A_MOV;
  1954. taicpu(p).changeopsize(S_B);
  1955. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  1956. end;
  1957. end;
  1958. end
  1959. else if (taicpu(p).oper[0]^.typ = top_ref) and
  1960. (taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
  1961. (taicpu(p).oper[0]^.ref^.index <> taicpu(p).oper[1]^.reg) and
  1962. not(cs_opt_size in current_settings.optimizerswitches) and
  1963. IsGP32Reg(getsupreg(taicpu(p).oper[1]^.reg)) and
  1964. (current_settings.optimizecputype = cpu_Pentium) and
  1965. (taicpu(p).opsize = S_BL) then
  1966. {changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
  1967. Pentium and PentiumMMX}
  1968. begin
  1969. hp1 := taicpu.Op_reg_reg(A_XOR, S_L, taicpu(p).oper[1]^.reg,
  1970. taicpu(p).oper[1]^.reg);
  1971. taicpu(p).opcode := A_MOV;
  1972. taicpu(p).changeopsize(S_B);
  1973. setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
  1974. InsertLLItem(asml,p.previous, p, hp1);
  1975. end;
  1976. end;
  1977. A_TEST, A_OR:
  1978. {removes the line marked with (x) from the sequence
  1979. and/or/xor/add/sub/... $x, %y
  1980. test/or %y, %y (x)
  1981. j(n)z _Label
  1982. as the first instruction already adjusts the ZF}
  1983. begin
  1984. if OpsEqual(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
  1985. if GetLastInstruction(p, hp1) and
  1986. (tai(hp1).typ = ait_instruction) and
  1987. GetNextInstruction(hp1,hp2) and
  1988. (hp2.typ = ait_instruction) and
  1989. ((taicpu(hp2).opcode = A_SETcc) or
  1990. (taicpu(hp2).opcode = A_Jcc)) then
  1991. case taicpu(hp1).opcode Of
  1992. A_ADD, A_SUB, A_OR, A_XOR, A_AND{, A_SHL, A_SHR}:
  1993. begin
  1994. if OpsEqual(taicpu(hp1).oper[1]^,taicpu(p).oper[0]^) and
  1995. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  1996. { and in case of carry for A(E)/B(E)/C/NC }
  1997. ((taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) or
  1998. ((taicpu(hp1).opcode <> A_ADD) and
  1999. (taicpu(hp1).opcode <> A_SUB))) then
  2000. begin
  2001. hp1 := tai(p.next);
  2002. asml.remove(p);
  2003. p.free;
  2004. p := tai(hp1);
  2005. continue
  2006. end;
  2007. end;
  2008. A_DEC, A_INC, A_NEG:
  2009. begin
  2010. if OpsEqual(taicpu(hp1).oper[0]^,taicpu(p).oper[0]^) and
  2011. { does not work in case of overflow for G(E)/L(E)/C_O/C_NO }
  2012. { and in case of carry for A(E)/B(E)/C/NC }
  2013. (taicpu(hp2).condition in [C_Z,C_NZ,C_E,C_NE]) then
  2014. begin
  2015. case taicpu(hp1).opcode Of
  2016. A_DEC, A_INC:
  2017. {replace inc/dec with add/sub 1, because inc/dec doesn't set the carry flag}
  2018. begin
  2019. case taicpu(hp1).opcode Of
  2020. A_DEC: taicpu(hp1).opcode := A_SUB;
  2021. A_INC: taicpu(hp1).opcode := A_ADD;
  2022. end;
  2023. taicpu(hp1).loadoper(1,taicpu(hp1).oper[0]^);
  2024. taicpu(hp1).loadConst(0,1);
  2025. taicpu(hp1).ops:=2;
  2026. end
  2027. end;
  2028. hp1 := tai(p.next);
  2029. asml.remove(p);
  2030. p.free;
  2031. p := tai(hp1);
  2032. continue
  2033. end;
  2034. end
  2035. end
  2036. end;
  2037. end;
  2038. end;
  2039. end;
  2040. p := tai(p.next)
  2041. end;
  2042. end;
  2043. end.