aasmcpu.pas 79 KB

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  1. {
  2. Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
  3. Contains the abstract assembler implementation for the i386
  4. * Portions of this code was inspired by the NASM sources
  5. The Netwide Assembler is Copyright (c) 1996 Simon Tatham and
  6. Julian Hall. All rights reserved.
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. ****************************************************************************
  19. }
  20. unit aasmcpu;
  21. {$i fpcdefs.inc}
  22. interface
  23. uses
  24. globtype,globals,verbose,
  25. cpubase,
  26. cgbase,cgutils,
  27. symtype,
  28. aasmbase,aasmtai,aasmdata,aasmsym,
  29. ogbase;
  30. const
  31. { "mov reg,reg" source operand number }
  32. O_MOV_SOURCE = 0;
  33. { "mov reg,reg" destination operand number }
  34. O_MOV_DEST = 1;
  35. { Operand types }
  36. OT_NONE = $00000000;
  37. OT_BITS8 = $00000001; { size, and other attributes, of the operand }
  38. OT_BITS16 = $00000002;
  39. OT_BITS32 = $00000004;
  40. OT_BITS64 = $00000008; { FPU only }
  41. OT_BITS80 = $00000010;
  42. OT_SIZE_MASK = $0000001F; { all the size attributes }
  43. OT_NON_SIZE = longint(not OT_SIZE_MASK);
  44. OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
  45. OT_NEAR = $00000040;
  46. OT_SHORT = $00000080;
  47. OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
  48. OT_TO = $00000200; { operand is followed by a colon }
  49. { reverse effect in FADD, FSUB &c }
  50. OT_COLON = $00000400;
  51. OT_REGISTER = $00001000;
  52. OT_IMMEDIATE = $00002000;
  53. OT_IMM8 = $00002001;
  54. OT_IMM16 = $00002002;
  55. OT_IMM32 = $00002004;
  56. OT_IMM64 = $00002008;
  57. OT_IMM80 = $00002010;
  58. OT_REGMEM = $00200000; { for r/m, ie EA, operands }
  59. OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
  60. OT_REG8 = $00201001;
  61. OT_REG16 = $00201002;
  62. OT_REG32 = $00201004;
  63. OT_REG64 = $00201008;
  64. OT_XMMREG = $00201010; { Katmai registers }
  65. OT_MMXREG = $00201020; { MMX registers }
  66. OT_MEMORY = $00204000; { register number in 'basereg' }
  67. OT_MEM8 = $00204001;
  68. OT_MEM16 = $00204002;
  69. OT_MEM32 = $00204004;
  70. OT_MEM64 = $00204008;
  71. OT_MEM80 = $00204010;
  72. OT_FPUREG = $01000000; { floating point stack registers }
  73. OT_FPU0 = $01000800; { FPU stack register zero }
  74. OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
  75. { a mask for the following }
  76. OT_REG_ACCUM = $00211000; { FUNCTION_RETURN_REG: AL, AX or EAX }
  77. OT_REG_AL = $00211001; { REG_ACCUM | BITSxx }
  78. OT_REG_AX = $00211002; { ditto }
  79. OT_REG_EAX = $00211004; { and again }
  80. {$ifdef x86_64}
  81. OT_REG_RAX = $00211008;
  82. {$endif x86_64}
  83. OT_REG_COUNT = $00221000; { counter: CL, CX or ECX }
  84. OT_REG_CL = $00221001; { REG_COUNT | BITSxx }
  85. OT_REG_CX = $00221002; { ditto }
  86. OT_REG_ECX = $00221004; { another one }
  87. {$ifdef x86_64}
  88. OT_REG_RCX = $00221008;
  89. {$endif x86_64}
  90. OT_REG_DX = $00241002;
  91. OT_REG_EDX = $00241004;
  92. OT_REG_SREG = $00081002; { any segment register }
  93. OT_REG_CS = $01081002; { CS }
  94. OT_REG_DESS = $02081002; { DS, ES, SS (non-CS 86 registers) }
  95. OT_REG_FSGS = $04081002; { FS, GS (386 extended registers) }
  96. OT_REG_CDT = $00101004; { CRn, DRn and TRn }
  97. OT_REG_CREG = $08101004; { CRn }
  98. OT_REG_CR4 = $08101404; { CR4 (Pentium only) }
  99. OT_REG_DREG = $10101004; { DRn }
  100. OT_REG_TREG = $20101004; { TRn }
  101. OT_MEM_OFFS = $00604000; { special type of EA }
  102. { simple [address] offset }
  103. OT_ONENESS = $00800000; { special type of immediate operand }
  104. { so UNITY == IMMEDIATE | ONENESS }
  105. OT_UNITY = $00802000; { for shift/rotate instructions }
  106. { Size of the instruction table converted by nasmconv.pas }
  107. {$ifdef x86_64}
  108. instabentries = {$i x8664nop.inc}
  109. {$else x86_64}
  110. instabentries = {$i i386nop.inc}
  111. {$endif x86_64}
  112. maxinfolen = 11;
  113. MaxInsChanges = 3; { Max things a instruction can change }
  114. type
  115. { What an instruction can change. Needed for optimizer and spilling code.
  116. Note: The order of this enumeration is should not be changed! }
  117. TInsChange = (Ch_None,
  118. {Read from a register}
  119. Ch_REAX, Ch_RECX, Ch_REDX, Ch_REBX, Ch_RESP, Ch_REBP, Ch_RESI, Ch_REDI,
  120. {write from a register}
  121. Ch_WEAX, Ch_WECX, Ch_WEDX, Ch_WEBX, Ch_WESP, Ch_WEBP, Ch_WESI, Ch_WEDI,
  122. {read and write from/to a register}
  123. Ch_RWEAX, Ch_RWECX, Ch_RWEDX, Ch_RWEBX, Ch_RWESP, Ch_RWEBP, Ch_RWESI, Ch_RWEDI,
  124. {modify the contents of a register with the purpose of using
  125. this changed content afterwards (add/sub/..., but e.g. not rep
  126. or movsd)}
  127. Ch_MEAX, Ch_MECX, Ch_MEDX, Ch_MEBX, Ch_MESP, Ch_MEBP, Ch_MESI, Ch_MEDI,
  128. Ch_CDirFlag {clear direction flag}, Ch_SDirFlag {set dir flag},
  129. Ch_RFlags, Ch_WFlags, Ch_RWFlags, Ch_FPU,
  130. Ch_Rop1, Ch_Wop1, Ch_RWop1,Ch_Mop1,
  131. Ch_Rop2, Ch_Wop2, Ch_RWop2,Ch_Mop2,
  132. Ch_Rop3, Ch_WOp3, Ch_RWOp3,Ch_Mop3,
  133. Ch_WMemEDI,
  134. Ch_All,
  135. { x86_64 registers }
  136. Ch_RRAX, Ch_RRCX, Ch_RRDX, Ch_RRBX, Ch_RRSP, Ch_RRBP, Ch_RRSI, Ch_RRDI,
  137. Ch_WRAX, Ch_WRCX, Ch_WRDX, Ch_WRBX, Ch_WRSP, Ch_WRBP, Ch_WRSI, Ch_WRDI,
  138. Ch_RWRAX, Ch_RWRCX, Ch_RWRDX, Ch_RWRBX, Ch_RWRSP, Ch_RWRBP, Ch_RWRSI, Ch_RWRDI,
  139. Ch_MRAX, Ch_MRCX, Ch_MRDX, Ch_MRBX, Ch_MRSP, Ch_MRBP, Ch_MRSI, Ch_MRDI
  140. );
  141. TInsProp = packed record
  142. Ch : Array[1..MaxInsChanges] of TInsChange;
  143. end;
  144. const
  145. InsProp : array[tasmop] of TInsProp =
  146. {$ifdef x86_64}
  147. {$i x8664pro.inc}
  148. {$else x86_64}
  149. {$i i386prop.inc}
  150. {$endif x86_64}
  151. type
  152. TOperandOrder = (op_intel,op_att);
  153. tinsentry=packed record
  154. opcode : tasmop;
  155. ops : byte;
  156. optypes : array[0..2] of longint;
  157. code : array[0..maxinfolen] of char;
  158. flags : longint;
  159. end;
  160. pinsentry=^tinsentry;
  161. { alignment for operator }
  162. tai_align = class(tai_align_abstract)
  163. reg : tregister;
  164. constructor create(b:byte);override;
  165. constructor create_op(b: byte; _op: byte);override;
  166. function calculatefillbuf(var buf : tfillbuffer):pchar;override;
  167. end;
  168. taicpu = class(tai_cpu_abstract_sym)
  169. opsize : topsize;
  170. constructor op_none(op : tasmop);
  171. constructor op_none(op : tasmop;_size : topsize);
  172. constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  173. constructor op_const(op : tasmop;_size : topsize;_op1 : aint);
  174. constructor op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  175. constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  176. constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  177. constructor op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  178. constructor op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  179. constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  180. constructor op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  181. constructor op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  182. constructor op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  183. constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  184. constructor op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  185. constructor op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister; const _op3 : treference);
  186. constructor op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  187. { this is for Jmp instructions }
  188. constructor op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  189. constructor op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  190. constructor op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  191. constructor op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  192. constructor op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  193. procedure changeopsize(siz:topsize);
  194. function GetString:string;
  195. procedure CheckNonCommutativeOpcodes;
  196. private
  197. FOperandOrder : TOperandOrder;
  198. procedure init(_size : topsize); { this need to be called by all constructor }
  199. public
  200. { the next will reset all instructions that can change in pass 2 }
  201. procedure ResetPass1;override;
  202. procedure ResetPass2;override;
  203. function CheckIfValid:boolean;
  204. function Pass1(objdata:TObjData):longint;override;
  205. procedure Pass2(objdata:TObjData);override;
  206. procedure SetOperandOrder(order:TOperandOrder);
  207. function is_same_reg_move(regtype: Tregistertype):boolean;override;
  208. { register spilling code }
  209. function spilling_get_operation_type(opnr: longint): topertype;override;
  210. private
  211. { next fields are filled in pass1, so pass2 is faster }
  212. insentry : PInsEntry;
  213. insoffset : longint;
  214. LastInsOffset : longint; { need to be public to be reset }
  215. inssize : shortint;
  216. {$ifdef x86_64}
  217. rex : byte;
  218. {$endif x86_64}
  219. function InsEnd:longint;
  220. procedure create_ot(objdata:TObjData);
  221. function Matches(p:PInsEntry):boolean;
  222. function calcsize(p:PInsEntry):shortint;
  223. procedure gencode(objdata:TObjData);
  224. function NeedAddrPrefix(opidx:byte):boolean;
  225. procedure Swapoperands;
  226. function FindInsentry(objdata:TObjData):boolean;
  227. end;
  228. function spilling_create_load(const ref:treference;r:tregister): tai;
  229. function spilling_create_store(r:tregister; const ref:treference): tai;
  230. procedure InitAsm;
  231. procedure DoneAsm;
  232. implementation
  233. uses
  234. cutils,
  235. itcpugas,
  236. symsym;
  237. {*****************************************************************************
  238. Instruction table
  239. *****************************************************************************}
  240. const
  241. {Instruction flags }
  242. IF_NONE = $00000000;
  243. IF_SM = $00000001; { size match first two operands }
  244. IF_SM2 = $00000002;
  245. IF_SB = $00000004; { unsized operands can't be non-byte }
  246. IF_SW = $00000008; { unsized operands can't be non-word }
  247. IF_SD = $00000010; { unsized operands can't be nondword }
  248. IF_SMASK = $0000001f;
  249. IF_AR0 = $00000020; { SB, SW, SD applies to argument 0 }
  250. IF_AR1 = $00000040; { SB, SW, SD applies to argument 1 }
  251. IF_AR2 = $00000060; { SB, SW, SD applies to argument 2 }
  252. IF_ARMASK = $00000060; { mask for unsized argument spec }
  253. IF_PRIV = $00000100; { it's a privileged instruction }
  254. IF_SMM = $00000200; { it's only valid in SMM }
  255. IF_PROT = $00000400; { it's protected mode only }
  256. IF_NOX86_64 = $00000800; { removed instruction in x86_64 }
  257. IF_UNDOC = $00001000; { it's an undocumented instruction }
  258. IF_FPU = $00002000; { it's an FPU instruction }
  259. IF_MMX = $00004000; { it's an MMX instruction }
  260. { it's a 3DNow! instruction }
  261. IF_3DNOW = $00008000;
  262. { it's a SSE (KNI, MMX2) instruction }
  263. IF_SSE = $00010000;
  264. { SSE2 instructions }
  265. IF_SSE2 = $00020000;
  266. { SSE3 instructions }
  267. IF_SSE3 = $00040000;
  268. { SSE64 instructions }
  269. IF_SSE64 = $00080000;
  270. { the mask for processor types }
  271. {IF_PMASK = longint($FF000000);}
  272. { the mask for disassembly "prefer" }
  273. {IF_PFMASK = longint($F001FF00);}
  274. { SVM instructions }
  275. IF_SVM = $00100000;
  276. { SSE4 instructions }
  277. IF_SSE4 = $00200000;
  278. IF_8086 = $00000000; { 8086 instruction }
  279. IF_186 = $01000000; { 186+ instruction }
  280. IF_286 = $02000000; { 286+ instruction }
  281. IF_386 = $03000000; { 386+ instruction }
  282. IF_486 = $04000000; { 486+ instruction }
  283. IF_PENT = $05000000; { Pentium instruction }
  284. IF_P6 = $06000000; { P6 instruction }
  285. IF_KATMAI = $07000000; { Katmai instructions }
  286. { Willamette instructions }
  287. IF_WILLAMETTE = $08000000;
  288. { Prescott instructions }
  289. IF_PRESCOTT = $09000000;
  290. IF_X86_64 = $0a000000;
  291. IF_CYRIX = $0b000000; { Cyrix-specific instruction }
  292. IF_AMD = $0c000000; { AMD-specific instruction }
  293. IF_CENTAUR = $0d000000; { centaur-specific instruction }
  294. { added flags }
  295. IF_PRE = $40000000; { it's a prefix instruction }
  296. IF_PASS2 = longint($80000000); { if the instruction can change in a second pass }
  297. type
  298. TInsTabCache=array[TasmOp] of longint;
  299. PInsTabCache=^TInsTabCache;
  300. const
  301. {$ifdef x86_64}
  302. InsTab:array[0..instabentries-1] of TInsEntry={$i x8664tab.inc}
  303. {$else x86_64}
  304. InsTab:array[0..instabentries-1] of TInsEntry={$i i386tab.inc}
  305. {$endif x86_64}
  306. var
  307. InsTabCache : PInsTabCache;
  308. const
  309. {$ifdef x86_64}
  310. { Intel style operands ! }
  311. opsize_2_type:array[0..2,topsize] of longint=(
  312. (OT_NONE,
  313. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,OT_BITS64,OT_BITS64,OT_BITS64,
  314. OT_BITS16,OT_BITS32,OT_BITS64,
  315. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  316. OT_BITS64,
  317. OT_NEAR,OT_FAR,OT_SHORT,
  318. OT_NONE,
  319. OT_NONE
  320. ),
  321. (OT_NONE,
  322. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,OT_BITS8,OT_BITS16,OT_BITS32,
  323. OT_BITS16,OT_BITS32,OT_BITS64,
  324. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  325. OT_BITS64,
  326. OT_NEAR,OT_FAR,OT_SHORT,
  327. OT_NONE,
  328. OT_NONE
  329. ),
  330. (OT_NONE,
  331. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,OT_NONE,
  332. OT_BITS16,OT_BITS32,OT_BITS64,
  333. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  334. OT_BITS64,
  335. OT_NEAR,OT_FAR,OT_SHORT,
  336. OT_NONE,
  337. OT_NONE
  338. )
  339. );
  340. reg_ot_table : array[tregisterindex] of longint = (
  341. {$i r8664ot.inc}
  342. );
  343. {$else x86_64}
  344. { Intel style operands ! }
  345. opsize_2_type:array[0..2,topsize] of longint=(
  346. (OT_NONE,
  347. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS16,OT_BITS32,OT_BITS32,
  348. OT_BITS16,OT_BITS32,OT_BITS64,
  349. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  350. OT_BITS64,
  351. OT_NEAR,OT_FAR,OT_SHORT,
  352. OT_NONE,
  353. OT_NONE
  354. ),
  355. (OT_NONE,
  356. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_BITS8,OT_BITS8,OT_BITS16,
  357. OT_BITS16,OT_BITS32,OT_BITS64,
  358. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  359. OT_BITS64,
  360. OT_NEAR,OT_FAR,OT_SHORT,
  361. OT_NONE,
  362. OT_NONE
  363. ),
  364. (OT_NONE,
  365. OT_BITS8,OT_BITS16,OT_BITS32,OT_BITS64,OT_NONE,OT_NONE,OT_NONE,
  366. OT_BITS16,OT_BITS32,OT_BITS64,
  367. OT_BITS32,OT_BITS64,OT_BITS80,OT_BITS64,OT_NONE,
  368. OT_BITS64,
  369. OT_NEAR,OT_FAR,OT_SHORT,
  370. OT_NONE,
  371. OT_NONE
  372. )
  373. );
  374. reg_ot_table : array[tregisterindex] of longint = (
  375. {$i r386ot.inc}
  376. );
  377. {$endif x86_64}
  378. { Operation type for spilling code }
  379. type
  380. toperation_type_table=array[tasmop,0..Max_Operands] of topertype;
  381. var
  382. operation_type_table : ^toperation_type_table;
  383. {****************************************************************************
  384. TAI_ALIGN
  385. ****************************************************************************}
  386. constructor tai_align.create(b: byte);
  387. begin
  388. inherited create(b);
  389. reg:=NR_ECX;
  390. end;
  391. constructor tai_align.create_op(b: byte; _op: byte);
  392. begin
  393. inherited create_op(b,_op);
  394. reg:=NR_NO;
  395. end;
  396. function tai_align.calculatefillbuf(var buf : tfillbuffer):pchar;
  397. const
  398. {$ifdef x86_64}
  399. alignarray:array[0..3] of string[4]=(
  400. #$66#$66#$66#$90,
  401. #$66#$66#$90,
  402. #$66#$90,
  403. #$90
  404. );
  405. {$else x86_64}
  406. alignarray:array[0..5] of string[8]=(
  407. #$8D#$B4#$26#$00#$00#$00#$00,
  408. #$8D#$B6#$00#$00#$00#$00,
  409. #$8D#$74#$26#$00,
  410. #$8D#$76#$00,
  411. #$89#$F6,
  412. #$90);
  413. {$endif x86_64}
  414. var
  415. bufptr : pchar;
  416. j : longint;
  417. begin
  418. inherited calculatefillbuf(buf);
  419. if not use_op then
  420. begin
  421. bufptr:=pchar(@buf);
  422. while (fillsize>0) do
  423. begin
  424. for j:=low(alignarray) to high(alignarray) do
  425. if (fillsize>=length(alignarray[j])) then
  426. break;
  427. move(alignarray[j][1],bufptr^,length(alignarray[j]));
  428. inc(bufptr,length(alignarray[j]));
  429. dec(fillsize,length(alignarray[j]));
  430. end;
  431. end;
  432. calculatefillbuf:=pchar(@buf);
  433. end;
  434. {*****************************************************************************
  435. Taicpu Constructors
  436. *****************************************************************************}
  437. procedure taicpu.changeopsize(siz:topsize);
  438. begin
  439. opsize:=siz;
  440. end;
  441. procedure taicpu.init(_size : topsize);
  442. begin
  443. { default order is att }
  444. FOperandOrder:=op_att;
  445. segprefix:=NR_NO;
  446. opsize:=_size;
  447. insentry:=nil;
  448. LastInsOffset:=-1;
  449. InsOffset:=0;
  450. InsSize:=0;
  451. end;
  452. constructor taicpu.op_none(op : tasmop);
  453. begin
  454. inherited create(op);
  455. init(S_NO);
  456. end;
  457. constructor taicpu.op_none(op : tasmop;_size : topsize);
  458. begin
  459. inherited create(op);
  460. init(_size);
  461. end;
  462. constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
  463. begin
  464. inherited create(op);
  465. init(_size);
  466. ops:=1;
  467. loadreg(0,_op1);
  468. end;
  469. constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : aint);
  470. begin
  471. inherited create(op);
  472. init(_size);
  473. ops:=1;
  474. loadconst(0,_op1);
  475. end;
  476. constructor taicpu.op_ref(op : tasmop;_size : topsize;const _op1 : treference);
  477. begin
  478. inherited create(op);
  479. init(_size);
  480. ops:=1;
  481. loadref(0,_op1);
  482. end;
  483. constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
  484. begin
  485. inherited create(op);
  486. init(_size);
  487. ops:=2;
  488. loadreg(0,_op1);
  489. loadreg(1,_op2);
  490. end;
  491. constructor taicpu.op_reg_const(op:tasmop; _size: topsize; _op1: tregister; _op2: aint);
  492. begin
  493. inherited create(op);
  494. init(_size);
  495. ops:=2;
  496. loadreg(0,_op1);
  497. loadconst(1,_op2);
  498. end;
  499. constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;const _op2 : treference);
  500. begin
  501. inherited create(op);
  502. init(_size);
  503. ops:=2;
  504. loadreg(0,_op1);
  505. loadref(1,_op2);
  506. end;
  507. constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister);
  508. begin
  509. inherited create(op);
  510. init(_size);
  511. ops:=2;
  512. loadconst(0,_op1);
  513. loadreg(1,_op2);
  514. end;
  515. constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : aint);
  516. begin
  517. inherited create(op);
  518. init(_size);
  519. ops:=2;
  520. loadconst(0,_op1);
  521. loadconst(1,_op2);
  522. end;
  523. constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference);
  524. begin
  525. inherited create(op);
  526. init(_size);
  527. ops:=2;
  528. loadconst(0,_op1);
  529. loadref(1,_op2);
  530. end;
  531. constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;const _op1 : treference;_op2 : tregister);
  532. begin
  533. inherited create(op);
  534. init(_size);
  535. ops:=2;
  536. loadref(0,_op1);
  537. loadreg(1,_op2);
  538. end;
  539. constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1,_op2,_op3 : tregister);
  540. begin
  541. inherited create(op);
  542. init(_size);
  543. ops:=3;
  544. loadreg(0,_op1);
  545. loadreg(1,_op2);
  546. loadreg(2,_op3);
  547. end;
  548. constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;_op3 : tregister);
  549. begin
  550. inherited create(op);
  551. init(_size);
  552. ops:=3;
  553. loadconst(0,_op1);
  554. loadreg(1,_op2);
  555. loadreg(2,_op3);
  556. end;
  557. constructor taicpu.op_reg_reg_ref(op : tasmop;_size : topsize;_op1,_op2 : tregister;const _op3 : treference);
  558. begin
  559. inherited create(op);
  560. init(_size);
  561. ops:=3;
  562. loadreg(0,_op1);
  563. loadreg(1,_op2);
  564. loadref(2,_op3);
  565. end;
  566. constructor taicpu.op_const_ref_reg(op : tasmop;_size : topsize;_op1 : aint;const _op2 : treference;_op3 : tregister);
  567. begin
  568. inherited create(op);
  569. init(_size);
  570. ops:=3;
  571. loadconst(0,_op1);
  572. loadref(1,_op2);
  573. loadreg(2,_op3);
  574. end;
  575. constructor taicpu.op_const_reg_ref(op : tasmop;_size : topsize;_op1 : aint;_op2 : tregister;const _op3 : treference);
  576. begin
  577. inherited create(op);
  578. init(_size);
  579. ops:=3;
  580. loadconst(0,_op1);
  581. loadreg(1,_op2);
  582. loadref(2,_op3);
  583. end;
  584. constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_size : topsize;_op1 : tasmsymbol);
  585. begin
  586. inherited create(op);
  587. init(_size);
  588. condition:=cond;
  589. ops:=1;
  590. loadsymbol(0,_op1,0);
  591. end;
  592. constructor taicpu.op_sym(op : tasmop;_size : topsize;_op1 : tasmsymbol);
  593. begin
  594. inherited create(op);
  595. init(_size);
  596. ops:=1;
  597. loadsymbol(0,_op1,0);
  598. end;
  599. constructor taicpu.op_sym_ofs(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint);
  600. begin
  601. inherited create(op);
  602. init(_size);
  603. ops:=1;
  604. loadsymbol(0,_op1,_op1ofs);
  605. end;
  606. constructor taicpu.op_sym_ofs_reg(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;_op2 : tregister);
  607. begin
  608. inherited create(op);
  609. init(_size);
  610. ops:=2;
  611. loadsymbol(0,_op1,_op1ofs);
  612. loadreg(1,_op2);
  613. end;
  614. constructor taicpu.op_sym_ofs_ref(op : tasmop;_size : topsize;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
  615. begin
  616. inherited create(op);
  617. init(_size);
  618. ops:=2;
  619. loadsymbol(0,_op1,_op1ofs);
  620. loadref(1,_op2);
  621. end;
  622. function taicpu.GetString:string;
  623. var
  624. i : longint;
  625. s : string;
  626. addsize : boolean;
  627. begin
  628. s:='['+std_op2str[opcode];
  629. for i:=0 to ops-1 do
  630. begin
  631. with oper[i]^ do
  632. begin
  633. if i=0 then
  634. s:=s+' '
  635. else
  636. s:=s+',';
  637. { type }
  638. addsize:=false;
  639. if (ot and OT_XMMREG)=OT_XMMREG then
  640. s:=s+'xmmreg'
  641. else
  642. if (ot and OT_MMXREG)=OT_MMXREG then
  643. s:=s+'mmxreg'
  644. else
  645. if (ot and OT_FPUREG)=OT_FPUREG then
  646. s:=s+'fpureg'
  647. else
  648. if (ot and OT_REGISTER)=OT_REGISTER then
  649. begin
  650. s:=s+'reg';
  651. addsize:=true;
  652. end
  653. else
  654. if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
  655. begin
  656. s:=s+'imm';
  657. addsize:=true;
  658. end
  659. else
  660. if (ot and OT_MEMORY)=OT_MEMORY then
  661. begin
  662. s:=s+'mem';
  663. addsize:=true;
  664. end
  665. else
  666. s:=s+'???';
  667. { size }
  668. if addsize then
  669. begin
  670. if (ot and OT_BITS8)<>0 then
  671. s:=s+'8'
  672. else
  673. if (ot and OT_BITS16)<>0 then
  674. s:=s+'16'
  675. else
  676. if (ot and OT_BITS32)<>0 then
  677. s:=s+'32'
  678. else
  679. if (ot and OT_BITS64)<>0 then
  680. s:=s+'64'
  681. else
  682. s:=s+'??';
  683. { signed }
  684. if (ot and OT_SIGNED)<>0 then
  685. s:=s+'s';
  686. end;
  687. end;
  688. end;
  689. GetString:=s+']';
  690. end;
  691. procedure taicpu.Swapoperands;
  692. var
  693. p : POper;
  694. begin
  695. { Fix the operands which are in AT&T style and we need them in Intel style }
  696. case ops of
  697. 2 : begin
  698. { 0,1 -> 1,0 }
  699. p:=oper[0];
  700. oper[0]:=oper[1];
  701. oper[1]:=p;
  702. end;
  703. 3 : begin
  704. { 0,1,2 -> 2,1,0 }
  705. p:=oper[0];
  706. oper[0]:=oper[2];
  707. oper[2]:=p;
  708. end;
  709. end;
  710. end;
  711. procedure taicpu.SetOperandOrder(order:TOperandOrder);
  712. begin
  713. if FOperandOrder<>order then
  714. begin
  715. Swapoperands;
  716. FOperandOrder:=order;
  717. end;
  718. end;
  719. procedure taicpu.CheckNonCommutativeOpcodes;
  720. begin
  721. { we need ATT order }
  722. SetOperandOrder(op_att);
  723. if (
  724. (ops=2) and
  725. (oper[0]^.typ=top_reg) and
  726. (oper[1]^.typ=top_reg) and
  727. { if the first is ST and the second is also a register
  728. it is necessarily ST1 .. ST7 }
  729. ((oper[0]^.reg=NR_ST) or
  730. (oper[0]^.reg=NR_ST0))
  731. ) or
  732. { ((ops=1) and
  733. (oper[0]^.typ=top_reg) and
  734. (oper[0]^.reg in [R_ST1..R_ST7])) or}
  735. (ops=0) then
  736. begin
  737. if opcode=A_FSUBR then
  738. opcode:=A_FSUB
  739. else if opcode=A_FSUB then
  740. opcode:=A_FSUBR
  741. else if opcode=A_FDIVR then
  742. opcode:=A_FDIV
  743. else if opcode=A_FDIV then
  744. opcode:=A_FDIVR
  745. else if opcode=A_FSUBRP then
  746. opcode:=A_FSUBP
  747. else if opcode=A_FSUBP then
  748. opcode:=A_FSUBRP
  749. else if opcode=A_FDIVRP then
  750. opcode:=A_FDIVP
  751. else if opcode=A_FDIVP then
  752. opcode:=A_FDIVRP;
  753. end;
  754. if (
  755. (ops=1) and
  756. (oper[0]^.typ=top_reg) and
  757. (getregtype(oper[0]^.reg)=R_FPUREGISTER) and
  758. (oper[0]^.reg<>NR_ST)
  759. ) then
  760. begin
  761. if opcode=A_FSUBRP then
  762. opcode:=A_FSUBP
  763. else if opcode=A_FSUBP then
  764. opcode:=A_FSUBRP
  765. else if opcode=A_FDIVRP then
  766. opcode:=A_FDIVP
  767. else if opcode=A_FDIVP then
  768. opcode:=A_FDIVRP;
  769. end;
  770. end;
  771. {*****************************************************************************
  772. Assembler
  773. *****************************************************************************}
  774. type
  775. ea = packed record
  776. sib_present : boolean;
  777. bytes : byte;
  778. size : byte;
  779. modrm : byte;
  780. sib : byte;
  781. {$ifdef x86_64}
  782. rex_present : boolean;
  783. rex : byte;
  784. {$endif x86_64}
  785. end;
  786. procedure taicpu.create_ot(objdata:TObjData);
  787. {
  788. this function will also fix some other fields which only needs to be once
  789. }
  790. var
  791. i,l,relsize : longint;
  792. currsym : TObjSymbol;
  793. begin
  794. if ops=0 then
  795. exit;
  796. { update oper[].ot field }
  797. for i:=0 to ops-1 do
  798. with oper[i]^ do
  799. begin
  800. case typ of
  801. top_reg :
  802. begin
  803. ot:=reg_ot_table[findreg_by_number(reg)];
  804. end;
  805. top_ref :
  806. begin
  807. if (ref^.refaddr=addr_no)
  808. {$ifdef x86_64}
  809. or (
  810. (ref^.refaddr=addr_pic) and
  811. (ref^.base<>NR_NO)
  812. )
  813. {$endif x86_64}
  814. then
  815. begin
  816. { create ot field }
  817. if (ot and OT_SIZE_MASK)=0 then
  818. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  819. else
  820. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  821. if (ref^.base=NR_NO) and (ref^.index=NR_NO) then
  822. ot:=ot or OT_MEM_OFFS;
  823. { fix scalefactor }
  824. if (ref^.index=NR_NO) then
  825. ref^.scalefactor:=0
  826. else
  827. if (ref^.scalefactor=0) then
  828. ref^.scalefactor:=1;
  829. end
  830. else
  831. begin
  832. if assigned(objdata) then
  833. begin
  834. currsym:=objdata.symbolref(ref^.symbol);
  835. l:=ref^.offset;
  836. if assigned(currsym) then
  837. inc(l,currsym.address);
  838. { when it is a forward jump we need to compensate the
  839. offset of the instruction since the previous time,
  840. because the symbol address is then still using the
  841. 'old-style' addressing.
  842. For backwards jumps this is not required because the
  843. address of the symbol is already adjusted to the
  844. new offset }
  845. if (l>InsOffset) and (LastInsOffset<>-1) then
  846. inc(l,InsOffset-LastInsOffset);
  847. { instruction size will then always become 2 (PFV) }
  848. relsize:=(InsOffset+2)-l;
  849. if (relsize>=-128) and (relsize<=127) and
  850. (
  851. not assigned(currsym) or
  852. (currsym.objsection=objdata.currobjsec)
  853. ) then
  854. ot:=OT_IMM8 or OT_SHORT
  855. else
  856. ot:=OT_IMM32 or OT_NEAR;
  857. end
  858. else
  859. ot:=OT_IMM32 or OT_NEAR;
  860. end;
  861. end;
  862. top_local :
  863. begin
  864. if (ot and OT_SIZE_MASK)=0 then
  865. ot:=OT_MEMORY or opsize_2_type[i,opsize]
  866. else
  867. ot:=OT_MEMORY or (ot and OT_SIZE_MASK);
  868. end;
  869. top_const :
  870. begin
  871. { allow 2nd or 3rd operand being a constant and expect no size for shuf* etc. }
  872. if (opsize=S_NO) and not(i in [1,2]) then
  873. message(asmr_e_invalid_opcode_and_operand);
  874. if (opsize<>S_W) and (longint(val)>=-128) and (val<=127) then
  875. ot:=OT_IMM8 or OT_SIGNED
  876. else
  877. ot:=OT_IMMEDIATE or opsize_2_type[i,opsize];
  878. end;
  879. top_none :
  880. begin
  881. { generated when there was an error in the
  882. assembler reader. It never happends when generating
  883. assembler }
  884. end;
  885. else
  886. internalerror(200402261);
  887. end;
  888. end;
  889. end;
  890. function taicpu.InsEnd:longint;
  891. begin
  892. InsEnd:=InsOffset+InsSize;
  893. end;
  894. function taicpu.Matches(p:PInsEntry):boolean;
  895. { * IF_SM stands for Size Match: any operand whose size is not
  896. * explicitly specified by the template is `really' intended to be
  897. * the same size as the first size-specified operand.
  898. * Non-specification is tolerated in the input instruction, but
  899. * _wrong_ specification is not.
  900. *
  901. * IF_SM2 invokes Size Match on only the first _two_ operands, for
  902. * three-operand instructions such as SHLD: it implies that the
  903. * first two operands must match in size, but that the third is
  904. * required to be _unspecified_.
  905. *
  906. * IF_SB invokes Size Byte: operands with unspecified size in the
  907. * template are really bytes, and so no non-byte specification in
  908. * the input instruction will be tolerated. IF_SW similarly invokes
  909. * Size Word, and IF_SD invokes Size Doubleword.
  910. *
  911. * (The default state if neither IF_SM nor IF_SM2 is specified is
  912. * that any operand with unspecified size in the template is
  913. * required to have unspecified size in the instruction too...)
  914. }
  915. var
  916. insot,
  917. insflags,
  918. currot,
  919. i,j,asize,oprs : longint;
  920. siz : array[0..2] of longint;
  921. begin
  922. result:=false;
  923. { Check the opcode and operands }
  924. if (p^.opcode<>opcode) or (p^.ops<>ops) then
  925. exit;
  926. for i:=0 to p^.ops-1 do
  927. begin
  928. insot:=p^.optypes[i];
  929. currot:=oper[i]^.ot;
  930. { Check the operand flags }
  931. if (insot and (not currot) and OT_NON_SIZE)<>0 then
  932. exit;
  933. { Check if the passed operand size matches with one of
  934. the supported operand sizes }
  935. if ((insot and OT_SIZE_MASK)<>0) and
  936. ((insot and currot and OT_SIZE_MASK)<>(currot and OT_SIZE_MASK)) then
  937. exit;
  938. end;
  939. { Check operand sizes }
  940. insflags:=p^.flags;
  941. if insflags and IF_SMASK<>0 then
  942. begin
  943. { as default an untyped size can get all the sizes, this is different
  944. from nasm, but else we need to do a lot checking which opcodes want
  945. size or not with the automatic size generation }
  946. asize:=-1;
  947. if (insflags and IF_SB)<>0 then
  948. asize:=OT_BITS8
  949. else if (insflags and IF_SW)<>0 then
  950. asize:=OT_BITS16
  951. else if (insflags and IF_SD)<>0 then
  952. asize:=OT_BITS32;
  953. if (insflags and IF_ARMASK)<>0 then
  954. begin
  955. siz[0]:=0;
  956. siz[1]:=0;
  957. siz[2]:=0;
  958. if (insflags and IF_AR0)<>0 then
  959. siz[0]:=asize
  960. else if (insflags and IF_AR1)<>0 then
  961. siz[1]:=asize
  962. else if (insflags and IF_AR2)<>0 then
  963. siz[2]:=asize;
  964. end
  965. else
  966. begin
  967. siz[0]:=asize;
  968. siz[1]:=asize;
  969. siz[2]:=asize;
  970. end;
  971. if (insflags and (IF_SM or IF_SM2))<>0 then
  972. begin
  973. if (insflags and IF_SM2)<>0 then
  974. oprs:=2
  975. else
  976. oprs:=p^.ops;
  977. for i:=0 to oprs-1 do
  978. if ((p^.optypes[i] and OT_SIZE_MASK) <> 0) then
  979. begin
  980. for j:=0 to oprs-1 do
  981. siz[j]:=p^.optypes[i] and OT_SIZE_MASK;
  982. break;
  983. end;
  984. end
  985. else
  986. oprs:=2;
  987. { Check operand sizes }
  988. for i:=0 to p^.ops-1 do
  989. begin
  990. insot:=p^.optypes[i];
  991. currot:=oper[i]^.ot;
  992. if ((insot and OT_SIZE_MASK)=0) and
  993. ((currot and OT_SIZE_MASK and (not siz[i]))<>0) and
  994. { Immediates can always include smaller size }
  995. ((currot and OT_IMMEDIATE)=0) and
  996. (((insot and OT_SIZE_MASK) or siz[i])<(currot and OT_SIZE_MASK)) then
  997. exit;
  998. end;
  999. end;
  1000. result:=true;
  1001. end;
  1002. procedure taicpu.ResetPass1;
  1003. begin
  1004. { we need to reset everything here, because the choosen insentry
  1005. can be invalid for a new situation where the previously optimized
  1006. insentry is not correct }
  1007. InsEntry:=nil;
  1008. InsSize:=0;
  1009. LastInsOffset:=-1;
  1010. end;
  1011. procedure taicpu.ResetPass2;
  1012. begin
  1013. { we are here in a second pass, check if the instruction can be optimized }
  1014. if assigned(InsEntry) and
  1015. ((InsEntry^.flags and IF_PASS2)<>0) then
  1016. begin
  1017. InsEntry:=nil;
  1018. InsSize:=0;
  1019. end;
  1020. LastInsOffset:=-1;
  1021. end;
  1022. function taicpu.CheckIfValid:boolean;
  1023. begin
  1024. result:=FindInsEntry(nil);
  1025. end;
  1026. function taicpu.FindInsentry(objdata:TObjData):boolean;
  1027. var
  1028. i : longint;
  1029. begin
  1030. result:=false;
  1031. { Things which may only be done once, not when a second pass is done to
  1032. optimize }
  1033. if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
  1034. begin
  1035. { We need intel style operands }
  1036. SetOperandOrder(op_intel);
  1037. { create the .ot fields }
  1038. create_ot(objdata);
  1039. { set the file postion }
  1040. current_filepos:=fileinfo;
  1041. end
  1042. else
  1043. begin
  1044. { we've already an insentry so it's valid }
  1045. result:=true;
  1046. exit;
  1047. end;
  1048. { Lookup opcode in the table }
  1049. InsSize:=-1;
  1050. i:=instabcache^[opcode];
  1051. if i=-1 then
  1052. begin
  1053. Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
  1054. exit;
  1055. end;
  1056. insentry:=@instab[i];
  1057. while (insentry^.opcode=opcode) do
  1058. begin
  1059. if matches(insentry) then
  1060. begin
  1061. result:=true;
  1062. exit;
  1063. end;
  1064. inc(insentry);
  1065. end;
  1066. Message1(asmw_e_invalid_opcode_and_operands,GetString);
  1067. { No instruction found, set insentry to nil and inssize to -1 }
  1068. insentry:=nil;
  1069. inssize:=-1;
  1070. end;
  1071. function taicpu.Pass1(objdata:TObjData):longint;
  1072. begin
  1073. Pass1:=0;
  1074. { Save the old offset and set the new offset }
  1075. InsOffset:=ObjData.CurrObjSec.Size;
  1076. { Error? }
  1077. if (Insentry=nil) and (InsSize=-1) then
  1078. exit;
  1079. { set the file postion }
  1080. current_filepos:=fileinfo;
  1081. { Get InsEntry }
  1082. if FindInsEntry(ObjData) then
  1083. begin
  1084. { Calculate instruction size }
  1085. InsSize:=calcsize(insentry);
  1086. if segprefix<>NR_NO then
  1087. inc(InsSize);
  1088. { Fix opsize if size if forced }
  1089. if (insentry^.flags and (IF_SB or IF_SW or IF_SD))<>0 then
  1090. begin
  1091. if (insentry^.flags and IF_ARMASK)=0 then
  1092. begin
  1093. if (insentry^.flags and IF_SB)<>0 then
  1094. begin
  1095. if opsize=S_NO then
  1096. opsize:=S_B;
  1097. end
  1098. else if (insentry^.flags and IF_SW)<>0 then
  1099. begin
  1100. if opsize=S_NO then
  1101. opsize:=S_W;
  1102. end
  1103. else if (insentry^.flags and IF_SD)<>0 then
  1104. begin
  1105. if opsize=S_NO then
  1106. opsize:=S_L;
  1107. end;
  1108. end;
  1109. end;
  1110. LastInsOffset:=InsOffset;
  1111. Pass1:=InsSize;
  1112. exit;
  1113. end;
  1114. LastInsOffset:=-1;
  1115. end;
  1116. procedure taicpu.Pass2(objdata:TObjData);
  1117. var
  1118. c : longint;
  1119. begin
  1120. { error in pass1 ? }
  1121. if insentry=nil then
  1122. exit;
  1123. current_filepos:=fileinfo;
  1124. { Segment override }
  1125. if (segprefix<>NR_NO) then
  1126. begin
  1127. case segprefix of
  1128. NR_CS : c:=$2e;
  1129. NR_DS : c:=$3e;
  1130. NR_ES : c:=$26;
  1131. NR_FS : c:=$64;
  1132. NR_GS : c:=$65;
  1133. NR_SS : c:=$36;
  1134. end;
  1135. objdata.writebytes(c,1);
  1136. { fix the offset for GenNode }
  1137. inc(InsOffset);
  1138. end;
  1139. { Generate the instruction }
  1140. GenCode(objdata);
  1141. end;
  1142. function taicpu.needaddrprefix(opidx:byte):boolean;
  1143. begin
  1144. result:=(oper[opidx]^.typ=top_ref) and
  1145. (oper[opidx]^.ref^.refaddr=addr_no) and
  1146. (
  1147. (
  1148. (oper[opidx]^.ref^.index<>NR_NO) and
  1149. (getsubreg(oper[opidx]^.ref^.index)<>R_SUBADDR)
  1150. ) or
  1151. (
  1152. (oper[opidx]^.ref^.base<>NR_NO) and
  1153. (getsubreg(oper[opidx]^.ref^.base)<>R_SUBADDR)
  1154. )
  1155. );
  1156. end;
  1157. function regval(r:Tregister):byte;
  1158. const
  1159. {$ifdef x86_64}
  1160. opcode_table:array[tregisterindex] of tregisterindex = (
  1161. {$i r8664op.inc}
  1162. );
  1163. {$else x86_64}
  1164. opcode_table:array[tregisterindex] of tregisterindex = (
  1165. {$i r386op.inc}
  1166. );
  1167. {$endif x86_64}
  1168. var
  1169. regidx : tregisterindex;
  1170. begin
  1171. regidx:=findreg_by_number(r);
  1172. if regidx<>0 then
  1173. result:=opcode_table[regidx]
  1174. else
  1175. begin
  1176. Message1(asmw_e_invalid_register,generic_regname(r));
  1177. result:=0;
  1178. end;
  1179. end;
  1180. {$ifdef x86_64}
  1181. function process_ea(const input:toper;out output:ea;rfield:longint):boolean;
  1182. var
  1183. sym : tasmsymbol;
  1184. md,s,rv : byte;
  1185. base,index,scalefactor,
  1186. o : longint;
  1187. ir,br : Tregister;
  1188. isub,bsub : tsubregister;
  1189. begin
  1190. process_ea:=false;
  1191. fillchar(output,sizeof(output),0);
  1192. {Register ?}
  1193. if (input.typ=top_reg) then
  1194. begin
  1195. rv:=regval(input.reg);
  1196. output.modrm:=$c0 or (rfield shl 3) or rv;
  1197. output.size:=1;
  1198. if ((getregtype(input.reg)=R_INTREGISTER) and
  1199. (getsupreg(input.reg)>=RS_R8)) or
  1200. ((getregtype(input.reg)=R_MMREGISTER) and
  1201. (getsupreg(input.reg)>=RS_XMM8)) then
  1202. begin
  1203. output.rex_present:=true;
  1204. output.rex:=output.rex or $41;
  1205. inc(output.size,1);
  1206. end
  1207. else if (getregtype(input.reg)=R_INTREGISTER) and
  1208. (getsubreg(input.reg)=R_SUBL) and
  1209. (getsupreg(input.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  1210. begin
  1211. output.rex_present:=true;
  1212. output.rex:=output.rex or $40;
  1213. inc(output.size,1);
  1214. end;
  1215. process_ea:=true;
  1216. exit;
  1217. end;
  1218. {No register, so memory reference.}
  1219. if input.typ<>top_ref then
  1220. internalerror(200409263);
  1221. ir:=input.ref^.index;
  1222. br:=input.ref^.base;
  1223. isub:=getsubreg(ir);
  1224. bsub:=getsubreg(br);
  1225. s:=input.ref^.scalefactor;
  1226. o:=input.ref^.offset;
  1227. sym:=input.ref^.symbol;
  1228. if ((ir<>NR_NO) and (getregtype(ir)<>R_INTREGISTER)) or
  1229. ((br<>NR_NO) and (br<>NR_RIP) and (getregtype(br)<>R_INTREGISTER)) then
  1230. internalerror(200301081);
  1231. { it's direct address }
  1232. if (br=NR_NO) and (ir=NR_NO) then
  1233. begin
  1234. output.sib_present:=true;
  1235. output.bytes:=4;
  1236. output.modrm:=4 or (rfield shl 3);
  1237. output.sib:=$25;
  1238. end
  1239. else if (br=NR_RIP) and (ir=NR_NO) then
  1240. begin
  1241. { rip based }
  1242. output.sib_present:=false;
  1243. output.bytes:=4;
  1244. output.modrm:=5 or (rfield shl 3);
  1245. end
  1246. else
  1247. { it's an indirection }
  1248. begin
  1249. { 16 bit or 32 bit address? }
  1250. if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
  1251. ((br<>NR_NO) and (bsub<>R_SUBADDR)) then
  1252. message(asmw_e_16bit_32bit_not_supported);
  1253. { wrong, for various reasons }
  1254. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1255. exit;
  1256. if ((getregtype(br)=R_INTREGISTER) and
  1257. (getsupreg(br)>=RS_R8)) or
  1258. ((getregtype(br)=R_MMREGISTER) and
  1259. (getsupreg(br)>=RS_XMM8)) then
  1260. begin
  1261. output.rex_present:=true;
  1262. output.rex:=output.rex or $41;
  1263. end;
  1264. if ((getregtype(ir)=R_INTREGISTER) and
  1265. (getsupreg(ir)>=RS_R8)) or
  1266. ((getregtype(ir)=R_MMREGISTER) and
  1267. (getsupreg(ir)>=RS_XMM8)) then
  1268. begin
  1269. output.rex_present:=true;
  1270. output.rex:=output.rex or $42;
  1271. end;
  1272. process_ea:=true;
  1273. { base }
  1274. case br of
  1275. NR_R8,
  1276. NR_RAX : base:=0;
  1277. NR_R9,
  1278. NR_RCX : base:=1;
  1279. NR_R10,
  1280. NR_RDX : base:=2;
  1281. NR_R11,
  1282. NR_RBX : base:=3;
  1283. NR_R12,
  1284. NR_RSP : base:=4;
  1285. NR_R13,
  1286. NR_NO,
  1287. NR_RBP : base:=5;
  1288. NR_R14,
  1289. NR_RSI : base:=6;
  1290. NR_R15,
  1291. NR_RDI : base:=7;
  1292. else
  1293. exit;
  1294. end;
  1295. { index }
  1296. case ir of
  1297. NR_R8,
  1298. NR_RAX : index:=0;
  1299. NR_R9,
  1300. NR_RCX : index:=1;
  1301. NR_R10,
  1302. NR_RDX : index:=2;
  1303. NR_R11,
  1304. NR_RBX : index:=3;
  1305. NR_R12,
  1306. NR_NO : index:=4;
  1307. NR_R13,
  1308. NR_RBP : index:=5;
  1309. NR_R14,
  1310. NR_RSI : index:=6;
  1311. NR_R15,
  1312. NR_RDI : index:=7;
  1313. else
  1314. exit;
  1315. end;
  1316. case s of
  1317. 0,
  1318. 1 : scalefactor:=0;
  1319. 2 : scalefactor:=1;
  1320. 4 : scalefactor:=2;
  1321. 8 : scalefactor:=3;
  1322. else
  1323. exit;
  1324. end;
  1325. { If rbp or r13 is used we must always include an offset }
  1326. if (br=NR_NO) or
  1327. ((br<>NR_RBP) and (br<>NR_R13) and (o=0) and (sym=nil)) then
  1328. md:=0
  1329. else
  1330. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1331. md:=1
  1332. else
  1333. md:=2;
  1334. if (br=NR_NO) or (md=2) then
  1335. output.bytes:=4
  1336. else
  1337. output.bytes:=md;
  1338. { SIB needed ? }
  1339. if (ir=NR_NO) and (br<>NR_RSP) and (br<>NR_R12) then
  1340. begin
  1341. output.sib_present:=false;
  1342. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  1343. end
  1344. else
  1345. begin
  1346. output.sib_present:=true;
  1347. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  1348. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1349. end;
  1350. end;
  1351. output.size:=1+ord(output.sib_present)+ord(output.rex_present)+output.bytes;
  1352. process_ea:=true;
  1353. end;
  1354. {$else x86_64}
  1355. function process_ea(const input:toper;out output:ea;rfield:longint):boolean;
  1356. var
  1357. sym : tasmsymbol;
  1358. md,s,rv : byte;
  1359. base,index,scalefactor,
  1360. o : longint;
  1361. ir,br : Tregister;
  1362. isub,bsub : tsubregister;
  1363. begin
  1364. process_ea:=false;
  1365. fillchar(output,sizeof(output),0);
  1366. {Register ?}
  1367. if (input.typ=top_reg) then
  1368. begin
  1369. rv:=regval(input.reg);
  1370. output.modrm:=$c0 or (rfield shl 3) or rv;
  1371. output.size:=1;
  1372. process_ea:=true;
  1373. exit;
  1374. end;
  1375. {No register, so memory reference.}
  1376. if (input.typ<>top_ref) then
  1377. internalerror(200409262);
  1378. if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
  1379. ((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
  1380. internalerror(200301081);
  1381. ir:=input.ref^.index;
  1382. br:=input.ref^.base;
  1383. isub:=getsubreg(ir);
  1384. bsub:=getsubreg(br);
  1385. s:=input.ref^.scalefactor;
  1386. o:=input.ref^.offset;
  1387. sym:=input.ref^.symbol;
  1388. { it's direct address }
  1389. if (br=NR_NO) and (ir=NR_NO) then
  1390. begin
  1391. { it's a pure offset }
  1392. output.sib_present:=false;
  1393. output.bytes:=4;
  1394. output.modrm:=5 or (rfield shl 3);
  1395. end
  1396. else
  1397. { it's an indirection }
  1398. begin
  1399. { 16 bit address? }
  1400. if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
  1401. ((br<>NR_NO) and (bsub<>R_SUBADDR)) then
  1402. message(asmw_e_16bit_not_supported);
  1403. {$ifdef OPTEA}
  1404. { make single reg base }
  1405. if (br=NR_NO) and (s=1) then
  1406. begin
  1407. br:=ir;
  1408. ir:=NR_NO;
  1409. end;
  1410. { convert [3,5,9]*EAX to EAX+[2,4,8]*EAX }
  1411. if (br=NR_NO) and
  1412. (((s=2) and (ir<>NR_ESP)) or
  1413. (s=3) or (s=5) or (s=9)) then
  1414. begin
  1415. br:=ir;
  1416. dec(s);
  1417. end;
  1418. { swap ESP into base if scalefactor is 1 }
  1419. if (s=1) and (ir=NR_ESP) then
  1420. begin
  1421. ir:=br;
  1422. br:=NR_ESP;
  1423. end;
  1424. {$endif OPTEA}
  1425. { wrong, for various reasons }
  1426. if (ir=NR_ESP) or ((s<>1) and (s<>2) and (s<>4) and (s<>8) and (ir<>NR_NO)) then
  1427. exit;
  1428. { base }
  1429. case br of
  1430. NR_EAX : base:=0;
  1431. NR_ECX : base:=1;
  1432. NR_EDX : base:=2;
  1433. NR_EBX : base:=3;
  1434. NR_ESP : base:=4;
  1435. NR_NO,
  1436. NR_EBP : base:=5;
  1437. NR_ESI : base:=6;
  1438. NR_EDI : base:=7;
  1439. else
  1440. exit;
  1441. end;
  1442. { index }
  1443. case ir of
  1444. NR_EAX : index:=0;
  1445. NR_ECX : index:=1;
  1446. NR_EDX : index:=2;
  1447. NR_EBX : index:=3;
  1448. NR_NO : index:=4;
  1449. NR_EBP : index:=5;
  1450. NR_ESI : index:=6;
  1451. NR_EDI : index:=7;
  1452. else
  1453. exit;
  1454. end;
  1455. case s of
  1456. 0,
  1457. 1 : scalefactor:=0;
  1458. 2 : scalefactor:=1;
  1459. 4 : scalefactor:=2;
  1460. 8 : scalefactor:=3;
  1461. else
  1462. exit;
  1463. end;
  1464. if (br=NR_NO) or
  1465. ((br<>NR_EBP) and (o=0) and (sym=nil)) then
  1466. md:=0
  1467. else
  1468. if ((o>=-128) and (o<=127) and (sym=nil)) then
  1469. md:=1
  1470. else
  1471. md:=2;
  1472. if (br=NR_NO) or (md=2) then
  1473. output.bytes:=4
  1474. else
  1475. output.bytes:=md;
  1476. { SIB needed ? }
  1477. if (ir=NR_NO) and (br<>NR_ESP) then
  1478. begin
  1479. output.sib_present:=false;
  1480. output.modrm:=(md shl 6) or (rfield shl 3) or base;
  1481. end
  1482. else
  1483. begin
  1484. output.sib_present:=true;
  1485. output.modrm:=(md shl 6) or (rfield shl 3) or 4;
  1486. output.sib:=(scalefactor shl 6) or (index shl 3) or base;
  1487. end;
  1488. end;
  1489. if output.sib_present then
  1490. output.size:=2+output.bytes
  1491. else
  1492. output.size:=1+output.bytes;
  1493. process_ea:=true;
  1494. end;
  1495. {$endif x86_64}
  1496. function taicpu.calcsize(p:PInsEntry):shortint;
  1497. var
  1498. codes : pchar;
  1499. c : byte;
  1500. len : shortint;
  1501. ea_data : ea;
  1502. begin
  1503. len:=0;
  1504. codes:=@p^.code[0];
  1505. {$ifdef x86_64}
  1506. rex:=0;
  1507. {$endif x86_64}
  1508. repeat
  1509. c:=ord(codes^);
  1510. inc(codes);
  1511. case c of
  1512. 0 :
  1513. break;
  1514. 1,2,3 :
  1515. begin
  1516. inc(codes,c);
  1517. inc(len,c);
  1518. end;
  1519. 8,9,10 :
  1520. begin
  1521. {$ifdef x86_64}
  1522. if ((getregtype(oper[c-8]^.reg)=R_INTREGISTER) and
  1523. (getsupreg(oper[c-8]^.reg)>=RS_R8)) or
  1524. ((getregtype(oper[c-8]^.reg)=R_MMREGISTER) and
  1525. (getsupreg(oper[c-8]^.reg)>=RS_XMM8)) then
  1526. begin
  1527. if rex=0 then
  1528. inc(len);
  1529. rex:=rex or $41;
  1530. end
  1531. else if (getregtype(oper[c-8]^.reg)=R_INTREGISTER) and
  1532. (getsubreg(oper[c-8]^.reg)=R_SUBL) and
  1533. (getsupreg(oper[c-8]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  1534. begin
  1535. if rex=0 then
  1536. inc(len);
  1537. rex:=rex or $40;
  1538. end;
  1539. {$endif x86_64}
  1540. inc(codes);
  1541. inc(len);
  1542. end;
  1543. 11 :
  1544. begin
  1545. inc(codes);
  1546. inc(len);
  1547. end;
  1548. 4,5,6,7 :
  1549. begin
  1550. if opsize=S_W then
  1551. inc(len,2)
  1552. else
  1553. inc(len);
  1554. end;
  1555. 15,
  1556. 12,13,14,
  1557. 16,17,18,
  1558. 20,21,22,
  1559. 40,41,42 :
  1560. inc(len);
  1561. 24,25,26,
  1562. 31,
  1563. 48,49,50 :
  1564. inc(len,2);
  1565. 28,29,30:
  1566. begin
  1567. if opsize=S_Q then
  1568. inc(len,8)
  1569. else
  1570. inc(len,4);
  1571. end;
  1572. 32,33,34,
  1573. 52,53,54,
  1574. 56,57,58 :
  1575. inc(len,4);
  1576. 192,193,194 :
  1577. if NeedAddrPrefix(c-192) then
  1578. inc(len);
  1579. 208,209,210 :
  1580. begin
  1581. case (oper[c-208]^.ot and OT_SIZE_MASK) of
  1582. OT_BITS16:
  1583. inc(len);
  1584. {$ifdef x86_64}
  1585. OT_BITS64:
  1586. begin
  1587. if rex=0 then
  1588. inc(len);
  1589. rex:=rex or $48;
  1590. end;
  1591. {$endif x86_64}
  1592. end;
  1593. end;
  1594. 200,
  1595. 212 :
  1596. inc(len);
  1597. 214 :
  1598. begin
  1599. {$ifdef x86_64}
  1600. if rex=0 then
  1601. inc(len);
  1602. rex:=rex or $48;
  1603. {$endif x86_64}
  1604. end;
  1605. 201,
  1606. 202,
  1607. 211,
  1608. 213,
  1609. 215,
  1610. 217,218: ;
  1611. 219,220 :
  1612. inc(len);
  1613. 221:
  1614. {$ifdef x86_64}
  1615. { remove rex competely? }
  1616. if rex=$48 then
  1617. begin
  1618. rex:=0;
  1619. dec(len);
  1620. end
  1621. else
  1622. rex:=rex and $f7
  1623. {$endif x86_64}
  1624. ;
  1625. 64..191 :
  1626. begin
  1627. {$ifdef x86_64}
  1628. if (c<127) then
  1629. begin
  1630. if (oper[c and 7]^.typ=top_reg) then
  1631. begin
  1632. if ((getregtype(oper[c and 7]^.reg)=R_INTREGISTER) and
  1633. (getsupreg(oper[c and 7]^.reg)>=RS_R8)) or
  1634. ((getregtype(oper[c and 7]^.reg)=R_MMREGISTER) and
  1635. (getsupreg(oper[c and 7]^.reg)>=RS_XMM8)) then
  1636. begin
  1637. if rex=0 then
  1638. inc(len);
  1639. rex:=rex or $44;
  1640. end
  1641. else if (getregtype(oper[c and 7]^.reg)=R_INTREGISTER) and
  1642. (getsubreg(oper[c and 7]^.reg)=R_SUBL) and
  1643. (getsupreg(oper[c and 7]^.reg) in [RS_RDI,RS_RSI,RS_RBP,RS_RSP]) then
  1644. begin
  1645. if rex=0 then
  1646. inc(len);
  1647. rex:=rex or $40;
  1648. end;
  1649. end;
  1650. end;
  1651. {$endif x86_64}
  1652. if not process_ea(oper[(c shr 3) and 7]^, ea_data, 0) then
  1653. Message(asmw_e_invalid_effective_address)
  1654. else
  1655. inc(len,ea_data.size);
  1656. {$ifdef x86_64}
  1657. { did we already create include a rex into the length calculation? }
  1658. if (rex<>0) and (ea_data.rex<>0) then
  1659. dec(len);
  1660. rex:=rex or ea_data.rex;
  1661. {$endif x86_64}
  1662. end;
  1663. else
  1664. InternalError(200603141);
  1665. end;
  1666. until false;
  1667. calcsize:=len;
  1668. end;
  1669. procedure taicpu.GenCode(objdata:TObjData);
  1670. {
  1671. * the actual codes (C syntax, i.e. octal):
  1672. * \0 - terminates the code. (Unless it's a literal of course.)
  1673. * \1, \2, \3 - that many literal bytes follow in the code stream
  1674. * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
  1675. * (POP is never used for CS) depending on operand 0
  1676. * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
  1677. * on operand 0
  1678. * \10, \11, \12 - a literal byte follows in the code stream, to be added
  1679. * to the register value of operand 0, 1 or 2
  1680. * \13 - a literal byte follows in the code stream, to be added
  1681. * to the condition code value of the instruction.
  1682. * \17 - encodes the literal byte 0. (Some compilers don't take
  1683. * kindly to a zero byte in the _middle_ of a compile time
  1684. * string constant, so I had to put this hack in.)
  1685. * \14, \15, \16 - a signed byte immediate operand, from operand 0, 1 or 2
  1686. * \20, \21, \22 - a byte immediate operand, from operand 0, 1 or 2
  1687. * \24, \25, \26 - an unsigned byte immediate operand, from operand 0, 1 or 2
  1688. * \30, \31, \32 - a word immediate operand, from operand 0, 1 or 2
  1689. * \34, \35, \36 - select between \3[012] and \4[012] depending on 16/32 bit
  1690. * assembly mode or the address-size override on the operand
  1691. * \37 - a word constant, from the _segment_ part of operand 0
  1692. * \40, \41, \42 - a long immediate operand, from operand 0, 1 or 2
  1693. * \50, \51, \52 - a byte relative operand, from operand 0, 1 or 2
  1694. * \60, \61, \62 - a word relative operand, from operand 0, 1 or 2
  1695. * \64, \65, \66 - select between \6[012] and \7[012] depending on 16/32 bit
  1696. * assembly mode or the address-size override on the operand
  1697. * \70, \71, \72 - a long relative operand, from operand 0, 1 or 2
  1698. * \1ab - a ModRM, calculated on EA in operand a, with the spare
  1699. * field the register value of operand b.
  1700. * \2ab - a ModRM, calculated on EA in operand a, with the spare
  1701. * field equal to digit b.
  1702. * \300,\301,\302 - might be an 0x67 or 0x48 byte, depending on the address size of
  1703. * the memory reference in operand x.
  1704. * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
  1705. * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
  1706. * \312 - indicates fixed 64-bit address size, i.e. optional 0x48.
  1707. * \320,\321,\322 - might be an 0x66 or 0x48 byte, depending on the operand
  1708. * size of operand x.
  1709. * \323 - insert x86_64 REX at this position.
  1710. * \324 - indicates fixed 16-bit operand size, i.e. optional 0x66.
  1711. * \325 - indicates fixed 32-bit operand size, i.e. optional 0x66.
  1712. * \326 - indicates fixed 64-bit operand size, i.e. optional 0x48.
  1713. * \327 - indicates that this instruction is only valid when the
  1714. * operand size is the default (instruction to disassembler,
  1715. * generates no code in the assembler)
  1716. * \331 - instruction not valid with REP prefix. Hint for
  1717. * disassembler only; for SSE instructions.
  1718. * \332 - disassemble a rep (0xF3 byte) prefix as repe not rep.
  1719. * \333 - REP prefix (0xF3 byte); for SSE instructions. Not encoded
  1720. * \335 - removes rex size prefix, i.e. rex.w must be the last opcode
  1721. }
  1722. var
  1723. currval : aint;
  1724. currsym : tobjsymbol;
  1725. currrelreloc,
  1726. currabsreloc,
  1727. currabsreloc32 : TObjRelocationType;
  1728. {$ifdef x86_64}
  1729. rexwritten : boolean;
  1730. {$endif x86_64}
  1731. procedure getvalsym(opidx:longint);
  1732. begin
  1733. case oper[opidx]^.typ of
  1734. top_ref :
  1735. begin
  1736. currval:=oper[opidx]^.ref^.offset;
  1737. currsym:=ObjData.symbolref(oper[opidx]^.ref^.symbol);
  1738. {$ifdef x86_64}
  1739. if oper[opidx]^.ref^.refaddr=addr_pic then
  1740. begin
  1741. currrelreloc:=RELOC_PLT32;
  1742. currabsreloc:=RELOC_GOTPCREL;
  1743. currabsreloc32:=RELOC_GOTPCREL;
  1744. end
  1745. else
  1746. {$endif x86_64}
  1747. begin
  1748. currrelreloc:=RELOC_RELATIVE;
  1749. currabsreloc:=RELOC_ABSOLUTE;
  1750. currabsreloc32:=RELOC_ABSOLUTE32;
  1751. end;
  1752. end;
  1753. top_const :
  1754. begin
  1755. currval:=aint(oper[opidx]^.val);
  1756. currsym:=nil;
  1757. currabsreloc:=RELOC_ABSOLUTE;
  1758. currabsreloc32:=RELOC_ABSOLUTE32;
  1759. end;
  1760. else
  1761. Message(asmw_e_immediate_or_reference_expected);
  1762. end;
  1763. end;
  1764. {$ifdef x86_64}
  1765. procedure maybewriterex;
  1766. begin
  1767. if (rex<>0) and not(rexwritten) then
  1768. begin
  1769. rexwritten:=true;
  1770. objdata.writebytes(rex,1);
  1771. end;
  1772. end;
  1773. {$endif x86_64}
  1774. const
  1775. CondVal:array[TAsmCond] of byte=($0,
  1776. $7, $3, $2, $6, $2, $4, $F, $D, $C, $E, $6, $2,
  1777. $3, $7, $3, $5, $E, $C, $D, $F, $1, $B, $9, $5,
  1778. $0, $A, $A, $B, $8, $4);
  1779. var
  1780. c : byte;
  1781. pb : pbyte;
  1782. codes : pchar;
  1783. bytes : array[0..3] of byte;
  1784. rfield,
  1785. data,s,opidx : longint;
  1786. ea_data : ea;
  1787. begin
  1788. { safety check }
  1789. if objdata.currobjsec.size<>insoffset then
  1790. internalerror(200130121);
  1791. { load data to write }
  1792. codes:=insentry^.code;
  1793. {$ifdef x86_64}
  1794. rexwritten:=false;
  1795. {$endif x86_64}
  1796. { Force word push/pop for registers }
  1797. if (opsize=S_W) and ((codes[0]=#4) or (codes[0]=#6) or
  1798. ((codes[0]=#1) and ((codes[2]=#5) or (codes[2]=#7)))) then
  1799. begin
  1800. bytes[0]:=$66;
  1801. objdata.writebytes(bytes,1);
  1802. end;
  1803. repeat
  1804. c:=ord(codes^);
  1805. inc(codes);
  1806. case c of
  1807. 0 :
  1808. break;
  1809. 1,2,3 :
  1810. begin
  1811. objdata.writebytes(codes^,c);
  1812. inc(codes,c);
  1813. end;
  1814. 4,6 :
  1815. begin
  1816. case oper[0]^.reg of
  1817. NR_CS:
  1818. bytes[0]:=$e;
  1819. NR_NO,
  1820. NR_DS:
  1821. bytes[0]:=$1e;
  1822. NR_ES:
  1823. bytes[0]:=$6;
  1824. NR_SS:
  1825. bytes[0]:=$16;
  1826. else
  1827. internalerror(777004);
  1828. end;
  1829. if c=4 then
  1830. inc(bytes[0]);
  1831. objdata.writebytes(bytes,1);
  1832. end;
  1833. 5,7 :
  1834. begin
  1835. case oper[0]^.reg of
  1836. NR_FS:
  1837. bytes[0]:=$a0;
  1838. NR_GS:
  1839. bytes[0]:=$a8;
  1840. else
  1841. internalerror(777005);
  1842. end;
  1843. if c=5 then
  1844. inc(bytes[0]);
  1845. objdata.writebytes(bytes,1);
  1846. end;
  1847. 8,9,10 :
  1848. begin
  1849. bytes[0]:=ord(codes^)+regval(oper[c-8]^.reg);
  1850. inc(codes);
  1851. objdata.writebytes(bytes,1);
  1852. end;
  1853. 11 :
  1854. begin
  1855. bytes[0]:=ord(codes^)+condval[condition];
  1856. inc(codes);
  1857. objdata.writebytes(bytes,1);
  1858. end;
  1859. 15 :
  1860. begin
  1861. bytes[0]:=0;
  1862. objdata.writebytes(bytes,1);
  1863. end;
  1864. 12,13,14 :
  1865. begin
  1866. getvalsym(c-12);
  1867. if (currval<-128) or (currval>127) then
  1868. Message2(asmw_e_value_exceeds_bounds,'signed byte',tostr(currval));
  1869. if assigned(currsym) then
  1870. objdata.writereloc(currval,1,currsym,currabsreloc)
  1871. else
  1872. objdata.writebytes(currval,1);
  1873. end;
  1874. 16,17,18 :
  1875. begin
  1876. getvalsym(c-16);
  1877. if (currval<-256) or (currval>255) then
  1878. Message2(asmw_e_value_exceeds_bounds,'byte',tostr(currval));
  1879. if assigned(currsym) then
  1880. objdata.writereloc(currval,1,currsym,currabsreloc)
  1881. else
  1882. objdata.writebytes(currval,1);
  1883. end;
  1884. 20,21,22 :
  1885. begin
  1886. getvalsym(c-20);
  1887. if (currval<0) or (currval>255) then
  1888. Message2(asmw_e_value_exceeds_bounds,'unsigned byte',tostr(currval));
  1889. if assigned(currsym) then
  1890. objdata.writereloc(currval,1,currsym,currabsreloc)
  1891. else
  1892. objdata.writebytes(currval,1);
  1893. end;
  1894. 24,25,26 :
  1895. begin
  1896. getvalsym(c-24);
  1897. if (currval<-65536) or (currval>65535) then
  1898. Message2(asmw_e_value_exceeds_bounds,'word',tostr(currval));
  1899. if assigned(currsym) then
  1900. objdata.writereloc(currval,2,currsym,currabsreloc)
  1901. else
  1902. objdata.writebytes(currval,2);
  1903. end;
  1904. 28,29,30 :
  1905. begin
  1906. getvalsym(c-28);
  1907. if opsize=S_Q then
  1908. begin
  1909. if assigned(currsym) then
  1910. objdata.writereloc(currval,8,currsym,currabsreloc)
  1911. else
  1912. objdata.writebytes(currval,8);
  1913. end
  1914. else
  1915. begin
  1916. if assigned(currsym) then
  1917. objdata.writereloc(currval,4,currsym,currabsreloc32)
  1918. else
  1919. objdata.writebytes(currval,4);
  1920. end
  1921. end;
  1922. 32,33,34 :
  1923. begin
  1924. getvalsym(c-32);
  1925. if assigned(currsym) then
  1926. objdata.writereloc(currval,4,currsym,currabsreloc32)
  1927. else
  1928. objdata.writebytes(currval,4);
  1929. end;
  1930. 40,41,42 :
  1931. begin
  1932. getvalsym(c-40);
  1933. data:=currval-insend;
  1934. if assigned(currsym) then
  1935. inc(data,currsym.address);
  1936. if (data>127) or (data<-128) then
  1937. Message1(asmw_e_short_jmp_out_of_range,tostr(data));
  1938. objdata.writebytes(data,1);
  1939. end;
  1940. 52,53,54 :
  1941. begin
  1942. getvalsym(c-52);
  1943. if assigned(currsym) then
  1944. objdata.writereloc(currval,4,currsym,currrelreloc)
  1945. else
  1946. objdata.writereloc(currval-insend,4,nil,currabsreloc32)
  1947. end;
  1948. 56,57,58 :
  1949. begin
  1950. getvalsym(c-56);
  1951. if assigned(currsym) then
  1952. objdata.writereloc(currval,4,currsym,currrelreloc)
  1953. else
  1954. objdata.writereloc(currval-insend,4,nil,currabsreloc32)
  1955. end;
  1956. 192,193,194 :
  1957. begin
  1958. if NeedAddrPrefix(c-192) then
  1959. begin
  1960. bytes[0]:=$67;
  1961. objdata.writebytes(bytes,1);
  1962. end;
  1963. end;
  1964. 200 :
  1965. begin
  1966. bytes[0]:=$67;
  1967. objdata.writebytes(bytes,1);
  1968. end;
  1969. 208,209,210 :
  1970. begin
  1971. case oper[c-208]^.ot and OT_SIZE_MASK of
  1972. OT_BITS16 :
  1973. begin
  1974. bytes[0]:=$66;
  1975. objdata.writebytes(bytes,1);
  1976. end;
  1977. {$ifndef x86_64}
  1978. OT_BITS64 :
  1979. Message(asmw_e_64bit_not_supported);
  1980. {$endif x86_64}
  1981. end;
  1982. {$ifdef x86_64}
  1983. maybewriterex;
  1984. {$endif x86_64}
  1985. end;
  1986. 211,
  1987. 213 :
  1988. begin
  1989. {$ifdef x86_64}
  1990. maybewriterex;
  1991. {$endif x86_64}
  1992. end;
  1993. 212 :
  1994. begin
  1995. bytes[0]:=$66;
  1996. objdata.writebytes(bytes,1);
  1997. {$ifdef x86_64}
  1998. maybewriterex;
  1999. {$endif x86_64}
  2000. end;
  2001. 214 :
  2002. begin
  2003. {$ifdef x86_64}
  2004. maybewriterex;
  2005. {$else x86_64}
  2006. Message(asmw_e_64bit_not_supported);
  2007. {$endif x86_64}
  2008. end;
  2009. 219 :
  2010. begin
  2011. bytes[0]:=$f3;
  2012. objdata.writebytes(bytes,1);
  2013. {$ifdef x86_64}
  2014. maybewriterex;
  2015. {$endif x86_64}
  2016. end;
  2017. 220 :
  2018. begin
  2019. bytes[0]:=$f2;
  2020. objdata.writebytes(bytes,1);
  2021. end;
  2022. 221:
  2023. ;
  2024. 201,
  2025. 202,
  2026. 215,
  2027. 217,218 :
  2028. begin
  2029. { these are dissambler hints or 32 bit prefixes which
  2030. are not needed
  2031. It's usefull to write rex :) (FK) }
  2032. {$ifdef x86_64}
  2033. maybewriterex;
  2034. {$endif x86_64}
  2035. end;
  2036. 31,
  2037. 48,49,50 :
  2038. begin
  2039. InternalError(777006);
  2040. end
  2041. else
  2042. begin
  2043. { rex should be written at this point }
  2044. {$ifdef x86_64}
  2045. if (rex<>0) and not(rexwritten) then
  2046. internalerror(200603191);
  2047. {$endif x86_64}
  2048. if (c>=64) and (c<=191) then
  2049. begin
  2050. if (c<127) then
  2051. begin
  2052. if (oper[c and 7]^.typ=top_reg) then
  2053. rfield:=regval(oper[c and 7]^.reg)
  2054. else
  2055. rfield:=regval(oper[c and 7]^.ref^.base);
  2056. end
  2057. else
  2058. rfield:=c and 7;
  2059. opidx:=(c shr 3) and 7;
  2060. if not process_ea(oper[opidx]^,ea_data,rfield) then
  2061. Message(asmw_e_invalid_effective_address);
  2062. pb:=@bytes[0];
  2063. pb^:=ea_data.modrm;
  2064. inc(pb);
  2065. if ea_data.sib_present then
  2066. begin
  2067. pb^:=ea_data.sib;
  2068. inc(pb);
  2069. end;
  2070. s:=pb-@bytes[0];
  2071. objdata.writebytes(bytes,s);
  2072. case ea_data.bytes of
  2073. 0 : ;
  2074. 1 :
  2075. begin
  2076. if (oper[opidx]^.ot and OT_MEMORY)=OT_MEMORY then
  2077. begin
  2078. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  2079. {$ifdef x86_64}
  2080. if oper[opidx]^.ref^.refaddr=addr_pic then
  2081. currabsreloc:=RELOC_GOTPCREL
  2082. else
  2083. {$endif x86_64}
  2084. currabsreloc:=RELOC_ABSOLUTE;
  2085. objdata.writereloc(oper[opidx]^.ref^.offset,1,currsym,currabsreloc);
  2086. end
  2087. else
  2088. begin
  2089. bytes[0]:=oper[opidx]^.ref^.offset;
  2090. objdata.writebytes(bytes,1);
  2091. end;
  2092. inc(s);
  2093. end;
  2094. 2,4 :
  2095. begin
  2096. currsym:=objdata.symbolref(oper[opidx]^.ref^.symbol);
  2097. {$ifdef x86_64}
  2098. if oper[opidx]^.ref^.refaddr=addr_pic then
  2099. currabsreloc:=RELOC_GOTPCREL
  2100. else
  2101. {$endif x86_64}
  2102. currabsreloc:=RELOC_ABSOLUTE32;
  2103. objdata.writereloc(oper[opidx]^.ref^.offset,ea_data.bytes,currsym,currabsreloc);
  2104. inc(s,ea_data.bytes);
  2105. end;
  2106. end;
  2107. end
  2108. else
  2109. InternalError(777007);
  2110. end;
  2111. end;
  2112. until false;
  2113. end;
  2114. function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
  2115. begin
  2116. result:=(((opcode=A_MOV) or (opcode=A_XCHG)) and
  2117. (regtype = R_INTREGISTER) and
  2118. (ops=2) and
  2119. (oper[0]^.typ=top_reg) and
  2120. (oper[1]^.typ=top_reg) and
  2121. (oper[0]^.reg=oper[1]^.reg)
  2122. ) or
  2123. (((opcode=A_MOVSS) or (opcode=A_MOVSD) or (opcode=A_MOVQ) or
  2124. (opcode=A_MOVAPS) or (OPCODE=A_MOVAPD)) and
  2125. (regtype = R_MMREGISTER) and
  2126. (ops=2) and
  2127. (oper[0]^.typ=top_reg) and
  2128. (oper[1]^.typ=top_reg) and
  2129. (oper[0]^.reg=oper[1]^.reg)
  2130. );
  2131. end;
  2132. procedure build_spilling_operation_type_table;
  2133. var
  2134. opcode : tasmop;
  2135. i : integer;
  2136. begin
  2137. new(operation_type_table);
  2138. fillchar(operation_type_table^,sizeof(toperation_type_table),byte(operand_read));
  2139. for opcode:=low(tasmop) to high(tasmop) do
  2140. begin
  2141. for i:=1 to MaxInsChanges do
  2142. begin
  2143. case InsProp[opcode].Ch[i] of
  2144. Ch_Rop1 :
  2145. operation_type_table^[opcode,0]:=operand_read;
  2146. Ch_Wop1 :
  2147. operation_type_table^[opcode,0]:=operand_write;
  2148. Ch_RWop1,
  2149. Ch_Mop1 :
  2150. operation_type_table^[opcode,0]:=operand_readwrite;
  2151. Ch_Rop2 :
  2152. operation_type_table^[opcode,1]:=operand_read;
  2153. Ch_Wop2 :
  2154. operation_type_table^[opcode,1]:=operand_write;
  2155. Ch_RWop2,
  2156. Ch_Mop2 :
  2157. operation_type_table^[opcode,1]:=operand_readwrite;
  2158. Ch_Rop3 :
  2159. operation_type_table^[opcode,2]:=operand_read;
  2160. Ch_Wop3 :
  2161. operation_type_table^[opcode,2]:=operand_write;
  2162. Ch_RWop3,
  2163. Ch_Mop3 :
  2164. operation_type_table^[opcode,2]:=operand_readwrite;
  2165. end;
  2166. end;
  2167. end;
  2168. { Special cases that can't be decoded from the InsChanges flags }
  2169. operation_type_table^[A_IMUL,1]:=operand_readwrite;
  2170. end;
  2171. function taicpu.spilling_get_operation_type(opnr: longint): topertype;
  2172. begin
  2173. { the information in the instruction table is made for the string copy
  2174. operation MOVSD so hack here (FK)
  2175. }
  2176. if (opcode=A_MOVSD) and (ops=2) then
  2177. begin
  2178. case opnr of
  2179. 0:
  2180. result:=operand_read;
  2181. 1:
  2182. result:=operand_write;
  2183. else
  2184. internalerror(200506055);
  2185. end
  2186. end
  2187. else
  2188. result:=operation_type_table^[opcode,opnr];
  2189. end;
  2190. function spilling_create_load(const ref:treference;r:tregister): tai;
  2191. begin
  2192. case getregtype(r) of
  2193. R_INTREGISTER :
  2194. result:=taicpu.op_ref_reg(A_MOV,reg2opsize(r),ref,r);
  2195. R_MMREGISTER :
  2196. case getsubreg(r) of
  2197. R_SUBMMD:
  2198. result:=taicpu.op_ref_reg(A_MOVSD,reg2opsize(r),ref,r);
  2199. R_SUBMMS:
  2200. result:=taicpu.op_ref_reg(A_MOVSS,reg2opsize(r),ref,r);
  2201. R_SUBMMWHOLE:
  2202. result:=taicpu.op_ref_reg(A_MOVQ,S_NO,ref,r);
  2203. else
  2204. internalerror(200506043);
  2205. end;
  2206. else
  2207. internalerror(200401041);
  2208. end;
  2209. end;
  2210. function spilling_create_store(r:tregister; const ref:treference): tai;
  2211. begin
  2212. case getregtype(r) of
  2213. R_INTREGISTER :
  2214. result:=taicpu.op_reg_ref(A_MOV,reg2opsize(r),r,ref);
  2215. R_MMREGISTER :
  2216. case getsubreg(r) of
  2217. R_SUBMMD:
  2218. result:=taicpu.op_reg_ref(A_MOVSD,reg2opsize(r),r,ref);
  2219. R_SUBMMS:
  2220. result:=taicpu.op_reg_ref(A_MOVSS,reg2opsize(r),r,ref);
  2221. R_SUBMMWHOLE:
  2222. result:=taicpu.op_reg_ref(A_MOVQ,S_NO,r,ref);
  2223. else
  2224. internalerror(200506042);
  2225. end;
  2226. else
  2227. internalerror(200401041);
  2228. end;
  2229. end;
  2230. {*****************************************************************************
  2231. Instruction table
  2232. *****************************************************************************}
  2233. procedure BuildInsTabCache;
  2234. var
  2235. i : longint;
  2236. begin
  2237. new(instabcache);
  2238. FillChar(instabcache^,sizeof(tinstabcache),$ff);
  2239. i:=0;
  2240. while (i<InsTabEntries) do
  2241. begin
  2242. if InsTabCache^[InsTab[i].OPcode]=-1 then
  2243. InsTabCache^[InsTab[i].OPcode]:=i;
  2244. inc(i);
  2245. end;
  2246. end;
  2247. procedure InitAsm;
  2248. begin
  2249. build_spilling_operation_type_table;
  2250. if not assigned(instabcache) then
  2251. BuildInsTabCache;
  2252. end;
  2253. procedure DoneAsm;
  2254. begin
  2255. if assigned(operation_type_table) then
  2256. begin
  2257. dispose(operation_type_table);
  2258. operation_type_table:=nil;
  2259. end;
  2260. if assigned(instabcache) then
  2261. begin
  2262. dispose(instabcache);
  2263. instabcache:=nil;
  2264. end;
  2265. end;
  2266. begin
  2267. cai_align:=tai_align;
  2268. cai_cpu:=taicpu;
  2269. end.