| .. |
|
aasmcpu.pas
|
c49c8210a3
m68k: some initial HLCG, use BSET/BCLR instructions for simple bit manipulation
|
10 lat temu |
|
ag68kgas.pas
|
c062e55aa2
m68k: after a compare on the FPU, move the condition flags back to the CPU. this should make floating point compare actually working
|
10 lat temu |
|
aoptcpu.pas
|
b617345e43
m68k: disabled premature MOVEA #0,Ax to SUBA Ax,Ax in the CG, because it breaks with spilling temp replacement and moved it to the optimizer, where it belongs. this fixes some code with potentially heavy address register pressure, like the IDE.
|
10 lat temu |
|
aoptcpub.pas
|
3c2031c9c6
m68k: added RegModifiedByInstruction implementation, enabled RefsHaveScale define
|
10 lat temu |
|
aoptcpud.pas
|
790a4fe2d3
* log and id tags removed
|
20 lat temu |
|
cgcpu.pas
|
201121d7c9
* synchronised with trunk till r30345
|
10 lat temu |
|
cpubase.pas
|
258b42de26
m68k: added support for FSIN/FCOS. these are software supported on the 68040, so we should have a separate 68040/060 FPU option too, to avoid these in the future.
|
10 lat temu |
|
cpuinfo.pas
|
5c67fcc43f
+ change always floating point divisions into multiplications if they are a power of two,
|
11 lat temu |
|
cpunode.pas
|
db50666b3b
n68kinl: added inline nodes for 68k. implemented first_sqr_real and second_sqr_real for 68881 FPU
|
10 lat temu |
|
cpupara.pas
|
67b8aceaee
* synchronized with privatetrunk till r30095
|
10 lat temu |
|
cpupi.pas
|
786e814d49
Use the correct frame pointer register: A6 on Unixes and A5 on everything else. The only
|
13 lat temu |
|
cputarg.pas
|
df7af34de9
m68k: very early optimizer implementation experiments
|
11 lat temu |
|
hlcgcpu.pas
|
201121d7c9
* synchronised with trunk till r30345
|
10 lat temu |
|
itcpugas.pas
|
258b42de26
m68k: added support for FSIN/FCOS. these are software supported on the 68040, so we should have a separate 68040/060 FPU option too, to avoid these in the future.
|
10 lat temu |
|
m68kreg.dat
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
n68kadd.pas
|
3650991d90
m68k: support LOC_REFERENCE/LOC_CREFERENCE for floating point instructions where possible
|
10 lat temu |
|
n68kcal.pas
|
b7da785688
* m68k: support stack cleanup at caller side, fixed calculation of pushed parameters size and offsets and cleaned out another pile of junk.
|
11 lat temu |
|
n68kcnv.pas
|
935820293c
m68k: in tm68ktypeconvnode.int_to_real, fix the reference before using it, and if the source is a register, make sure it's a data register
|
10 lat temu |
|
n68kinl.pas
|
258b42de26
m68k: added support for FSIN/FCOS. these are software supported on the 68040, so we should have a separate 68040/060 FPU option too, to avoid these in the future.
|
10 lat temu |
|
n68kmat.pas
|
5f66d63335
m68k: disabled comment generation
|
10 lat temu |
|
n68kmem.pas
|
ad301f8fa1
m68k: implemented t68kvecnode.update_reference_reg_packed. same as the generic one, but allocates int registers instead of address registers, because on 68k IMUL,SHR/SHL and AND can't work on address registers, which results in a lot of register shuffling
|
10 lat temu |
|
r68kcon.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
r68kgas.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
r68kgri.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
r68knor.inc
|
b19572b41d
+ gas registers
|
21 lat temu |
|
r68knum.inc
|
2555cc8496
* register numbers for address registers fixed
|
21 lat temu |
|
r68krni.inc
|
b19572b41d
+ gas registers
|
21 lat temu |
|
r68ksri.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
r68ksta.inc
|
2555cc8496
* register numbers for address registers fixed
|
21 lat temu |
|
r68kstd.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
r68ksup.inc
|
7ee09b9620
instead of supporting SP only, have register A7 defined, and have SP as an alias
|
11 lat temu |
|
ra68k.pas
|
392da9e43f
* fix warnings when compiling the compiler with DFA optimizer enabled on m68k
|
11 lat temu |
|
ra68kmot.pas
|
392da9e43f
* fix warnings when compiling the compiler with DFA optimizer enabled on m68k
|
11 lat temu |
|
rgcpu.pas
|
bd203a5b57
* synchronised with trunk till r30240
|
10 lat temu |
|
symcpu.pas
|
aa6b62cf4c
Add new procedure option: po_syscall_has_libsym,
|
11 lat temu |
Jonas Maebe
201121d7c9
* synchronised with trunk till r30345