* patch by Christo Crause: more AVR controllers, resolves #36683

git-svn-id: trunk@44130 -

.gitattributes

@@ -10365,8 +10365,10 @@ rtl/embedded/avr/atmega1280.pp svneol=native#text/plain
 rtl/embedded/avr/atmega1281.pp svneol=native#text/plain
 rtl/embedded/avr/atmega1284.pp svneol=native#text/plain
 rtl/embedded/avr/atmega1284p.pp svneol=native#text/plain
+rtl/embedded/avr/atmega1284rfr2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega128a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega128rfa1.pp svneol=native#text/plain
+rtl/embedded/avr/atmega128rfr2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega16.pp svneol=native#text/plain
 rtl/embedded/avr/atmega1608.pp svneol=native#text/pascal
 rtl/embedded/avr/atmega1609.pp svneol=native#text/pascal
@@ -10386,12 +10388,16 @@ rtl/embedded/avr/atmega169a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega169p.pp svneol=native#text/plain
 rtl/embedded/avr/atmega169pa.pp svneol=native#text/plain
 rtl/embedded/avr/atmega16a.pp svneol=native#text/plain
+rtl/embedded/avr/atmega16hva.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega16hvb.pp svneol=native#text/plain
+rtl/embedded/avr/atmega16hvbrevb.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega16m1.pp svneol=native#text/plain
 rtl/embedded/avr/atmega16u2.pp svneol=native#text/plain
 rtl/embedded/avr/atmega16u4.pp svneol=native#text/plain
 rtl/embedded/avr/atmega2560.pp svneol=native#text/plain
 rtl/embedded/avr/atmega2561.pp svneol=native#text/plain
+rtl/embedded/avr/atmega2564rfr2.pp -text svneol=native#text/pascal
+rtl/embedded/avr/atmega256rfr2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega32.pp svneol=native#text/plain
 rtl/embedded/avr/atmega3208.pp svneol=native#text/pascal
 rtl/embedded/avr/atmega3209.pp svneol=native#text/pascal
@@ -10421,9 +10427,11 @@ rtl/embedded/avr/atmega329pa.pp svneol=native#text/plain
 rtl/embedded/avr/atmega32a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega32c1.pp svneol=native#text/plain
 rtl/embedded/avr/atmega32hvb.pp svneol=native#text/plain
+rtl/embedded/avr/atmega32hvbrevb.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega32m1.pp svneol=native#text/plain
 rtl/embedded/avr/atmega32u2.pp svneol=native#text/plain
 rtl/embedded/avr/atmega32u4.pp svneol=native#text/plain
+rtl/embedded/avr/atmega406.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega48.pp svneol=native#text/plain
 rtl/embedded/avr/atmega4808.pp svneol=native#text/pascal
 rtl/embedded/avr/atmega4809.pp svneol=native#text/pascal
@@ -10437,6 +10445,7 @@ rtl/embedded/avr/atmega644.pp svneol=native#text/plain
 rtl/embedded/avr/atmega644a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega644p.pp svneol=native#text/plain
 rtl/embedded/avr/atmega644pa.pp svneol=native#text/plain
+rtl/embedded/avr/atmega644rfr2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega645.pp svneol=native#text/plain
 rtl/embedded/avr/atmega6450.pp svneol=native#text/plain
 rtl/embedded/avr/atmega6450a.pp svneol=native#text/plain
@@ -10451,7 +10460,9 @@ rtl/embedded/avr/atmega649a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega649p.pp svneol=native#text/plain
 rtl/embedded/avr/atmega64a.pp svneol=native#text/plain
 rtl/embedded/avr/atmega64c1.pp svneol=native#text/plain
+rtl/embedded/avr/atmega64hve2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega64m1.pp svneol=native#text/plain
+rtl/embedded/avr/atmega64rfr2.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega8.pp svneol=native#text/plain
 rtl/embedded/avr/atmega808.pp svneol=native#text/pascal
 rtl/embedded/avr/atmega809.pp svneol=native#text/pascal
@@ -10463,6 +10474,7 @@ rtl/embedded/avr/atmega88p.pp svneol=native#text/plain
 rtl/embedded/avr/atmega88pa.pp svneol=native#text/plain
 rtl/embedded/avr/atmega88pb.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega8a.pp svneol=native#text/plain
+rtl/embedded/avr/atmega8hva.pp -text svneol=native#text/pascal
 rtl/embedded/avr/atmega8u2.pp svneol=native#text/plain
 rtl/embedded/avr/attiny10.pp svneol=native#text/plain
 rtl/embedded/avr/attiny102.pp svneol=native#text/pascal
@@ -10475,6 +10487,9 @@ rtl/embedded/avr/attiny1607.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny1614.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny1616.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny1617.pp svneol=native#text/pascal
+rtl/embedded/avr/attiny1624.pp svneol=native#text/pascal
+rtl/embedded/avr/attiny1626.pp svneol=native#text/pascal
+rtl/embedded/avr/attiny1627.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny1634.pp svneol=native#text/plain
 rtl/embedded/avr/attiny167.pp svneol=native#text/plain
 rtl/embedded/avr/attiny20.pp svneol=native#text/plain
@@ -10507,6 +10522,7 @@ rtl/embedded/avr/attiny417.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny4313.pp svneol=native#text/plain
 rtl/embedded/avr/attiny43u.pp svneol=native#text/plain
 rtl/embedded/avr/attiny44.pp svneol=native#text/plain
+rtl/embedded/avr/attiny441.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny44a.pp svneol=native#text/plain
 rtl/embedded/avr/attiny45.pp svneol=native#text/plain
 rtl/embedded/avr/attiny461.pp svneol=native#text/plain
@@ -10521,6 +10537,7 @@ rtl/embedded/avr/attiny816.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny817.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny828.pp svneol=native#text/plain
 rtl/embedded/avr/attiny84.pp svneol=native#text/plain
+rtl/embedded/avr/attiny841.pp svneol=native#text/pascal
 rtl/embedded/avr/attiny84a.pp svneol=native#text/plain
 rtl/embedded/avr/attiny85.pp svneol=native#text/plain
 rtl/embedded/avr/attiny861.pp svneol=native#text/plain

compiler/avr/cpuinfo.pas

@@ -82,10 +82,13 @@ Type
       ct_ata6286,
       ct_atmega8,
       ct_atmega8a,
+      ct_atmega8hva,
       ct_atmega8u2,
       ct_atmega16,
       ct_atmega16a,
+      ct_atmega16hva,
       ct_atmega16hvb,
+      ct_atmega16hvbrevb,
       ct_atmega16m1,
       ct_atmega16u2,
       ct_atmega16u4,
@@ -93,6 +96,7 @@ Type
       ct_atmega32a,
       ct_atmega32c1,
       ct_atmega32hvb,
+      ct_atmega32hvbrevb,
       ct_atmega32m1,
       ct_atmega32u2,
       ct_atmega32u4,
@@ -104,7 +108,9 @@ Type
       ct_atmega64,
       ct_atmega64a,
       ct_atmega64c1,
+      ct_atmega64hve2,
       ct_atmega64m1,
+      ct_atmega64rfr2,
       ct_atmega88,
       ct_atmega88a,
       ct_atmega88p,
@@ -113,6 +119,7 @@ Type
       ct_atmega128,
       ct_atmega128a,
       ct_atmega128rfa1,
+      ct_atmega128rfr2,
       ct_atmega162,
       ct_atmega164a,
       ct_atmega164p,
@@ -128,6 +135,7 @@ Type
       ct_atmega169a,
       ct_atmega169p,
       ct_atmega169pa,
+      ct_atmega256rfr2,
       ct_atmega324a,
       ct_atmega324p,
       ct_atmega324pa,
@@ -143,11 +151,13 @@ Type
       ct_atmega329a,
       ct_atmega329p,
       ct_atmega329pa,
+      ct_atmega406,
       ct_atmega640,
       ct_atmega644,
       ct_atmega644a,
       ct_atmega644p,
       ct_atmega644pa,
+      ct_atmega644rfr2,
       ct_atmega645,
       ct_atmega645a,
       ct_atmega645p,
@@ -160,10 +170,12 @@ Type
       ct_atmega1281,
       ct_atmega1284,
       ct_atmega1284p,
+      ct_atmega1284rfr2,
       ct_atmega1608,
       ct_atmega1609,
       ct_atmega2560,
       ct_atmega2561,
+      ct_atmega2564rfr2,
       ct_atmega3208,
       ct_atmega3209,
       ct_atmega3250,
@@ -224,6 +236,7 @@ Type
       ct_attiny416,
       ct_attiny416auto,
       ct_attiny417,
+      ct_attiny441,
       ct_attiny461,
       ct_attiny461a,
       ct_attiny804,
@@ -233,6 +246,7 @@ Type
       ct_attiny816,
       ct_attiny817,
       ct_attiny828,
+      ct_attiny841,
       ct_attiny861,
       ct_attiny861a,
       ct_attiny1604,
@@ -241,6 +255,9 @@ Type
       ct_attiny1614,
       ct_attiny1616,
       ct_attiny1617,
+      ct_attiny1624,
+      ct_attiny1626,
+      ct_attiny1627,
       ct_attiny1634,
       ct_attiny2313,
       ct_attiny2313a,
@@ -248,7 +265,6 @@ Type
       ct_attiny3216,
       ct_attiny3217,
       ct_attiny4313,
-
       // Controller board aliases
       ct_arduinoleonardo,
       ct_arduinomega,
@@ -256,6 +272,7 @@ Type
       ct_arduinonano,
       ct_arduinonanoevery,
       ct_arduinouno,
+      ct_atmega256rfr2xpro,
       ct_atmega324pbxpro,
       ct_atmega1284pxplained,
       ct_atmega4809xpro,
@@ -361,10 +378,13 @@ Const
         ,(controllertypestr:'ATA6286';controllerunitstr:'ATA6286';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:512;eeprombase:0;eepromsize:320)
         ,(controllertypestr:'ATMEGA8';controllerunitstr:'ATMEGA8';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:96;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA8A';controllerunitstr:'ATMEGA8A';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:96;sramsize:1024;eeprombase:0;eepromsize:512)
+        ,(controllertypestr:'ATMEGA8HVA';controllerunitstr:'ATMEGA8HVA';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:512;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATMEGA8U2';controllerunitstr:'ATMEGA8U2';cputype:cpu_avr35;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:512;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA16';controllerunitstr:'ATMEGA16';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:96;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA16A';controllerunitstr:'ATMEGA16A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:96;sramsize:1024;eeprombase:0;eepromsize:512)
+        ,(controllertypestr:'ATMEGA16HVA';controllerunitstr:'ATMEGA16HVA';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:512;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATMEGA16HVB';controllerunitstr:'ATMEGA16HVB';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
+        ,(controllertypestr:'ATMEGA16HVBREVB';controllerunitstr:'ATMEGA16HVBREVB';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA16M1';controllerunitstr:'ATMEGA16M1';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA16U2';controllerunitstr:'ATMEGA16U2';cputype:cpu_avr35;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:512;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA16U4';controllerunitstr:'ATMEGA16U4';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1280;eeprombase:0;eepromsize:512)
@@ -372,6 +392,7 @@ Const
         ,(controllertypestr:'ATMEGA32A';controllerunitstr:'ATMEGA32A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:96;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA32C1';controllerunitstr:'ATMEGA32C1';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA32HVB';controllerunitstr:'ATMEGA32HVB';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
+        ,(controllertypestr:'ATMEGA32HVBREVB';controllerunitstr:'ATMEGA32HVBREVB';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA32M1';controllerunitstr:'ATMEGA32M1';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA32U2';controllerunitstr:'ATMEGA32U2';cputype:cpu_avr35;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:1024;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA32U4';controllerunitstr:'ATMEGA32U4';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2560;eeprombase:0;eepromsize:1024)
@@ -383,7 +404,9 @@ Const
         ,(controllertypestr:'ATMEGA64';controllerunitstr:'ATMEGA64';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA64A';controllerunitstr:'ATMEGA64A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA64C1';controllerunitstr:'ATMEGA64C1';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
+        ,(controllertypestr:'ATMEGA64HVE2';controllerunitstr:'ATMEGA64HVE2';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA64M1';controllerunitstr:'ATMEGA64M1';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
+        ,(controllertypestr:'ATMEGA64RFR2';controllerunitstr:'ATMEGA64RFR2';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:512;sramsize:8192;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA88';controllerunitstr:'ATMEGA88';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA88A';controllerunitstr:'ATMEGA88A';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA88P';controllerunitstr:'ATMEGA88P';cputype:cpu_avr4;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
@@ -392,6 +415,7 @@ Const
         ,(controllertypestr:'ATMEGA128';controllerunitstr:'ATMEGA128';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:256;sramsize:4096;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA128A';controllerunitstr:'ATMEGA128A';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:256;sramsize:4096;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA128RFA1';controllerunitstr:'ATMEGA128RFA1';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:512;sramsize:16384;eeprombase:0;eepromsize:4096)
+        ,(controllertypestr:'ATMEGA128RFR2';controllerunitstr:'ATMEGA128RFR2';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:512;sramsize:16384;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA162';controllerunitstr:'ATMEGA162';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA164A';controllerunitstr:'ATMEGA164A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA164P';controllerunitstr:'ATMEGA164P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
@@ -407,6 +431,7 @@ Const
         ,(controllertypestr:'ATMEGA169A';controllerunitstr:'ATMEGA169A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA169P';controllerunitstr:'ATMEGA169P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA169PA';controllerunitstr:'ATMEGA169PA';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:512)
+        ,(controllertypestr:'ATMEGA256RFR2';controllerunitstr:'ATMEGA256RFR2';cputype:cpu_avr6;fputype:fpu_soft;flashbase:0;flashsize:262144;srambase:512;sramsize:32768;eeprombase:0;eepromsize:8192)
         ,(controllertypestr:'ATMEGA324A';controllerunitstr:'ATMEGA324A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA324P';controllerunitstr:'ATMEGA324P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA324PA';controllerunitstr:'ATMEGA324PA';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
@@ -422,11 +447,13 @@ Const
         ,(controllertypestr:'ATMEGA329A';controllerunitstr:'ATMEGA329A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA329P';controllerunitstr:'ATMEGA329P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
         ,(controllertypestr:'ATMEGA329PA';controllerunitstr:'ATMEGA329PA';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
+        ,(controllertypestr:'ATMEGA406';controllerunitstr:'ATMEGA406';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:40960;srambase:256;sramsize:2048;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATMEGA640';controllerunitstr:'ATMEGA640';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:512;sramsize:8192;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA644';controllerunitstr:'ATMEGA644';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA644A';controllerunitstr:'ATMEGA644A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA644P';controllerunitstr:'ATMEGA644P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA644PA';controllerunitstr:'ATMEGA644PA';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
+        ,(controllertypestr:'ATMEGA644RFR2';controllerunitstr:'ATMEGA644RFR2';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:512;sramsize:8192;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA645';controllerunitstr:'ATMEGA645';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA645A';controllerunitstr:'ATMEGA645A';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
         ,(controllertypestr:'ATMEGA645P';controllerunitstr:'ATMEGA645P';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:65536;srambase:256;sramsize:4096;eeprombase:0;eepromsize:2048)
@@ -439,10 +466,12 @@ Const
         ,(controllertypestr:'ATMEGA1281';controllerunitstr:'ATMEGA1281';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:512;sramsize:8192;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA1284';controllerunitstr:'ATMEGA1284';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:256;sramsize:16384;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA1284P';controllerunitstr:'ATMEGA1284P';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:256;sramsize:16384;eeprombase:0;eepromsize:4096)
+        ,(controllertypestr:'ATMEGA1284RFR2';controllerunitstr:'ATMEGA1284RFR2';cputype:cpu_avr51;fputype:fpu_soft;flashbase:0;flashsize:131072;srambase:512;sramsize:16384;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA1608';controllerunitstr:'ATMEGA1608';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATMEGA1609';controllerunitstr:'ATMEGA1609';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATMEGA2560';controllerunitstr:'ATMEGA2560';cputype:cpu_avr6;fputype:fpu_soft;flashbase:0;flashsize:262144;srambase:512;sramsize:8192;eeprombase:0;eepromsize:4096)
         ,(controllertypestr:'ATMEGA2561';controllerunitstr:'ATMEGA2561';cputype:cpu_avr6;fputype:fpu_soft;flashbase:0;flashsize:262144;srambase:512;sramsize:8192;eeprombase:0;eepromsize:4096)
+        ,(controllertypestr:'ATMEGA2564RFR2';controllerunitstr:'ATMEGA2564RFR2';cputype:cpu_avr6;fputype:fpu_soft;flashbase:0;flashsize:262144;srambase:512;sramsize:32768;eeprombase:0;eepromsize:8192)
         ,(controllertypestr:'ATMEGA3208';controllerunitstr:'ATMEGA3208';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:12288;sramsize:4096;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATMEGA3209';controllerunitstr:'ATMEGA3209';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:12288;sramsize:4096;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATMEGA3250';controllerunitstr:'ATMEGA3250';cputype:cpu_avr5;fputype:fpu_soft;flashbase:0;flashsize:32768;srambase:256;sramsize:2048;eeprombase:0;eepromsize:1024)
@@ -503,6 +532,7 @@ Const
         ,(controllertypestr:'ATTINY416';controllerunitstr:'ATTINY416';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:16128;sramsize:256;eeprombase:5120;eepromsize:128)
         ,(controllertypestr:'ATTINY416AUTO';controllerunitstr:'ATTINY416AUTO';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:16128;sramsize:256;eeprombase:5120;eepromsize:128)
         ,(controllertypestr:'ATTINY417';controllerunitstr:'ATTINY417';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:16128;sramsize:256;eeprombase:5120;eepromsize:128)
+        ,(controllertypestr:'ATTINY441';controllerunitstr:'ATTINY441';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:256;sramsize:256;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATTINY461';controllerunitstr:'ATTINY461';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:96;sramsize:256;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATTINY461A';controllerunitstr:'ATTINY461A';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:4096;srambase:96;sramsize:256;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATTINY804';controllerunitstr:'ATTINY804';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:15872;sramsize:512;eeprombase:5120;eepromsize:128)
@@ -512,6 +542,7 @@ Const
         ,(controllertypestr:'ATTINY816';controllerunitstr:'ATTINY816';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:15872;sramsize:512;eeprombase:5120;eepromsize:128)
         ,(controllertypestr:'ATTINY817';controllerunitstr:'ATTINY817';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:15872;sramsize:512;eeprombase:5120;eepromsize:128)
         ,(controllertypestr:'ATTINY828';controllerunitstr:'ATTINY828';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:512;eeprombase:0;eepromsize:256)
+        ,(controllertypestr:'ATTINY841';controllerunitstr:'ATTINY841';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:256;sramsize:512;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATTINY861';controllerunitstr:'ATTINY861';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:96;sramsize:512;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATTINY861A';controllerunitstr:'ATTINY861A';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:8192;srambase:96;sramsize:512;eeprombase:0;eepromsize:512)
         ,(controllertypestr:'ATTINY1604';controllerunitstr:'ATTINY1604';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:15360;sramsize:1024;eeprombase:5120;eepromsize:256)
@@ -520,6 +551,9 @@ Const
         ,(controllertypestr:'ATTINY1614';controllerunitstr:'ATTINY1614';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATTINY1616';controllerunitstr:'ATTINY1616';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATTINY1617';controllerunitstr:'ATTINY1617';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
+        ,(controllertypestr:'ATTINY1624';controllerunitstr:'ATTINY1624';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
+        ,(controllertypestr:'ATTINY1626';controllerunitstr:'ATTINY1626';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
+        ,(controllertypestr:'ATTINY1627';controllerunitstr:'ATTINY1627';cputype:cpu_avrxmega3;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:14336;sramsize:2048;eeprombase:5120;eepromsize:256)
         ,(controllertypestr:'ATTINY1634';controllerunitstr:'ATTINY1634';cputype:cpu_avr35;fputype:fpu_soft;flashbase:0;flashsize:16384;srambase:256;sramsize:1024;eeprombase:0;eepromsize:256)
         ,(controllertypestr:'ATTINY2313';controllerunitstr:'ATTINY2313';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:2048;srambase:96;sramsize:128;eeprombase:0;eepromsize:128)
         ,(controllertypestr:'ATTINY2313A';controllerunitstr:'ATTINY2313A';cputype:cpu_avr25;fputype:fpu_soft;flashbase:0;flashsize:2048;srambase:96;sramsize:128;eeprombase:0;eepromsize:128)
@@ -534,6 +568,7 @@ Const
         ,(controllertypestr:'ARDUINONANO'; controllerunitstr:'ATMEGA328P'; cputype: cpu_avr5; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:256; sramsize:2048; eeprombase:0; eepromsize:1024)
         ,(controllertypestr:'ARDUINONANOEVERY'; controllerunitstr:'ATMEGA4809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256)
         ,(controllertypestr:'ARDUINOUNO'; controllerunitstr:'ATMEGA328P'; cputype: cpu_avr5; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:256; sramsize:2048; eeprombase:0; eepromsize:1024)
+        ,(controllertypestr:'ATMEGA256RFR2XPRO';controllerunitstr:'ATMEGA256RFR2';cputype:cpu_avr6;fputype:fpu_soft;flashbase:0;flashsize:262144;srambase:512;sramsize:32768;eeprombase:0;eepromsize:8192)
         ,(controllertypestr:'ATMEGA324PBXPRO'; controllerunitstr:'ATMEGA324PB'; cputype: cpu_avr5; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:256; sramsize:2048; eeprombase:0; eepromsize:1024)
         ,(controllertypestr:'ATMEGA1284PXPLAINED'; controllerunitstr:'ATMEGA1284P'; cputype: cpu_avr51; fputype:fpu_soft; flashbase:0; flashsize:131072; srambase:256; sramsize:16384; eeprombase:0; eepromsize:4096)
         ,(controllertypestr:'ATMEGA4809XPRO'; controllerunitstr:'ATMEGA4809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256)

rtl/embedded/Makefile

@@ -396,8 +396,8 @@ endif
 ifeq ($(SUBARCH),avr25)
 CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny28 attiny43u \
           attiny44 attiny44a attiny45 attiny48 attiny84a attiny84 attiny85 \
-          attiny87 attiny88 attiny261 attiny261a attiny461 attiny461a attiny828 \
-          attiny861 attiny861a attiny2313 attiny2313a attiny4313
+          attiny87 attiny88 attiny261 attiny261a attiny441 attiny461 attiny461a attiny828 \
+          attiny841 attiny861 attiny861a attiny2313 attiny2313a attiny4313
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr35)
@@ -406,33 +406,34 @@ CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr4)
 CPU_UNITS=at90pwm1 at90pwm2b at90pwm3b at90pwm81 ata6285 ata6286 atmega8 \
-          atmega8a atmega48 atmega48a atmega48p atmega48pa atmega48pb atmega88 atmega88a \
-          atmega88p atmega88pa atmega88pb atmega8515 atmega8535
+          atmega8a atmega8hva atmega48 atmega48a atmega48p atmega48pa \
+          atmega48pb atmega88 atmega88a atmega88p atmega88pa atmega88pb \
+          atmega8515 atmega8535
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr5)
 CPU_UNITS=avrsim at90can32 at90can64 at90pwm161 at90pwm216 at90pwm316 \
-          at90usb646 at90usb647 atmega16 atmega16a atmega16hvb atmega16m1 \
-          atmega16u4 atmega32 atmega32a atmega32c1 atmega32hvb atmega32m1 \
-          atmega32u4 atmega64 atmega64a atmega64c1 atmega64m1 atmega162 \
+          at90usb646 at90usb647 atmega16 atmega16a atmega16hva atmega16hvb atmega16hvbrevb atmega16m1 \
+          atmega16u4 atmega32 atmega32a atmega32c1 atmega32hvb atmega32hvbrevb atmega32m1 \
+          atmega32u4 atmega64 atmega64a atmega64c1 atmega64hve2 atmega64m1 atmega64rfr2 atmega162 \
           atmega164a atmega164p atmega164pa atmega165a atmega165p atmega165pa \
           atmega168 atmega168a atmega168p atmega168pa atmega168pb atmega169a atmega169p \
           atmega169pa atmega324a atmega324p atmega324pa atmega324pb atmega325 atmega325a \
           atmega325p atmega325pa atmega328 atmega328p atmega328pb atmega329 atmega329a \
-          atmega329p atmega329pa atmega640 atmega644 atmega644a atmega644p \
-          atmega644pa atmega645 atmega645a atmega645p atmega649 atmega649a \
+          atmega329p atmega329pa atmega406 atmega640 atmega644 atmega644a atmega644p \
+          atmega644pa atmega644rfr2 atmega645 atmega645a atmega645p atmega649 atmega649a \
           atmega649p atmega3250 atmega3250a atmega3250p atmega3250pa atmega3290 \
           atmega3290a atmega3290p atmega3290pa atmega6450 atmega6450a \
           atmega6450p atmega6490 atmega6490a atmega6490p
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr51)
-CPU_UNITS=at90can128 at90usb1286 at90usb1287 atmega128 atmega128a atmega128rfa1 \
-          atmega1280 atmega1281 atmega1284 atmega1284p
+CPU_UNITS=at90can128 at90usb1286 at90usb1287 atmega128 atmega128a atmega128rfa1 atmega128rfr2 \
+          atmega1280 atmega1281 atmega1284 atmega1284p atmega1284rfr2
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr6)
-CPU_UNITS=avrsim atmega2560 atmega2561
+CPU_UNITS=avrsim atmega256rfr2 atmega2560 atmega2561 atmega2564rfr2
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avrxmega3)
@@ -441,7 +442,7 @@ CPU_UNITS=atmega808 atmega809 atmega1608 atmega1609 atmega3208 atmega3209 \
           attiny402 attiny404 attiny406 attiny412 attiny414 attiny416 \
           attiny416auto attiny417 attiny804 attiny806 attiny807 attiny814 \
           attiny816 attiny817 attiny1604 attiny1606 attiny1607 attiny1614 \
-          attiny1616 attiny1617 attiny3214 attiny3216 attiny3217
+          attiny1616 attiny1617 attiny1624 attiny1626 attiny1627 attiny3214 attiny3216 attiny3217
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(CPU_UNITS_DEFINED),)

rtl/embedded/Makefile.fpc

@@ -112,8 +112,8 @@ endif
 ifeq ($(SUBARCH),avr25)
 CPU_UNITS=attiny13 attiny13a attiny24 attiny24a attiny25 attiny28 attiny43u \
           attiny44 attiny44a attiny45 attiny48 attiny84a attiny84 attiny85 \
-          attiny87 attiny88 attiny261 attiny261a attiny461 attiny461a attiny828 \
-          attiny861 attiny861a attiny2313 attiny2313a attiny4313
+          attiny87 attiny88 attiny261 attiny261a attiny441 attiny461 attiny461a attiny828 \
+          attiny841 attiny861 attiny861a attiny2313 attiny2313a attiny4313
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr35)
@@ -122,33 +122,34 @@ CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr4)
 CPU_UNITS=at90pwm1 at90pwm2b at90pwm3b at90pwm81 ata6285 ata6286 atmega8 \
-          atmega8a atmega48 atmega48a atmega48p atmega48pa atmega48pb atmega88 atmega88a \
-          atmega88p atmega88pa atmega88pb atmega8515 atmega8535
+          atmega8a atmega8hva atmega48 atmega48a atmega48p atmega48pa \
+          atmega48pb atmega88 atmega88a atmega88p atmega88pa atmega88pb \
+          atmega8515 atmega8535
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr5)
 CPU_UNITS=avrsim at90can32 at90can64 at90pwm161 at90pwm216 at90pwm316 \
-          at90usb646 at90usb647 atmega16 atmega16a atmega16hvb atmega16m1 \
-          atmega16u4 atmega32 atmega32a atmega32c1 atmega32hvb atmega32m1 \
-          atmega32u4 atmega64 atmega64a atmega64c1 atmega64m1 atmega162 \
+          at90usb646 at90usb647 atmega16 atmega16a atmega16hva atmega16hvb atmega16hvbrevb atmega16m1 \
+          atmega16u4 atmega32 atmega32a atmega32c1 atmega32hvb atmega32hvbrevb atmega32m1 \
+          atmega32u4 atmega64 atmega64a atmega64c1 atmega64hve2 atmega64m1 atmega64rfr2 atmega162 \
           atmega164a atmega164p atmega164pa atmega165a atmega165p atmega165pa \
           atmega168 atmega168a atmega168p atmega168pa atmega168pb atmega169a atmega169p \
           atmega169pa atmega324a atmega324p atmega324pa atmega324pb atmega325 atmega325a \
           atmega325p atmega325pa atmega328 atmega328p atmega328pb atmega329 atmega329a \
-          atmega329p atmega329pa atmega640 atmega644 atmega644a atmega644p \
-          atmega644pa atmega645 atmega645a atmega645p atmega649 atmega649a \
+          atmega329p atmega329pa atmega406 atmega640 atmega644 atmega644a atmega644p \
+          atmega644pa atmega644rfr2 atmega645 atmega645a atmega645p atmega649 atmega649a \
           atmega649p atmega3250 atmega3250a atmega3250p atmega3250pa atmega3290 \
           atmega3290a atmega3290p atmega3290pa atmega6450 atmega6450a \
           atmega6450p atmega6490 atmega6490a atmega6490p
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr51)
-CPU_UNITS=at90can128 at90usb1286 at90usb1287 atmega128 atmega128a atmega128rfa1 \
-          atmega1280 atmega1281 atmega1284 atmega1284p
+CPU_UNITS=at90can128 at90usb1286 at90usb1287 atmega128 atmega128a atmega128rfa1 atmega128rfr2 \
+          atmega1280 atmega1281 atmega1284 atmega1284p atmega1284rfr2
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avr6)
-CPU_UNITS=avrsim atmega2560 atmega2561
+CPU_UNITS=avrsim atmega256rfr2 atmega2560 atmega2561 atmega2564rfr2
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(SUBARCH),avrxmega3)
@@ -157,7 +158,7 @@ CPU_UNITS=atmega808 atmega809 atmega1608 atmega1609 atmega3208 atmega3209 \
           attiny402 attiny404 attiny406 attiny412 attiny414 attiny416 \
           attiny416auto attiny417 attiny804 attiny806 attiny807 attiny814 \
           attiny816 attiny817 attiny1604 attiny1606 attiny1607 attiny1614 \
-          attiny1616 attiny1617 attiny3214 attiny3216 attiny3217
+          attiny1616 attiny1617 attiny1624 attiny1626 attiny1627 attiny3214 attiny3216 attiny3217
 CPU_UNITS_DEFINED=1
 endif
 ifeq ($(CPU_UNITS_DEFINED),)

rtl/embedded/avr/atmega1284rfr2.pp

@@ -0,0 +1,2093 @@
+unit ATmega1284RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  RAMPZ: byte absolute $5B;  // Extended Z-pointer Register for ELPM/SPM
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Extended Z-pointer Register for ELPM/SPM
+  RAMPZ0 = $00;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  Res = $00;  
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega128rfr2.pp

@@ -0,0 +1,2101 @@
+unit ATmega128RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  RAMPZ: byte absolute $5B;  // Extended Z-pointer Register for ELPM/SPM
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Extended Z-pointer Register for ELPM/SPM
+  RAMPZ0 = $00;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  OSCCAL0 = $00;  // Oscillator Calibration 
+  OSCCAL1 = $01;  // Oscillator Calibration 
+  OSCCAL2 = $02;  // Oscillator Calibration 
+  OSCCAL3 = $03;  // Oscillator Calibration 
+  OSCCAL4 = $04;  // Oscillator Calibration 
+  OSCCAL5 = $05;  // Oscillator Calibration 
+  OSCCAL6 = $06;  // Oscillator Calibration 
+  OSCCAL7 = $07;  // Oscillator Calibration 
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  Res = $00;  
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega16hva.pp

@@ -0,0 +1,413 @@
+unit ATmega16HVA;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Input Pins, Port B
+  DDRB: byte absolute $24;  // Data Direction Register, Port B
+  PORTB: byte absolute $25;  // Data Register, Port B
+  PINC: byte absolute $26;  // Port C Input Pins
+  PORTC: byte absolute $28;  // Port C Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  OSICSR: byte absolute $37;  // Oscillator Sampling Interface Control and Status Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: byte absolute $41;  // EEPROM Read/Write Access
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register
+  TCNT0: word absolute $46;  // Timer Counter 0  Bytes
+  TCNT0L: byte absolute $46;  // Timer Counter 0  Bytes
+  TCNT0H: byte absolute $47;  // Timer Counter 0  Bytes;
+  OCR0A: byte absolute $48;  // Output compare Register A
+  OCR0B: byte absolute $49;  // Output compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  FOSCCAL: byte absolute $66;  // Fast Oscillator Calibration Value
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  VADC: word absolute $78;  // VADC Data Register  Bytes
+  VADCL: byte absolute $78;  // VADC Data Register  Bytes
+  VADCH: byte absolute $79;  // VADC Data Register  Bytes;
+  VADCSR: byte absolute $7A;  // The VADC Control and Status register
+  VADMUX: byte absolute $7C;  // The VADC multiplexer Selection Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1A: byte absolute $80;  // Timer/Counter 1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1  Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1  Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1  Bytes;
+  OCR1A: byte absolute $88;  // Output Compare Register 1A
+  OCR1B: byte absolute $89;  // Output Compare Register B
+  ROCR: byte absolute $C8;  // Regulator Operating Condition Register
+  BGCCR: byte absolute $D0;  // Bandgap Calibration Register
+  BGCRR: byte absolute $D1;  // Bandgap Calibration of Resistor Ladder
+  CADAC0: byte absolute $E0;  // ADC Accumulate Current
+  CADAC1: byte absolute $E1;  // ADC Accumulate Current
+  CADAC2: byte absolute $E2;  // ADC Accumulate Current
+  CADAC3: byte absolute $E3;  // ADC Accumulate Current
+  CADCSRA: byte absolute $E4;  // CC-ADC Control and Status Register A
+  CADCSRB: byte absolute $E5;  // CC-ADC Control and Status Register B
+  CADRC: byte absolute $E6;  // CC-ADC Regular Current
+  CADIC: word absolute $E8;  // CC-ADC Instantaneous Current
+  CADICL: byte absolute $E8;  // CC-ADC Instantaneous Current
+  CADICH: byte absolute $E9;  // CC-ADC Instantaneous Current;
+  FCSR: byte absolute $F0;  // FET Control and Status Register
+  BPIMSK: byte absolute $F2;  // Battery Protection Interrupt Mask Register
+  BPIFR: byte absolute $F3;  // Battery Protection Interrupt Flag Register
+  BPSCD: byte absolute $F5;  // Battery Protection Short-Circuit Detection Level Register
+  BPDOCD: byte absolute $F6;  // Battery Protection Discharge-Over-current Detection Level Register
+  BPCOCD: byte absolute $F7;  // Battery Protection Charge-Over-current Detection Level Register
+  BPDHCD: byte absolute $F8;  // Battery Protection Discharge-High-current Detection Level Register
+  BPCHCD: byte absolute $F9;  // Battery Protection Charge-High-current Detection Level Register
+  BPSCTR: byte absolute $FA;  // Battery Protection Short-current Timing Register
+  BPOCTR: byte absolute $FB;  // Battery Protection Over-current Timing Register
+  BPHCTR: byte absolute $FC;  // Battery Protection Short-current Timing Register
+  BPCR: byte absolute $FD;  // Battery Protection Control Register
+  BPPLR: byte absolute $FE;  // Battery Protection Parameter Lock Register
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  // Data Register, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  // Port C Data Register
+  PC0 = $00;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  ICF0 = $03;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $03;  
+  // Oscillator Sampling Interface Control and Status Register
+  OSIEN = $00;  
+  OSIST = $01;  
+  OSISEL0 = $04;  
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flags
+  INTF1 = $01;  // External Interrupt Flags
+  INTF2 = $02;  // External Interrupt Flags
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request 2 Enable
+  INT1 = $01;  // External Interrupt Request 2 Enable
+  INT2 = $02;  // External Interrupt Request 2 Enable
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;
+  EEPM1 = $05;
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register
+  WGM00 = $00;  
+  ICS0 = $03;  
+  ICES0 = $04;  
+  ICNC0 = $05;  
+  ICEN0 = $06;  
+  TCW0 = $07;  
+  // Timer/Counter0 Control Register
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  OCDRF = $04;  
+  // MCU Control Register
+  PUD = $04;  
+  CKOE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  RFLB = $03;  
+  CTPB = $04;  
+  SIGRD = $05;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 0
+  PRVADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRSPI = $03;  
+  PRVRM = $05;  
+  // External Interrupt Control Register
+  ISC00 = $00;  // External Interrupt Sense Control 0 Bits
+  ISC01 = $01;  // External Interrupt Sense Control 0 Bits
+  ISC10 = $02;  // External Interrupt Sense Control 1 Bits
+  ISC11 = $03;  // External Interrupt Sense Control 1 Bits
+  ISC20 = $04;  // External Interrupt Sense Control 2 Bits
+  ISC21 = $05;  // External Interrupt Sense Control 2 Bits
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  ICIE0 = $03;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $03;  
+  // The VADC Control and Status register
+  VADCCIE = $00;  
+  VADCCIF = $01;  
+  VADSC = $02;  
+  VADEN = $03;  
+  // The VADC multiplexer Selection Register
+  VADMUX0 = $00;  // Analog Channel and Gain Selection Bits
+  VADMUX1 = $01;  // Analog Channel and Gain Selection Bits
+  VADMUX2 = $02;  // Analog Channel and Gain Selection Bits
+  VADMUX3 = $03;  // Analog Channel and Gain Selection Bits
+  // Digital Input Disable Register
+  PA0DID = $00;  
+  PA1DID = $01;  
+  // Timer/Counter 1 Control Register A
+  WGM10 = $00;  
+  ICS1 = $03;  
+  ICES1 = $04;  
+  ICNC1 = $05;  
+  ICEN1 = $06;  
+  TCW1 = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bis
+  CS11 = $01;  // Clock Select1 bis
+  CS12 = $02;  // Clock Select1 bis
+  // Regulator Operating Condition Register
+  ROCWIE = $00;  
+  ROCWIF = $01;  
+  ROCS = $07;  
+  // Bandgap Calibration Register
+  BGCC0 = $00;  // BG Calibration of PTAT Current Bits
+  BGCC1 = $01;  // BG Calibration of PTAT Current Bits
+  BGCC2 = $02;  // BG Calibration of PTAT Current Bits
+  BGCC3 = $03;  // BG Calibration of PTAT Current Bits
+  BGCC4 = $04;  // BG Calibration of PTAT Current Bits
+  BGCC5 = $05;  // BG Calibration of PTAT Current Bits
+  BGD = $07;  
+  // Bandgap Calibration of Resistor Ladder
+  BGCR0 = $00;  // Bandgap calibration bits
+  BGCR1 = $01;  // Bandgap calibration bits
+  BGCR2 = $02;  // Bandgap calibration bits
+  BGCR3 = $03;  // Bandgap calibration bits
+  BGCR4 = $04;  // Bandgap calibration bits
+  BGCR5 = $05;  // Bandgap calibration bits
+  BGCR6 = $06;  // Bandgap calibration bits
+  BGCR7 = $07;  // Bandgap calibration bits
+  // CC-ADC Control and Status Register A
+  CADSE = $00;  
+  CADSI0 = $01;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADSI1 = $02;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADAS0 = $03;  // CC_ADC Accumulate Current Select Bits
+  CADAS1 = $04;  // CC_ADC Accumulate Current Select Bits
+  CADUB = $05;  
+  CADPOL = $06;  
+  CADEN = $07;  
+  // CC-ADC Control and Status Register B
+  CADICIF = $00;  
+  CADRCIF = $01;  
+  CADACIF = $02;  
+  CADICIE = $04;  
+  CADRCIE = $05;  
+  CADACIE = $06;  
+  // FET Control and Status Register
+  CFE = $00;  
+  DFE = $01;  
+  CPS = $02;  
+  DUVRD = $03;  
+  // Battery Protection Interrupt Mask Register
+  CHCIE = $00;  
+  DHCIE = $01;  
+  COCIE = $02;  
+  DOCIE = $03;  
+  SCIE = $04;  
+  // Battery Protection Interrupt Flag Register
+  CHCIF = $00;  
+  DHCIF = $01;  
+  COCIF = $02;  
+  DOCIF = $03;  
+  SCIF = $04;  
+  // Battery Protection Control Register
+  CHCD = $00;  
+  DHCD = $01;  
+  COCD = $02;  
+  DOCD = $03;  
+  SCD = $04;  
+  // Battery Protection Parameter Lock Register
+  BPPL = $00;  
+  BPPLE = $01;  
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
+procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 6 Watchdog Timeout Interrupt
+procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 7 Timer 1 Input capture
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 8 Timer 1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 9 Timer 1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 10 Timer 1 overflow
+procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 11 Timer 0 Input Capture
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 12 Timer 0 Comapre Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 13 Timer 0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 14 Timer 0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 15 SPI Serial transfer complete
+procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 16 Voltage ADC Conversion Complete
+procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 17 Coulomb Counter ADC Conversion Complete
+procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 18 Coloumb Counter ADC Regular Current
+procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 19 Coloumb Counter ADC Accumulator
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 20 EEPROM Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp BPINT_ISR
+  jmp VREGMON_ISR
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp WDT_ISR
+  jmp TIMER1_IC_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_IC_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp VADC_ISR
+  jmp CCADC_CONV_ISR
+  jmp CCADC_REG_CUR_ISR
+  jmp CCADC_ACC_ISR
+  jmp EE_READY_ISR
+
+  {$i start.inc}
+
+  .weak BPINT_ISR
+  .weak VREGMON_ISR
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak WDT_ISR
+  .weak TIMER1_IC_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_IC_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak VADC_ISR
+  .weak CCADC_CONV_ISR
+  .weak CCADC_REG_CUR_ISR
+  .weak CCADC_ACC_ISR
+  .weak EE_READY_ISR
+
+  .set BPINT_ISR, Default_IRQ_handler
+  .set VREGMON_ISR, Default_IRQ_handler
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER1_IC_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_IC_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set VADC_ISR, Default_IRQ_handler
+  .set CCADC_CONV_ISR, Default_IRQ_handler
+  .set CCADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CCADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega16hvbrevb.pp

@@ -0,0 +1,806 @@
+unit ATmega16HVBrevB;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins
+  PORTC: byte absolute $28;  // Port C Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  OSICSR: byte absolute $37;  // Oscillator Sampling Interface Control and Status Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Read/Write Access
+  EEARL: byte absolute $41;  // EEPROM Read/Write Access
+  EEARH: byte absolute $42;  // EEPROM Read/Write Access;
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter 0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: word absolute $46;  // Timer Counter 0 Bytes
+  TCNT0L: byte absolute $46;  // Timer Counter 0 Bytes
+  TCNT0H: byte absolute $47;  // Timer Counter 0 Bytes;
+  OCR0A: byte absolute $48;  // Output Compare Register 0A
+  OCR0B: byte absolute $49;  // Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  FOSCCAL: byte absolute $66;  // Fast Oscillator Calibration Value
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  PCMSK0: byte absolute $6B;  // Pin Change Enable Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Enable Mask Register 1
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  VADC: word absolute $78;  // VADC Data Register Bytes
+  VADCL: byte absolute $78;  // VADC Data Register Bytes
+  VADCH: byte absolute $79;  // VADC Data Register Bytes;
+  VADCSR: byte absolute $7A;  // The VADC Control and Status register
+  VADMUX: byte absolute $7C;  // The VADC multiplexer Selection Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1A: byte absolute $80;  // Timer/Counter 1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1 Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1 Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1 Bytes;
+  OCR1A: byte absolute $88;  // Output Compare Register 1A
+  OCR1B: byte absolute $89;  // Output Compare Register B
+  TWBR: byte absolute $B8;  // TWI Bit Rate register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address register
+  TWDR: byte absolute $BB;  // TWI Data register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  TWBCSR: byte absolute $BE;  // TWI Bus Control and Status Register
+  ROCR: byte absolute $C8;  // Regulator Operating Condition Register
+  BGCCR: byte absolute $D0;  // Bandgap Calibration Register
+  BGCRR: byte absolute $D1;  // Bandgap Calibration of Resistor Ladder
+  BGCSR: byte absolute $D2;  // Bandgap Control and Status Register
+  CHGDCSR: byte absolute $D4;  // Charger Detect Control and Status Register
+  CADAC0: byte absolute $E0;  // ADC Accumulate Current
+  CADAC1: byte absolute $E1;  // ADC Accumulate Current
+  CADAC2: byte absolute $E2;  // ADC Accumulate Current
+  CADAC3: byte absolute $E3;  // ADC Accumulate Current
+  CADIC: word absolute $E4;  // CC-ADC Instantaneous Current
+  CADICL: byte absolute $E4;  // CC-ADC Instantaneous Current
+  CADICH: byte absolute $E5;  // CC-ADC Instantaneous Current;
+  CADCSRA: byte absolute $E6;  // CC-ADC Control and Status Register A
+  CADCSRB: byte absolute $E7;  // CC-ADC Control and Status Register B
+  CADCSRC: byte absolute $E8;  // CC-ADC Control and Status Register C
+  CADRCC: byte absolute $E9;  // CC-ADC Regular Charge Current
+  CADRDC: byte absolute $EA;  // CC-ADC Regular Discharge Current
+  FCSR: byte absolute $F0;  // FET Control and Status Register
+  CBCR: byte absolute $F1;  // Cell Balancing Control Register
+  BPIMSK: byte absolute $F2;  // Battery Protection Interrupt Mask Register
+  BPIFR: byte absolute $F3;  // Battery Protection Interrupt Flag Register
+  BPSCD: byte absolute $F5;  // Battery Protection Short-Circuit Detection Level Register
+  BPDOCD: byte absolute $F6;  // Battery Protection Discharge-Over-current Detection Level Register
+  BPCOCD: byte absolute $F7;  // Battery Protection Charge-Over-current Detection Level Register
+  BPDHCD: byte absolute $F8;  // Battery Protection Discharge-High-current Detection Level Register
+  BPCHCD: byte absolute $F9;  // Battery Protection Charge-High-current Detection Level Register
+  BPSCTR: byte absolute $FA;  // Battery Protection Short-current Timing Register
+  BPOCTR: byte absolute $FB;  // Battery Protection Over-current Timing Register
+  BPHCTR: byte absolute $FC;  // Battery Protection Short-current Timing Register
+  BPCR: byte absolute $FD;  // Battery Protection Control Register
+  BPPLR: byte absolute $FE;  // Battery Protection Parameter Lock Register
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  ICF0 = $03;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $03;  
+  // Oscillator Sampling Interface Control and Status Register
+  OSIEN = $00;  
+  OSIST = $01;  
+  OSISEL0 = $04;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flags
+  INTF1 = $01;  // External Interrupt Flags
+  INTF2 = $02;  // External Interrupt Flags
+  INTF3 = $03;  // External Interrupt Flags
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request 3 Enable
+  INT1 = $01;  // External Interrupt Request 3 Enable
+  INT2 = $02;  // External Interrupt Request 3 Enable
+  INT3 = $03;  // External Interrupt Request 3 Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  // General Purpose IO bits
+  GPIOR01 = $01;  // General Purpose IO bits
+  GPIOR02 = $02;  // General Purpose IO bits
+  GPIOR03 = $03;  // General Purpose IO bits
+  GPIOR04 = $04;  // General Purpose IO bits
+  GPIOR05 = $05;  // General Purpose IO bits
+  GPIOR06 = $06;  // General Purpose IO bits
+  GPIOR07 = $07;  // General Purpose IO bits
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;
+  EEPM1 = $05;
+  // EEPROM Data Register
+  EEDR0 = $00;  // EEPROM Data bits
+  EEDR1 = $01;  // EEPROM Data bits
+  EEDR2 = $02;  // EEPROM Data bits
+  EEDR3 = $03;  // EEPROM Data bits
+  EEDR4 = $04;  // EEPROM Data bits
+  EEDR5 = $05;  // EEPROM Data bits
+  EEDR6 = $06;  // EEPROM Data bits
+  EEDR7 = $07;  // EEPROM Data bits
+  // EEPROM Read/Write Access
+  EEAR0 = $00;  // EEPROM Address bits
+  EEAR1 = $01;  // EEPROM Address bits
+  EEAR2 = $02;  // EEPROM Address bits
+  EEAR3 = $03;  // EEPROM Address bits
+  EEAR4 = $04;  // EEPROM Address bits
+  EEAR5 = $05;  // EEPROM Address bits
+  EEAR6 = $06;  // EEPROM Address bits
+  EEAR7 = $07;  // EEPROM Address bits
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter 0 Control Register A
+  WGM00 = $00;  
+  ICS0 = $03;  
+  ICES0 = $04;  
+  ICNC0 = $05;  
+  ICEN0 = $06;  
+  TCW0 = $07;  
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // Timer Counter 0 Bytes
+  TCNT00 = $00;  // Timer Counter 0 bits
+  TCNT01 = $01;  // Timer Counter 0 bits
+  TCNT02 = $02;  // Timer Counter 0 bits
+  TCNT03 = $03;  // Timer Counter 0 bits
+  TCNT04 = $04;  // Timer Counter 0 bits
+  TCNT05 = $05;  // Timer Counter 0 bits
+  TCNT06 = $06;  // Timer Counter 0 bits
+  TCNT07 = $07;  // Timer Counter 0 bits
+  // Output Compare Register 0A
+  OCR0A0 = $00;  // Output Compare 0 A bits
+  OCR0A1 = $01;  // Output Compare 0 A bits
+  OCR0A2 = $02;  // Output Compare 0 A bits
+  OCR0A3 = $03;  // Output Compare 0 A bits
+  OCR0A4 = $04;  // Output Compare 0 A bits
+  OCR0A5 = $05;  // Output Compare 0 A bits
+  OCR0A6 = $06;  // Output Compare 0 A bits
+  OCR0A7 = $07;  // Output Compare 0 A bits
+  // Output Compare Register B
+  OCR0B0 = $00;  // Output Compare 0 B bits
+  OCR0B1 = $01;  // Output Compare 0 B bits
+  OCR0B2 = $02;  // Output Compare 0 B bits
+  OCR0B3 = $03;  // Output Compare 0 B bits
+  OCR0B4 = $04;  // Output Compare 0 B bits
+  OCR0B5 = $05;  // Output Compare 0 B bits
+  OCR0B6 = $06;  // Output Compare 0 B bits
+  OCR0B7 = $07;  // Output Compare 0 B bits
+  // General Purpose IO Register 1
+  GPIOR10 = $00;  // General Purpose IO bits
+  GPIOR11 = $01;  // General Purpose IO bits
+  GPIOR12 = $02;  // General Purpose IO bits
+  GPIOR13 = $03;  // General Purpose IO bits
+  GPIOR14 = $04;  // General Purpose IO bits
+  GPIOR15 = $05;  // General Purpose IO bits
+  GPIOR16 = $06;  // General Purpose IO bits
+  GPIOR17 = $07;  // General Purpose IO bits
+  // General Purpose IO Register 2
+  GPIOR20 = $00;  // General Purpose IO bits
+  GPIOR21 = $01;  // General Purpose IO bits
+  GPIOR22 = $02;  // General Purpose IO bits
+  GPIOR23 = $03;  // General Purpose IO bits
+  GPIOR24 = $04;  // General Purpose IO bits
+  GPIOR25 = $05;  // General Purpose IO bits
+  GPIOR26 = $06;  // General Purpose IO bits
+  GPIOR27 = $07;  // General Purpose IO bits
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // SPI Data Register
+  SPDR0 = $00;  // SPI Data bits
+  SPDR1 = $01;  // SPI Data bits
+  SPDR2 = $02;  // SPI Data bits
+  SPDR3 = $03;  // SPI Data bits
+  SPDR4 = $04;  // SPI Data bits
+  SPDR5 = $05;  // SPI Data bits
+  SPDR6 = $06;  // SPI Data bits
+  SPDR7 = $07;  // SPI Data bits
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  OCDRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  CKOE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  LBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 0
+  PRVADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRSPI = $03;  
+  PRVRM = $05;  
+  PRTWI = $06;  
+  // Fast Oscillator Calibration Value
+  FCAL0 = $00;  // Fast Oscillator Calibration Value
+  FCAL1 = $01;  // Fast Oscillator Calibration Value
+  FCAL2 = $02;  // Fast Oscillator Calibration Value
+  FCAL3 = $03;  // Fast Oscillator Calibration Value
+  FCAL4 = $04;  // Fast Oscillator Calibration Value
+  FCAL5 = $05;  // Fast Oscillator Calibration Value
+  FCAL6 = $06;  // Fast Oscillator Calibration Value
+  FCAL7 = $07;  // Fast Oscillator Calibration Value
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register
+  ISC00 = $00;  // External Interrupt Sense Control 0 Bits
+  ISC01 = $01;  // External Interrupt Sense Control 0 Bits
+  ISC10 = $02;  // External Interrupt Sense Control 1 Bits
+  ISC11 = $03;  // External Interrupt Sense Control 1 Bits
+  ISC20 = $04;  // External Interrupt Sense Control 2 Bits
+  ISC21 = $05;  // External Interrupt Sense Control 2 Bits
+  ISC30 = $06;  // External Interrupt Sense Control 3 Bits
+  ISC31 = $07;  // External Interrupt Sense Control 3 Bits
+  // Pin Change Enable Mask Register 1
+  PCINT4 = $00;  // Pin Change Enable Mask
+  PCINT5 = $01;  // Pin Change Enable Mask
+  PCINT6 = $02;  // Pin Change Enable Mask
+  PCINT7 = $03;  // Pin Change Enable Mask
+  PCINT8 = $04;  // Pin Change Enable Mask
+  PCINT9 = $05;  // Pin Change Enable Mask
+  PCINT10 = $06;  // Pin Change Enable Mask
+  PCINT11 = $07;  // Pin Change Enable Mask
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  ICIE0 = $03;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $03;  
+  // VADC Data Register Bytes
+  VADC0 = $00;  // VADC Data bits
+  VADC1 = $01;  // VADC Data bits
+  VADC2 = $02;  // VADC Data bits
+  VADC3 = $03;  // VADC Data bits
+  VADC4 = $04;  // VADC Data bits
+  VADC5 = $05;  // VADC Data bits
+  VADC6 = $06;  // VADC Data bits
+  VADC7 = $07;  // VADC Data bits
+  // The VADC Control and Status register
+  VADCCIE = $00;  
+  VADCCIF = $01;  
+  VADSC = $02;  
+  VADEN = $03;  
+  // The VADC multiplexer Selection Register
+  VADMUX0 = $00;  // Analog Channel and Gain Selection Bits
+  VADMUX1 = $01;  // Analog Channel and Gain Selection Bits
+  VADMUX2 = $02;  // Analog Channel and Gain Selection Bits
+  VADMUX3 = $03;  // Analog Channel and Gain Selection Bits
+  // Digital Input Disable Register
+  PA0DID = $00;  
+  PA1DID = $01;  
+  // Timer/Counter 1 Control Register A
+  WGM10 = $00;  
+  ICS1 = $03;  
+  ICES1 = $04;  
+  ICNC1 = $05;  
+  ICEN1 = $06;  
+  TCW1 = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bis
+  CS11 = $01;  // Clock Select1 bis
+  CS12 = $02;  // Clock Select1 bis
+  // Timer Counter 1 Bytes
+  TCNT10 = $00;  // Timer Counter 1 bits
+  TCNT11 = $01;  // Timer Counter 1 bits
+  TCNT12 = $02;  // Timer Counter 1 bits
+  TCNT13 = $03;  // Timer Counter 1 bits
+  TCNT14 = $04;  // Timer Counter 1 bits
+  TCNT15 = $05;  // Timer Counter 1 bits
+  TCNT16 = $06;  // Timer Counter 1 bits
+  TCNT17 = $07;  // Timer Counter 1 bits
+  // Output Compare Register 1A
+  OCR1A0 = $00;  // Output Compare 1 A bits
+  OCR1A1 = $01;  // Output Compare 1 A bits
+  OCR1A2 = $02;  // Output Compare 1 A bits
+  OCR1A3 = $03;  // Output Compare 1 A bits
+  OCR1A4 = $04;  // Output Compare 1 A bits
+  OCR1A5 = $05;  // Output Compare 1 A bits
+  OCR1A6 = $06;  // Output Compare 1 A bits
+  OCR1A7 = $07;  // Output Compare 1 A bits
+  // Output Compare Register B
+  OCR1B0 = $00;  // Output Compare 1 B bits
+  OCR1B1 = $01;  // Output Compare 1 B bits
+  OCR1B2 = $02;  // Output Compare 1 B bits
+  OCR1B3 = $03;  // Output Compare 1 B bits
+  OCR1B4 = $04;  // Output Compare 1 B bits
+  OCR1B5 = $05;  // Output Compare 1 B bits
+  OCR1B6 = $06;  // Output Compare 1 B bits
+  OCR1B7 = $07;  // Output Compare 1 B bits
+  // TWI Bit Rate register
+  TWBR0 = $00;  // TWI Bit Rate bits
+  TWBR1 = $01;  // TWI Bit Rate bits
+  TWBR2 = $02;  // TWI Bit Rate bits
+  TWBR3 = $03;  // TWI Bit Rate bits
+  TWBR4 = $04;  // TWI Bit Rate bits
+  TWBR5 = $05;  // TWI Bit Rate bits
+  TWBR6 = $06;  // TWI Bit Rate bits
+  TWBR7 = $07;  // TWI Bit Rate bits
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler
+  TWPS1 = $01;  // TWI Prescaler
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address register Bits
+  TWA1 = $02;  // TWI (Slave) Address register Bits
+  TWA2 = $03;  // TWI (Slave) Address register Bits
+  TWA3 = $04;  // TWI (Slave) Address register Bits
+  TWA4 = $05;  // TWI (Slave) Address register Bits
+  TWA5 = $06;  // TWI (Slave) Address register Bits
+  TWA6 = $07;  // TWI (Slave) Address register Bits
+  // TWI Data register
+  TWD0 = $00;  // TWI Data Bits
+  TWD1 = $01;  // TWI Data Bits
+  TWD2 = $02;  // TWI Data Bits
+  TWD3 = $03;  // TWI Data Bits
+  TWD4 = $04;  // TWI Data Bits
+  TWD5 = $05;  // TWI Data Bits
+  TWD6 = $06;  // TWI Data Bits
+  TWD7 = $07;  // TWI Data Bits
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  TWAM0 = $01;
+  TWAM1 = $02;
+  TWAM2 = $03;
+  TWAM3 = $04;
+  TWAM4 = $05;
+  TWAM5 = $06;
+  TWAM6 = $07;
+  // TWI Bus Control and Status Register
+  TWBCIP = $00;  
+  TWBDT0 = $01;  // TWI Bus Disconnect Time-out Period
+  TWBDT1 = $02;  // TWI Bus Disconnect Time-out Period
+  TWBCIE = $06;  
+  TWBCIF = $07;  
+  // Regulator Operating Condition Register
+  ROCWIE = $00;  
+  ROCWIF = $01;  
+  ROCD = $04;  
+  ROCS = $07;  
+  // Bandgap Calibration Register
+  BGCC0 = $00;  // BG Calibration of PTAT Current Bits
+  BGCC1 = $01;  // BG Calibration of PTAT Current Bits
+  BGCC2 = $02;  // BG Calibration of PTAT Current Bits
+  BGCC3 = $03;  // BG Calibration of PTAT Current Bits
+  BGCC4 = $04;  // BG Calibration of PTAT Current Bits
+  BGCC5 = $05;  // BG Calibration of PTAT Current Bits
+  // Bandgap Calibration of Resistor Ladder
+  BGCR0 = $00;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR1 = $01;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR2 = $02;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR3 = $03;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR4 = $04;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR5 = $05;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR6 = $06;  // Bandgap Calibration of Resistor Ladder Bits
+  BGCR7 = $07;  // Bandgap Calibration of Resistor Ladder Bits
+  // Bandgap Control and Status Register
+  BGSCDIE = $00;  
+  BGSCDIF = $01;  
+  BGSCDE = $04;  
+  BGD = $05;  
+  // Charger Detect Control and Status Register
+  CHGDIE = $00;  
+  CHGDIF = $01;  
+  CHGDISC0 = $02;  // Charger Detect Interrupt Sense Control
+  CHGDISC1 = $03;  // Charger Detect Interrupt Sense Control
+  BATTPVL = $04;  
+  // ADC Accumulate Current
+  CADAC08 = $00;  // ADC accumulate current bits
+  CADAC09 = $01;  // ADC accumulate current bits
+  // ADC Accumulate Current
+  CADAC24 = $00;  // ADC accumulate current bits
+  CADAC25 = $01;  // ADC accumulate current bits
+  CADAC26 = $02;  // ADC accumulate current bits
+  CADAC27 = $03;  // ADC accumulate current bits
+  CADAC28 = $04;  // ADC accumulate current bits
+  CADAC29 = $05;  // ADC accumulate current bits
+  CADAC30 = $06;  // ADC accumulate current bits
+  CADAC31 = $07;  // ADC accumulate current bits
+  // CC-ADC Instantaneous Current
+  CADIC0 = $00;  // CC-ADC Instantaneous Current
+  CADIC1 = $01;  // CC-ADC Instantaneous Current
+  CADIC2 = $02;  // CC-ADC Instantaneous Current
+  CADIC3 = $03;  // CC-ADC Instantaneous Current
+  CADIC4 = $04;  // CC-ADC Instantaneous Current
+  CADIC5 = $05;  // CC-ADC Instantaneous Current
+  CADIC6 = $06;  // CC-ADC Instantaneous Current
+  CADIC7 = $07;  // CC-ADC Instantaneous Current
+  // CC-ADC Control and Status Register A
+  CADSE = $00;  
+  CADSI0 = $01;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADSI1 = $02;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADAS0 = $03;  // CC_ADC Accumulate Current Select Bits
+  CADAS1 = $04;  // CC_ADC Accumulate Current Select Bits
+  CADUB = $05;  
+  CADPOL = $06;  
+  CADEN = $07;  
+  // CC-ADC Control and Status Register B
+  CADICIF = $00;  
+  CADRCIF = $01;  
+  CADACIF = $02;  
+  CADICIE = $04;  
+  CADRCIE = $05;  
+  CADACIE = $06;  
+  // CC-ADC Control and Status Register C
+  CADVSE = $00;  
+  // CC-ADC Regular Charge Current
+  CADRCC0 = $00;  // CC-ADC Regular Charge Current
+  CADRCC1 = $01;  // CC-ADC Regular Charge Current
+  CADRCC2 = $02;  // CC-ADC Regular Charge Current
+  CADRCC3 = $03;  // CC-ADC Regular Charge Current
+  CADRCC4 = $04;  // CC-ADC Regular Charge Current
+  CADRCC5 = $05;  // CC-ADC Regular Charge Current
+  CADRCC6 = $06;  // CC-ADC Regular Charge Current
+  CADRCC7 = $07;  // CC-ADC Regular Charge Current
+  // CC-ADC Regular Discharge Current
+  CADRDC0 = $00;  // CC-ADC Regular Discharge Current
+  CADRDC1 = $01;  // CC-ADC Regular Discharge Current
+  CADRDC2 = $02;  // CC-ADC Regular Discharge Current
+  CADRDC3 = $03;  // CC-ADC Regular Discharge Current
+  CADRDC4 = $04;  // CC-ADC Regular Discharge Current
+  CADRDC5 = $05;  // CC-ADC Regular Discharge Current
+  CADRDC6 = $06;  // CC-ADC Regular Discharge Current
+  CADRDC7 = $07;  // CC-ADC Regular Discharge Current
+  // FET Control and Status Register
+  CFE = $00;  
+  DFE = $01;  
+  CPS = $02;  
+  DUVRD = $03;  
+  // Cell Balancing Control Register
+  CBE1 = $00;  // Cell Balancing Enables
+  CBE2 = $01;  // Cell Balancing Enables
+  CBE3 = $02;  // Cell Balancing Enables
+  CBE4 = $03;  // Cell Balancing Enables
+  // Battery Protection Interrupt Mask Register
+  CHCIE = $00;  
+  DHCIE = $01;  
+  COCIE = $02;  
+  DOCIE = $03;  
+  SCIE = $04;  
+  // Battery Protection Interrupt Flag Register
+  CHCIF = $00;  
+  DHCIF = $01;  
+  COCIF = $02;  
+  DOCIF = $03;  
+  SCIF = $04;  
+  // Battery Protection Short-Circuit Detection Level Register
+  SCDL0 = $00;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL1 = $01;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL2 = $02;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL3 = $03;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL4 = $04;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL5 = $05;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL6 = $06;  // Battery Protection Short-Circuit Detection Level Register bits
+  SCDL7 = $07;  // Battery Protection Short-Circuit Detection Level Register bits
+  // Battery Protection Discharge-Over-current Detection Level Register
+  DOCDL0 = $00;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL1 = $01;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL2 = $02;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL3 = $03;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL4 = $04;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL5 = $05;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL6 = $06;  // Battery Protection Discharge-Over-current Detection Level bits
+  DOCDL7 = $07;  // Battery Protection Discharge-Over-current Detection Level bits
+  // Battery Protection Charge-Over-current Detection Level Register
+  COCDL0 = $00;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL1 = $01;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL2 = $02;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL3 = $03;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL4 = $04;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL5 = $05;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL6 = $06;  // Battery Protection Charge-Over-current Detection Level bits
+  COCDL7 = $07;  // Battery Protection Charge-Over-current Detection Level bits
+  // Battery Protection Discharge-High-current Detection Level Register
+  DHCDL0 = $00;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL1 = $01;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL2 = $02;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL3 = $03;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL4 = $04;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL5 = $05;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL6 = $06;  // Battery Protection Discharge-High-current Detection Level bits
+  DHCDL7 = $07;  // Battery Protection Discharge-High-current Detection Level bits
+  // Battery Protection Charge-High-current Detection Level Register
+  CHCDL0 = $00;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL1 = $01;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL2 = $02;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL3 = $03;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL4 = $04;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL5 = $05;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL6 = $06;  // Battery Protection Charge-High-current Detection Level bits
+  CHCDL7 = $07;  // Battery Protection Charge-High-current Detection Level bits
+  // Battery Protection Short-current Timing Register
+  SCPT0 = $00;  // Battery Protection Short-current Timing bits
+  SCPT1 = $01;  // Battery Protection Short-current Timing bits
+  SCPT2 = $02;  // Battery Protection Short-current Timing bits
+  SCPT3 = $03;  // Battery Protection Short-current Timing bits
+  SCPT4 = $04;  // Battery Protection Short-current Timing bits
+  SCPT5 = $05;  // Battery Protection Short-current Timing bits
+  SCPT6 = $06;  // Battery Protection Short-current Timing bits
+  // Battery Protection Over-current Timing Register
+  OCPT0 = $00;  // Battery Protection Over-current Timing bits
+  OCPT1 = $01;  // Battery Protection Over-current Timing bits
+  OCPT2 = $02;  // Battery Protection Over-current Timing bits
+  OCPT3 = $03;  // Battery Protection Over-current Timing bits
+  OCPT4 = $04;  // Battery Protection Over-current Timing bits
+  OCPT5 = $05;  // Battery Protection Over-current Timing bits
+  // Battery Protection Short-current Timing Register
+  HCPT0 = $00;  // Battery Protection Short-current Timing bits
+  HCPT1 = $01;  // Battery Protection Short-current Timing bits
+  HCPT2 = $02;  // Battery Protection Short-current Timing bits
+  HCPT3 = $03;  // Battery Protection Short-current Timing bits
+  HCPT4 = $04;  // Battery Protection Short-current Timing bits
+  HCPT5 = $05;  // Battery Protection Short-current Timing bits
+  // Battery Protection Control Register
+  CHCD = $00;  
+  DHCD = $01;  
+  COCD = $02;  
+  DOCD = $03;  
+  SCD = $04;  
+  EPID = $05;  
+  // Battery Protection Parameter Lock Register
+  BPPL = $00;  
+  BPPLE = $01;  
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
+procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 6 External Interrupt Request 3
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 7 Pin Change Interrupt 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 8 Pin Change Interrupt 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 9 Watchdog Timeout Interrupt
+procedure BGSCD_ISR; external name 'BGSCD_ISR'; // Interrupt 10 Bandgap Buffer Short Circuit Detected
+procedure CHDET_ISR; external name 'CHDET_ISR'; // Interrupt 11 Charger Detect
+procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 12 Timer 1 Input capture
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer 1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer 1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer 1 overflow
+procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 16 Timer 0 Input Capture
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 17 Timer 0 Comapre Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 18 Timer 0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 19 Timer 0 Overflow
+procedure TWIBUSCD_ISR; external name 'TWIBUSCD_ISR'; // Interrupt 20 Two-Wire Bus Connect/Disconnect
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 21 Two-Wire Serial Interface
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 22 SPI Serial transfer complete
+procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 23 Voltage ADC Conversion Complete
+procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 24 Coulomb Counter ADC Conversion Complete
+procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 25 Coloumb Counter ADC Regular Current
+procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 26 Coloumb Counter ADC Accumulator
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 27 EEPROM Ready
+procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 28 SPM Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp BPINT_ISR
+  jmp VREGMON_ISR
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp WDT_ISR
+  jmp BGSCD_ISR
+  jmp CHDET_ISR
+  jmp TIMER1_IC_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_IC_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp TWIBUSCD_ISR
+  jmp TWI_ISR
+  jmp SPI_STC_ISR
+  jmp VADC_ISR
+  jmp CCADC_CONV_ISR
+  jmp CCADC_REG_CUR_ISR
+  jmp CCADC_ACC_ISR
+  jmp EE_READY_ISR
+  jmp SPM_ISR
+
+  {$i start.inc}
+
+  .weak BPINT_ISR
+  .weak VREGMON_ISR
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak BGSCD_ISR
+  .weak CHDET_ISR
+  .weak TIMER1_IC_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_IC_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak TWIBUSCD_ISR
+  .weak TWI_ISR
+  .weak SPI_STC_ISR
+  .weak VADC_ISR
+  .weak CCADC_CONV_ISR
+  .weak CCADC_REG_CUR_ISR
+  .weak CCADC_ACC_ISR
+  .weak EE_READY_ISR
+  .weak SPM_ISR
+
+  .set BPINT_ISR, Default_IRQ_handler
+  .set VREGMON_ISR, Default_IRQ_handler
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set BGSCD_ISR, Default_IRQ_handler
+  .set CHDET_ISR, Default_IRQ_handler
+  .set TIMER1_IC_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_IC_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set TWIBUSCD_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set VADC_ISR, Default_IRQ_handler
+  .set CCADC_CONV_ISR, Default_IRQ_handler
+  .set CCADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CCADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set SPM_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega2564rfr2.pp

@@ -0,0 +1,2095 @@
+unit ATmega2564RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  RAMPZ: byte absolute $5B;  // Extended Z-pointer Register for ELPM/SPM
+  EIND: byte absolute $5C;  // Extended Indirect Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Extended Z-pointer Register for ELPM/SPM
+  RAMPZ0 = $00;  // Extended Z-Pointer Value
+  RAMPZ1 = $01;  // Extended Z-Pointer Value
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  Res = $00;  
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega256rfr2.pp

@@ -0,0 +1,2103 @@
+unit ATmega256RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  RAMPZ: byte absolute $5B;  // Extended Z-pointer Register for ELPM/SPM
+  EIND: byte absolute $5C;  // Extended Indirect Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Extended Z-pointer Register for ELPM/SPM
+  RAMPZ0 = $00;  // Extended Z-Pointer Value
+  RAMPZ1 = $01;  // Extended Z-Pointer Value
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  OSCCAL0 = $00;  // Oscillator Calibration 
+  OSCCAL1 = $01;  // Oscillator Calibration 
+  OSCCAL2 = $02;  // Oscillator Calibration 
+  OSCCAL3 = $03;  // Oscillator Calibration 
+  OSCCAL4 = $04;  // Oscillator Calibration 
+  OSCCAL5 = $05;  // Oscillator Calibration 
+  OSCCAL6 = $06;  // Oscillator Calibration 
+  OSCCAL7 = $07;  // Oscillator Calibration 
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  Res = $00;  
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega32hvbrevb.pp

@@ -0,0 +1,538 @@
+unit ATmega32HVBrevB;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins
+  PORTC: byte absolute $28;  // Port C Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  OSICSR: byte absolute $37;  // Oscillator Sampling Interface Control and Status Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Read/Write Access
+  EEARL: byte absolute $41;  // EEPROM Read/Write Access
+  EEARH: byte absolute $42;  // EEPROM Read/Write Access;
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter 0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: word absolute $46;  // Timer Counter 0  Bytes
+  TCNT0L: byte absolute $46;  // Timer Counter 0  Bytes
+  TCNT0H: byte absolute $47;  // Timer Counter 0  Bytes;
+  OCR0A: byte absolute $48;  // Output Compare Register 0A
+  OCR0B: byte absolute $49;  // Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  FOSCCAL: byte absolute $66;  // Fast Oscillator Calibration Value
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  PCMSK0: byte absolute $6B;  // Pin Change Enable Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Enable Mask Register 1
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  VADC: word absolute $78;  // VADC Data Register  Bytes
+  VADCL: byte absolute $78;  // VADC Data Register  Bytes
+  VADCH: byte absolute $79;  // VADC Data Register  Bytes;
+  VADCSR: byte absolute $7A;  // The VADC Control and Status register
+  VADMUX: byte absolute $7C;  // The VADC multiplexer Selection Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1A: byte absolute $80;  // Timer/Counter 1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1  Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1  Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1  Bytes;
+  OCR1A: byte absolute $88;  // Output Compare Register 1A
+  OCR1B: byte absolute $89;  // Output Compare Register B
+  TWBR: byte absolute $B8;  // TWI Bit Rate register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address register
+  TWDR: byte absolute $BB;  // TWI Data register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  TWBCSR: byte absolute $BE;  // TWI Bus Control and Status Register
+  ROCR: byte absolute $C8;  // Regulator Operating Condition Register
+  BGCCR: byte absolute $D0;  // Bandgap Calibration Register
+  BGCRR: byte absolute $D1;  // Bandgap Calibration of Resistor Ladder
+  BGCSR: byte absolute $D2;  // Bandgap Control and Status Register
+  CHGDCSR: byte absolute $D4;  // Charger Detect Control and Status Register
+  CADAC0: byte absolute $E0;  // ADC Accumulate Current
+  CADAC1: byte absolute $E1;  // ADC Accumulate Current
+  CADAC2: byte absolute $E2;  // ADC Accumulate Current
+  CADAC3: byte absolute $E3;  // ADC Accumulate Current
+  CADIC: word absolute $E4;  // CC-ADC Instantaneous Current
+  CADICL: byte absolute $E4;  // CC-ADC Instantaneous Current
+  CADICH: byte absolute $E5;  // CC-ADC Instantaneous Current;
+  CADCSRA: byte absolute $E6;  // CC-ADC Control and Status Register A
+  CADCSRB: byte absolute $E7;  // CC-ADC Control and Status Register B
+  CADCSRC: byte absolute $E8;  // CC-ADC Control and Status Register C
+  CADRCC: byte absolute $E9;  // CC-ADC Regular Charge Current
+  CADRDC: byte absolute $EA;  // CC-ADC Regular Discharge Current
+  FCSR: byte absolute $F0;  // FET Control and Status Register
+  CBCR: byte absolute $F1;  // Cell Balancing Control Register
+  BPIMSK: byte absolute $F2;  // Battery Protection Interrupt Mask Register
+  BPIFR: byte absolute $F3;  // Battery Protection Interrupt Flag Register
+  BPSCD: byte absolute $F5;  // Battery Protection Short-Circuit Detection Level Register
+  BPDOCD: byte absolute $F6;  // Battery Protection Discharge-Over-current Detection Level Register
+  BPCOCD: byte absolute $F7;  // Battery Protection Charge-Over-current Detection Level Register
+  BPDHCD: byte absolute $F8;  // Battery Protection Discharge-High-current Detection Level Register
+  BPCHCD: byte absolute $F9;  // Battery Protection Charge-High-current Detection Level Register
+  BPSCTR: byte absolute $FA;  // Battery Protection Short-current Timing Register
+  BPOCTR: byte absolute $FB;  // Battery Protection Over-current Timing Register
+  BPHCTR: byte absolute $FC;  // Battery Protection Short-current Timing Register
+  BPCR: byte absolute $FD;  // Battery Protection Control Register
+  BPPLR: byte absolute $FE;  // Battery Protection Parameter Lock Register
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  ICF0 = $03;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $03;  
+  // Oscillator Sampling Interface Control and Status Register
+  OSIEN = $00;  
+  OSIST = $01;  
+  OSISEL0 = $04;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flags
+  INTF1 = $01;  // External Interrupt Flags
+  INTF2 = $02;  // External Interrupt Flags
+  INTF3 = $03;  // External Interrupt Flags
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request 3 Enable
+  INT1 = $01;  // External Interrupt Request 3 Enable
+  INT2 = $02;  // External Interrupt Request 3 Enable
+  INT3 = $03;  // External Interrupt Request 3 Enable
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;
+  EEPM1 = $05;
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter 0 Control Register A
+  WGM00 = $00;  
+  ICS0 = $03;  
+  ICES0 = $04;  
+  ICNC0 = $05;  
+  ICEN0 = $06;  
+  TCW0 = $07;  
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  OCDRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  CKOE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  LBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 0
+  PRVADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRSPI = $03;  
+  PRVRM = $05;  
+  PRTWI = $06;  
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register
+  ISC00 = $00;  // External Interrupt Sense Control 0 Bits
+  ISC01 = $01;  // External Interrupt Sense Control 0 Bits
+  ISC10 = $02;  // External Interrupt Sense Control 1 Bits
+  ISC11 = $03;  // External Interrupt Sense Control 1 Bits
+  ISC20 = $04;  // External Interrupt Sense Control 2 Bits
+  ISC21 = $05;  // External Interrupt Sense Control 2 Bits
+  ISC30 = $06;  // External Interrupt Sense Control 3 Bits
+  ISC31 = $07;  // External Interrupt Sense Control 3 Bits
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  ICIE0 = $03;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $03;  
+  // The VADC Control and Status register
+  VADCCIE = $00;  
+  VADCCIF = $01;  
+  VADSC = $02;  
+  VADEN = $03;  
+  // The VADC multiplexer Selection Register
+  VADMUX0 = $00;  // Analog Channel and Gain Selection Bits
+  VADMUX1 = $01;  // Analog Channel and Gain Selection Bits
+  VADMUX2 = $02;  // Analog Channel and Gain Selection Bits
+  VADMUX3 = $03;  // Analog Channel and Gain Selection Bits
+  // Digital Input Disable Register
+  PA0DID = $00;  
+  PA1DID = $01;  
+  // Timer/Counter 1 Control Register A
+  WGM10 = $00;  
+  ICS1 = $03;  
+  ICES1 = $04;  
+  ICNC1 = $05;  
+  ICEN1 = $06;  
+  TCW1 = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bis
+  CS11 = $01;  // Clock Select1 bis
+  CS12 = $02;  // Clock Select1 bis
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler
+  TWPS1 = $01;  // TWI Prescaler
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address register Bits
+  TWA1 = $02;  // TWI (Slave) Address register Bits
+  TWA2 = $03;  // TWI (Slave) Address register Bits
+  TWA3 = $04;  // TWI (Slave) Address register Bits
+  TWA4 = $05;  // TWI (Slave) Address register Bits
+  TWA5 = $06;  // TWI (Slave) Address register Bits
+  TWA6 = $07;  // TWI (Slave) Address register Bits
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  TWAM0 = $01;
+  TWAM1 = $02;
+  TWAM2 = $03;
+  TWAM3 = $04;
+  TWAM4 = $05;
+  TWAM5 = $06;
+  TWAM6 = $07;
+  // TWI Bus Control and Status Register
+  TWBCIP = $00;  
+  TWBDT0 = $01;  // TWI Bus Disconnect Time-out Period
+  TWBDT1 = $02;  // TWI Bus Disconnect Time-out Period
+  TWBCIE = $06;  
+  TWBCIF = $07;  
+  // Regulator Operating Condition Register
+  ROCWIE = $00;  
+  ROCWIF = $01;  
+  ROCD = $04;  
+  ROCS = $07;  
+  // Bandgap Calibration Register
+  BGCC0 = $00;  // BG Calibration of PTAT Current Bits
+  BGCC1 = $01;  // BG Calibration of PTAT Current Bits
+  BGCC2 = $02;  // BG Calibration of PTAT Current Bits
+  BGCC3 = $03;  // BG Calibration of PTAT Current Bits
+  BGCC4 = $04;  // BG Calibration of PTAT Current Bits
+  BGCC5 = $05;  // BG Calibration of PTAT Current Bits
+  // Bandgap Control and Status Register
+  BGSCDIE = $00;  
+  BGSCDIF = $01;  
+  BGSCDE = $04;  
+  BGD = $05;  
+  // Charger Detect Control and Status Register
+  CHGDIE = $00;  
+  CHGDIF = $01;  
+  CHGDISC0 = $02;  // Charger Detect Interrupt Sense Control
+  CHGDISC1 = $03;  // Charger Detect Interrupt Sense Control
+  BATTPVL = $04;  
+  // CC-ADC Control and Status Register A
+  CADSE = $00;  
+  CADSI0 = $01;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADSI1 = $02;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADAS0 = $03;  // CC_ADC Accumulate Current Select Bits
+  CADAS1 = $04;  // CC_ADC Accumulate Current Select Bits
+  CADUB = $05;  
+  CADPOL = $06;  
+  CADEN = $07;  
+  // CC-ADC Control and Status Register B
+  CADICIF = $00;  
+  CADRCIF = $01;  
+  CADACIF = $02;  
+  CADICIE = $04;  
+  CADRCIE = $05;  
+  CADACIE = $06;  
+  // CC-ADC Control and Status Register C
+  CADVSE = $00;  
+  // FET Control and Status Register
+  CFE = $00;  
+  DFE = $01;  
+  CPS = $02;  
+  DUVRD = $03;  
+  // Cell Balancing Control Register
+  CBE1 = $00;  // Cell Balancing Enables
+  CBE2 = $01;  // Cell Balancing Enables
+  CBE3 = $02;  // Cell Balancing Enables
+  CBE4 = $03;  // Cell Balancing Enables
+  // Battery Protection Interrupt Mask Register
+  CHCIE = $00;  
+  DHCIE = $01;  
+  COCIE = $02;  
+  DOCIE = $03;  
+  SCIE = $04;  
+  // Battery Protection Interrupt Flag Register
+  CHCIF = $00;  
+  DHCIF = $01;  
+  COCIF = $02;  
+  DOCIF = $03;  
+  SCIF = $04;  
+  // Battery Protection Control Register
+  CHCD = $00;  
+  DHCD = $01;  
+  COCD = $02;  
+  DOCD = $03;  
+  SCD = $04;  
+  EPID = $05;  
+  // Battery Protection Parameter Lock Register
+  BPPL = $00;  
+  BPPLE = $01;  
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
+procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 6 External Interrupt Request 3
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 7 Pin Change Interrupt 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 8 Pin Change Interrupt 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 9 Watchdog Timeout Interrupt
+procedure BGSCD_ISR; external name 'BGSCD_ISR'; // Interrupt 10 Bandgap Buffer Short Circuit Detected
+procedure CHDET_ISR; external name 'CHDET_ISR'; // Interrupt 11 Charger Detect
+procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 12 Timer 1 Input capture
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer 1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer 1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer 1 overflow
+procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 16 Timer 0 Input Capture
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 17 Timer 0 Comapre Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 18 Timer 0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 19 Timer 0 Overflow
+procedure TWIBUSCD_ISR; external name 'TWIBUSCD_ISR'; // Interrupt 20 Two-Wire Bus Connect/Disconnect
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 21 Two-Wire Serial Interface
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 22 SPI Serial transfer complete
+procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 23 Voltage ADC Conversion Complete
+procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 24 Coulomb Counter ADC Conversion Complete
+procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 25 Coloumb Counter ADC Regular Current
+procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 26 Coloumb Counter ADC Accumulator
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 27 EEPROM Ready
+procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 28 SPM Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp BPINT_ISR
+  jmp VREGMON_ISR
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp WDT_ISR
+  jmp BGSCD_ISR
+  jmp CHDET_ISR
+  jmp TIMER1_IC_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_IC_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp TWIBUSCD_ISR
+  jmp TWI_ISR
+  jmp SPI_STC_ISR
+  jmp VADC_ISR
+  jmp CCADC_CONV_ISR
+  jmp CCADC_REG_CUR_ISR
+  jmp CCADC_ACC_ISR
+  jmp EE_READY_ISR
+  jmp SPM_ISR
+
+  {$i start.inc}
+
+  .weak BPINT_ISR
+  .weak VREGMON_ISR
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak BGSCD_ISR
+  .weak CHDET_ISR
+  .weak TIMER1_IC_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_IC_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak TWIBUSCD_ISR
+  .weak TWI_ISR
+  .weak SPI_STC_ISR
+  .weak VADC_ISR
+  .weak CCADC_CONV_ISR
+  .weak CCADC_REG_CUR_ISR
+  .weak CCADC_ACC_ISR
+  .weak EE_READY_ISR
+  .weak SPM_ISR
+
+  .set BPINT_ISR, Default_IRQ_handler
+  .set VREGMON_ISR, Default_IRQ_handler
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set BGSCD_ISR, Default_IRQ_handler
+  .set CHDET_ISR, Default_IRQ_handler
+  .set TIMER1_IC_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_IC_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set TWIBUSCD_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set VADC_ISR, Default_IRQ_handler
+  .set CCADC_CONV_ISR, Default_IRQ_handler
+  .set CCADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CCADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set SPM_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega406.pp

@@ -0,0 +1,506 @@
+unit ATmega406;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Input Pins, Port D
+  DDRD: byte absolute $2A;  // Data Direction Register, Port D
+  PORTD: byte absolute $2B;  // Data Register, Port D
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register
+  TCNT0: byte absolute $46;  // Timer Counter 0
+  OCR0A: byte absolute $47;  // Output compare Register A
+  OCR0B: byte absolute $48;  // Output compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  WUTCSR: byte absolute $62;  // Wake-up Timer Control Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  FOSCCAL: byte absolute $66;  // Fast Oscillator Calibration Value
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  PCMSK0: byte absolute $6B;  // Pin Change Enable Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Enable Mask Register 1
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  VADC: word absolute $78;  // VADC Data Register  Bytes
+  VADCL: byte absolute $78;  // VADC Data Register  Bytes
+  VADCH: byte absolute $79;  // VADC Data Register  Bytes;
+  VADCSR: byte absolute $7A;  // The VADC Control and Status register
+  VADMUX: byte absolute $7C;  // The VADC multiplexer Selection Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1  Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1  Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1  Bytes;
+  OCR1AL: byte absolute $88;  // Output Compare Register 1A Low byte
+  OCR1AH: byte absolute $89;  // Output Compare Register 1A High byte
+  TWBR: byte absolute $B8;  // TWI Bit Rate register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address register
+  TWDR: byte absolute $BB;  // TWI Data register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  TWBCSR: byte absolute $BE;  // TWI Bus Control and Status Register
+  CCSR: byte absolute $C0;  // Clock Control and Status Register
+  BGCCR: byte absolute $D0;  // Bandgap Calibration Register
+  BGCRR: byte absolute $D1;  // Bandgap Calibration of Resistor Ladder
+  CADAC0: byte absolute $E0;  // ADC Accumulate Current
+  CADAC1: byte absolute $E1;  // ADC Accumulate Current
+  CADAC2: byte absolute $E2;  // ADC Accumulate Current
+  CADAC3: byte absolute $E3;  // ADC Accumulate Current
+  CADCSRA: byte absolute $E4;  // CC-ADC Control and Status Register A
+  CADCSRB: byte absolute $E5;  // CC-ADC Control and Status Register B
+  CADRCC: byte absolute $E6;  // CC-ADC Regular Charge Current
+  CADRDC: byte absolute $E7;  // CC-ADC Regular Discharge Current
+  CADIC: word absolute $E8;  // CC-ADC Instantaneous Current
+  CADICL: byte absolute $E8;  // CC-ADC Instantaneous Current
+  CADICH: byte absolute $E9;  // CC-ADC Instantaneous Current;
+  FCSR: byte absolute $F0;
+  CBCR: byte absolute $F1;  // Cell Balancing Control Register
+  BPIR: byte absolute $F2;  // Battery Protection Interrupt Register
+  BPDUV: byte absolute $F3;  // Battery Protection Deep Under Voltage Register
+  BPSCD: byte absolute $F4;  // Battery Protection Short-Circuit Detection Level Register
+  BPOCD: byte absolute $F5;  // Battery Protection OverCurrent Detection Level Register
+  CBPTR: byte absolute $F6;  // Current Battery Protection Timing Register
+  BPCR: byte absolute $F7;  // Battery Protection Control Register
+  BPPLR: byte absolute $F8;  // Battery Protection Parameter Lock Register
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  // Data Register, Port D
+  PD0 = $00;  
+  PD1 = $01;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flags
+  INTF1 = $01;  // External Interrupt Flags
+  INTF2 = $02;  // External Interrupt Flags
+  INTF3 = $03;  // External Interrupt Flags
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request 1 Enable
+  INT1 = $01;  // External Interrupt Request 1 Enable
+  INT2 = $02;  // External Interrupt Request 1 Enable
+  INT3 = $03;  // External Interrupt Request 1 Enable
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode Bits
+  EEPM1 = $05;  // EEPROM Programming Mode Bits
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register
+  WGM00 = $00;  // Clock Select0 bits
+  WGM01 = $01;  // Clock Select0 bits
+  COM0B0 = $04;
+  COM0B1 = $05;
+  COM0A0 = $06;  // Force Output Compare
+  COM0A1 = $07;  // Force Output Compare
+  // Timer/Counter0 Control Register
+  CS00 = $00;  // Clock Select0 bits
+  CS01 = $01;  // Clock Select0 bits
+  CS02 = $02;  // Clock Select0 bits
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // Output compare Register A
+  OCR0A0 = $00;
+  OCR0A1 = $01;
+  OCR0A2 = $02;
+  OCR0A3 = $03;
+  OCR0A4 = $04;
+  OCR0A5 = $05;
+  OCR0A6 = $06;
+  OCR0A7 = $07;
+  // Output compare Register B
+  OCR0B0 = $00;
+  OCR0B1 = $01;
+  OCR0B2 = $02;
+  OCR0B3 = $03;
+  OCR0B4 = $04;
+  OCR0B5 = $05;
+  OCR0B6 = $06;
+  OCR0B7 = $07;
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Wake-up Timer Control Register
+  WUTP0 = $00;  // Wake-up Timer Prescaler Bits
+  WUTP1 = $01;  // Wake-up Timer Prescaler Bits
+  WUTP2 = $02;  // Wake-up Timer Prescaler Bits
+  WUTE = $03;  
+  WUTR = $04;  
+  WUTCF = $05;  
+  WUTIE = $06;  
+  WUTIF = $07;  
+  // Power Reduction Register 0
+  PRVADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRTWI = $03;  
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register
+  ISC00 = $00;  // External Interrupt Sense Control 0 Bits
+  ISC01 = $01;  // External Interrupt Sense Control 0 Bits
+  ISC10 = $02;  // External Interrupt Sense Control 1 Bits
+  ISC11 = $03;  // External Interrupt Sense Control 1 Bits
+  ISC20 = $04;  // External Interrupt Sense Control 2 Bits
+  ISC21 = $05;  // External Interrupt Sense Control 2 Bits
+  ISC30 = $06;  // External Interrupt Sense Control 3 Bits
+  ISC31 = $07;  // External Interrupt Sense Control 3 Bits
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  // The VADC Control and Status register
+  VADCCIE = $00;  
+  VADCCIF = $01;  
+  VADSC = $02;  
+  VADEN = $03;  
+  // The VADC multiplexer Selection Register
+  VADMUX0 = $00;  // Analog Channel and Gain Selection Bits
+  VADMUX1 = $01;  // Analog Channel and Gain Selection Bits
+  VADMUX2 = $02;  // Analog Channel and Gain Selection Bits
+  VADMUX3 = $03;  // Analog Channel and Gain Selection Bits
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bits
+  CS11 = $01;  // Clock Select1 bits
+  CS12 = $02;  // Clock Select1 bits
+  CTC1 = $03;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler
+  TWPS1 = $01;  // TWI Prescaler
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address register Bits
+  TWA1 = $02;  // TWI (Slave) Address register Bits
+  TWA2 = $03;  // TWI (Slave) Address register Bits
+  TWA3 = $04;  // TWI (Slave) Address register Bits
+  TWA4 = $05;  // TWI (Slave) Address register Bits
+  TWA5 = $06;  // TWI (Slave) Address register Bits
+  TWA6 = $07;  // TWI (Slave) Address register Bits
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  TWAM0 = $01;
+  TWAM1 = $02;
+  TWAM2 = $03;
+  TWAM3 = $04;
+  TWAM4 = $05;
+  TWAM5 = $06;
+  TWAM6 = $07;
+  // TWI Bus Control and Status Register
+  TWBCIP = $00;  
+  TWBDT0 = $01;  // TWI Bus Disconnect Time-out Period
+  TWBDT1 = $02;  // TWI Bus Disconnect Time-out Period
+  TWBCIE = $06;  
+  TWBCIF = $07;  
+  // Clock Control and Status Register
+  ACS = $00;  
+  XOE = $01;  
+  // Bandgap Calibration Register
+  BGCC0 = $00;  // BG Calibration of PTAT Current Bits
+  BGCC1 = $01;  // BG Calibration of PTAT Current Bits
+  BGCC2 = $02;  // BG Calibration of PTAT Current Bits
+  BGCC3 = $03;  // BG Calibration of PTAT Current Bits
+  BGCC4 = $04;  // BG Calibration of PTAT Current Bits
+  BGCC5 = $05;  // BG Calibration of PTAT Current Bits
+  BGD = $07;  
+  // CC-ADC Control and Status Register A
+  CADSE = $00;  
+  CADSI0 = $01;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADSI1 = $02;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADAS0 = $03;  // CC_ADC Accumulate Current Select Bits
+  CADAS1 = $04;  // CC_ADC Accumulate Current Select Bits
+  CADUB = $05;  
+  CADEN = $07;  
+  // CC-ADC Control and Status Register B
+  CADICIF = $00;  
+  CADRCIF = $01;  
+  CADACIF = $02;  
+  CADICIE = $04;  
+  CADRCIE = $05;  
+  CADACIE = $06;  
+  PFD = $00;  
+  CFE = $01;  
+  DFE = $02;  
+  CPS = $03;  
+  PWMOPC = $04;  
+  PWMOC = $05;  
+  // Cell Balancing Control Register
+  CBE1 = $00;  // Cell Balancing Enables
+  CBE2 = $01;  // Cell Balancing Enables
+  CBE3 = $02;  // Cell Balancing Enables
+  CBE4 = $03;  // Cell Balancing Enables
+  // Battery Protection Interrupt Register
+  SCIE = $00;  
+  DOCIE = $01;  
+  COCIE = $02;  
+  DUVIE = $03;  
+  SCIF = $04;  
+  DOCIF = $05;  
+  COCIF = $06;  
+  DUVIF = $07;  
+  // Battery Protection Deep Under Voltage Register
+  DUDL0 = $00;
+  DUDL1 = $01;
+  DUDL2 = $02;
+  DUDL3 = $03;
+  DUVT0 = $04;
+  DUVT1 = $05;
+  // Battery Protection Short-Circuit Detection Level Register
+  SCDL0 = $00;
+  SCDL1 = $01;
+  SCDL2 = $02;
+  SCDL3 = $03;
+  // Battery Protection OverCurrent Detection Level Register
+  CCDL0 = $00;
+  CCDL1 = $01;
+  CCDL2 = $02;
+  CCDL3 = $03;
+  DCDL0 = $04;
+  DCDL1 = $05;
+  DCDL2 = $06;
+  DCDL3 = $07;
+  // Current Battery Protection Timing Register
+  OCPT0 = $00;
+  OCPT1 = $01;
+  OCPT2 = $02;
+  OCPT3 = $03;
+  SCPT0 = $04;
+  SCPT1 = $05;
+  SCPT2 = $06;
+  SCPT3 = $07;
+  // Battery Protection Control Register
+  CCD = $00;  
+  DCD = $01;  
+  SCD = $02;  
+  DUVD = $03;  
+  // Battery Protection Parameter Lock Register
+  BPPL = $00;  
+  BPPLE = $01;  
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 2 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 3 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 4 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 5 External Interrupt Request 3
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 6 Pin Change Interrupt 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 7 Pin Change Interrupt 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Timeout Interrupt
+procedure WAKE_UP_ISR; external name 'WAKE_UP_ISR'; // Interrupt 9 Wakeup timer overflow
+procedure TIM1_COMP_ISR; external name 'TIM1_COMP_ISR'; // Interrupt 10 Timer/Counter 1 Compare Match
+procedure TIM1_OVF_ISR; external name 'TIM1_OVF_ISR'; // Interrupt 11 Timer/Counter 1 Overflow
+procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 12 Timer/Counter0 Compare A Match
+procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 13 Timer/Counter0 Compare B Match
+procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 14 Timer/Counter0 Overflow
+procedure TWI_BUS_CD_ISR; external name 'TWI_BUS_CD_ISR'; // Interrupt 15 Two-Wire Bus Connect/Disconnect
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 16 Two-Wire Serial Interface
+procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 17 Voltage ADC Conversion Complete
+procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 18 Coulomb Counter ADC Conversion Complete
+procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 19 Coloumb Counter ADC Regular Current
+procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 20 Coloumb Counter ADC Accumulator
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 21 EEPROM Ready
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 22 Store Program Memory Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp BPINT_ISR
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp WDT_ISR
+  jmp WAKE_UP_ISR
+  jmp TIM1_COMP_ISR
+  jmp TIM1_OVF_ISR
+  jmp TIM0_COMPA_ISR
+  jmp TIM0_COMPB_ISR
+  jmp TIM0_OVF_ISR
+  jmp TWI_BUS_CD_ISR
+  jmp TWI_ISR
+  jmp VADC_ISR
+  jmp CCADC_CONV_ISR
+  jmp CCADC_REG_CUR_ISR
+  jmp CCADC_ACC_ISR
+  jmp EE_READY_ISR
+  jmp SPM_READY_ISR
+
+  {$i start.inc}
+
+  .weak BPINT_ISR
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak WAKE_UP_ISR
+  .weak TIM1_COMP_ISR
+  .weak TIM1_OVF_ISR
+  .weak TIM0_COMPA_ISR
+  .weak TIM0_COMPB_ISR
+  .weak TIM0_OVF_ISR
+  .weak TWI_BUS_CD_ISR
+  .weak TWI_ISR
+  .weak VADC_ISR
+  .weak CCADC_CONV_ISR
+  .weak CCADC_REG_CUR_ISR
+  .weak CCADC_ACC_ISR
+  .weak EE_READY_ISR
+  .weak SPM_READY_ISR
+
+  .set BPINT_ISR, Default_IRQ_handler
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set WAKE_UP_ISR, Default_IRQ_handler
+  .set TIM1_COMP_ISR, Default_IRQ_handler
+  .set TIM1_OVF_ISR, Default_IRQ_handler
+  .set TIM0_COMPA_ISR, Default_IRQ_handler
+  .set TIM0_COMPB_ISR, Default_IRQ_handler
+  .set TIM0_OVF_ISR, Default_IRQ_handler
+  .set TWI_BUS_CD_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set VADC_ISR, Default_IRQ_handler
+  .set CCADC_CONV_ISR, Default_IRQ_handler
+  .set CCADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CCADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega644rfr2.pp

@@ -0,0 +1,2090 @@
+unit ATmega644RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  Res = $00;  
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega64hve2.pp

@@ -0,0 +1,557 @@
+unit ATmega64HVE2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Read/Write Access
+  EEARL: byte absolute $41;  // EEPROM Read/Write Access
+  EEARH: byte absolute $42;  // EEPROM Read/Write Access;
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter 0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: word absolute $46;  // Timer Counter 0  Bytes
+  TCNT0L: byte absolute $46;  // Timer Counter 0  Bytes
+  TCNT0H: byte absolute $47;  // Timer Counter 0  Bytes;
+  OCR0A: byte absolute $48;  // Output Compare Register 0A
+  OCR0B: byte absolute $49;  // Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  WUTCSR: byte absolute $62;  // Wake-up Timer Control and Status Register
+  WDTCLR: byte absolute $63;  // Watchdog Timer Configuration Lock Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  SOSCCALA: byte absolute $66;  // Slow Oscillator Calibration Register A
+  SOSCCALB: byte absolute $67;  // Oscillator Calibration Register B
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  PCMSK0: byte absolute $6B;  // Pin Change Enable Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Enable Mask Register 1
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1A: byte absolute $80;  // Timer/Counter 1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1  Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1  Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1  Bytes;
+  OCR1A: byte absolute $88;  // Output Compare Register 1A
+  OCR1B: byte absolute $89;  // Output Compare Register B
+  LINCR: byte absolute $C0;  // LIN Control Register
+  LINSIR: byte absolute $C1;  // LIN Status and Interrupt Register
+  LINENIR: byte absolute $C2;  // LIN Enable Interrupt Register
+  LINERR: byte absolute $C3;  // LIN Error Register
+  LINBTR: byte absolute $C4;  // LIN Bit Timing Register
+  LINBRRL: byte absolute $C5;  // LIN Baud Rate Low Register
+  LINBRRH: byte absolute $C6;  // LIN Baud Rate High Register
+  LINDLR: byte absolute $C7;  // LIN Data Length Register
+  LINIDR: byte absolute $C8;  // LIN Identifier Register
+  LINSEL: byte absolute $C9;  // LIN Data Buffer Selection Register
+  LINDAT: byte absolute $CA;  // LIN Data Register
+  BGCSRA: byte absolute $D1;  // Bandgap Control and Status Register A
+  BGCRB: byte absolute $D2;  // Band Gap Calibration Register B
+  BGCRA: byte absolute $D3;  // Band Gap Calibration Register A
+  BGLR: byte absolute $D4;  // Band Gap Lock Register
+  PLLCSR: byte absolute $D8;  // PLL Control and Status Register
+  PBOV: byte absolute $DC;  // Port B Override
+  ADSCSRA: byte absolute $E0;  // ADC Synchronization Control and Status Register
+  ADSCSRB: byte absolute $E1;  // ADC Synchronization Control and Status Register
+  ADCRA: byte absolute $E2;  // ADC Control Register A
+  ADCRB: byte absolute $E3;  // ADC Control Register B
+  ADCRC: byte absolute $E4;  // ADC Control Register B
+  ADCRD: byte absolute $E5;  // ADC Control Register D
+  ADCRE: byte absolute $E6;  // ADC Control Register E
+  ADIFR: byte absolute $E7;  // ADC Interrupt Flag Register
+  ADIMR: byte absolute $E8;  // ADC Interrupt Mask Register
+  CADRCL: word absolute $E9;  // CC-ADC Regulator Current Comparator Threshold Level
+  CADRCLL: byte absolute $E9;  // CC-ADC Regulator Current Comparator Threshold Level
+  CADRCLH: byte absolute $EA;  // CC-ADC Regulator Current Comparator Threshold Level;
+  CADIC: word absolute $EB;  // C-ADC Instantaneous Conversion Result
+  CADICL: byte absolute $EB;  // C-ADC Instantaneous Conversion Result
+  CADICH: byte absolute $EC;  // C-ADC Instantaneous Conversion Result;
+  CADAC0: byte absolute $ED;  // C-ADC Accumulated Conversion Result
+  CADAC1: byte absolute $EE;  // C-ADC Accumulated Conversion Result
+  CADAC2: byte absolute $EF;  // C-ADC Accumulated Conversion Result
+  CADAC3: byte absolute $F0;  // C-ADC Accumulated Conversion Result
+  VADIC: word absolute $F1;  // V-ADC Instantaneous Conversion Result
+  VADICL: byte absolute $F1;  // V-ADC Instantaneous Conversion Result
+  VADICH: byte absolute $F2;  // V-ADC Instantaneous Conversion Result;
+  VADAC0: byte absolute $F3;  // V-ADC Accumulated Conversion Result
+  VADAC1: byte absolute $F4;  // V-ADC Accumulated Conversion Result
+  VADAC2: byte absolute $F5;  // V-ADC Accumulated Conversion Result
+  VADAC3: byte absolute $F6;  // V-ADC Accumulated Conversion Result
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  ICF0 = $03;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $03;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  
+  // External Interrupt Mask Register
+  INT0 = $00;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;
+  EEPM1 = $05;
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter 0 Control Register A
+  WGM00 = $00;  
+  ICS0 = $03;  
+  ICES0 = $04;  
+  ICNC0 = $05;  
+  ICEN0 = $06;  
+  TCW0 = $07;  
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  OCDRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  CKOE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  LBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Wake-up Timer Control and Status Register
+  WUTP0 = $00;  // Wake-up Timer Prescaler Bits
+  WUTP1 = $01;  // Wake-up Timer Prescaler Bits
+  WUTP2 = $02;  // Wake-up Timer Prescaler Bits
+  WUTE = $03;  
+  WUTR = $04;  
+  WUTIE = $06;  
+  WUTIF = $07;  
+  // Watchdog Timer Configuration Lock Register
+  WDCLE = $00;  
+  WDCL0 = $01;  // Watchdog Timer Comfiguration Lock bits
+  WDCL1 = $02;  // Watchdog Timer Comfiguration Lock bits
+  // Power Reduction Register 0
+  PRTIM0 = $00;  
+  PRTIM1 = $01;  
+  PRSPI = $02;  
+  PRLIN = $03;  
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register
+  ISC00 = $00;  
+  ISC01 = $01;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  ICIE0 = $03;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $03;  
+  // Digital Input Disable Register
+  PA0DID = $00;  
+  PA1DID = $01;  
+  // Timer/Counter 1 Control Register A
+  WGM10 = $00;  
+  ICS1 = $03;  
+  ICES1 = $04;  
+  ICNC1 = $05;  
+  ICEN1 = $06;  
+  TCW1 = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bis
+  CS11 = $01;  // Clock Select1 bis
+  CS12 = $02;  // Clock Select1 bis
+  // LIN Control Register
+  LCMD0 = $00;  // LIN Command and Mode bits
+  LCMD1 = $01;  // LIN Command and Mode bits
+  LCMD2 = $02;  // LIN Command and Mode bits
+  LENA = $03;  
+  LCONF0 = $04;  // LIN Configuration bits
+  LCONF1 = $05;  // LIN Configuration bits
+  LIN13 = $06;  
+  LSWRES = $07;  
+  // LIN Status and Interrupt Register
+  LRXOK = $00;  
+  LTXOK = $01;  
+  LIDOK = $02;  
+  LERR = $03;  
+  LBUSY = $04;  
+  LIDST0 = $05;  // Identifier Status bits
+  LIDST1 = $06;  // Identifier Status bits
+  LIDST2 = $07;  // Identifier Status bits
+  // LIN Enable Interrupt Register
+  LENRXOK = $00;  
+  LENTXOK = $01;  
+  LENIDOK = $02;  
+  LENERR = $03;  
+  // LIN Error Register
+  LBERR = $00;  
+  LCERR = $01;  
+  LPERR = $02;  
+  LSERR = $03;  
+  LFERR = $04;  
+  LOVERR = $05;  
+  LTOERR = $06;  
+  LABORT = $07;  
+  // LIN Bit Timing Register
+  LBT0 = $00;  // LIN Bit Timing bits
+  LBT1 = $01;  // LIN Bit Timing bits
+  LBT2 = $02;  // LIN Bit Timing bits
+  LBT3 = $03;  // LIN Bit Timing bits
+  LBT4 = $04;  // LIN Bit Timing bits
+  LBT5 = $05;  // LIN Bit Timing bits
+  LDISR = $07;  
+  // LIN Baud Rate Low Register
+  LDIV0 = $00;
+  LDIV1 = $01;
+  LDIV2 = $02;
+  LDIV3 = $03;
+  LDIV4 = $04;
+  LDIV5 = $05;
+  LDIV6 = $06;
+  LDIV7 = $07;
+  // LIN Data Length Register
+  LRXDL0 = $00;  // LIN Receive Data Length bits
+  LRXDL1 = $01;  // LIN Receive Data Length bits
+  LRXDL2 = $02;  // LIN Receive Data Length bits
+  LRXDL3 = $03;  // LIN Receive Data Length bits
+  LTXDL0 = $04;  // LIN Transmit Data Length bits
+  LTXDL1 = $05;  // LIN Transmit Data Length bits
+  LTXDL2 = $06;  // LIN Transmit Data Length bits
+  LTXDL3 = $07;  // LIN Transmit Data Length bits
+  // LIN Identifier Register
+  LID0 = $00;  // Identifier bit 5 or Data Length bits
+  LID1 = $01;  // Identifier bit 5 or Data Length bits
+  LID2 = $02;  // Identifier bit 5 or Data Length bits
+  LID3 = $03;  // Identifier bit 5 or Data Length bits
+  LID4 = $04;  // Identifier bit 5 or Data Length bits
+  LID5 = $05;  // Identifier bit 5 or Data Length bits
+  LP0 = $06;  // Parity bits
+  LP1 = $07;  // Parity bits
+  // LIN Data Buffer Selection Register
+  LINDX0 = $00;  // FIFO LIN Data Buffer Index bits
+  LINDX1 = $01;  // FIFO LIN Data Buffer Index bits
+  LINDX2 = $02;  // FIFO LIN Data Buffer Index bits
+  LAINC = $03;  
+  // LIN Data Register
+  LDATA0 = $00;
+  LDATA1 = $01;
+  LDATA2 = $02;
+  LDATA3 = $03;
+  LDATA4 = $04;
+  LDATA5 = $05;
+  LDATA6 = $06;
+  LDATA7 = $07;
+  // Bandgap Control and Status Register A
+  BGSC0 = $00;  // Band Gap Sample Configuration
+  BGSC1 = $01;  // Band Gap Sample Configuration
+  BGSC2 = $02;  // Band Gap Sample Configuration
+  // Band Gap Calibration Register B
+  BGCL0 = $00;  // Band Gap Calibration Linear
+  BGCL1 = $01;  // Band Gap Calibration Linear
+  BGCL2 = $02;  // Band Gap Calibration Linear
+  BGCL3 = $03;  // Band Gap Calibration Linear
+  BGCL4 = $04;  // Band Gap Calibration Linear
+  BGCL5 = $05;  // Band Gap Calibration Linear
+  BGCL6 = $06;  // Band Gap Calibration Linear
+  BGCL7 = $07;  // Band Gap Calibration Linear
+  // Band Gap Calibration Register A
+  BGCN0 = $00;  // Band Gap Calibration Nominal
+  BGCN1 = $01;  // Band Gap Calibration Nominal
+  BGCN2 = $02;  // Band Gap Calibration Nominal
+  BGCN3 = $03;  // Band Gap Calibration Nominal
+  BGCN4 = $04;  // Band Gap Calibration Nominal
+  BGCN5 = $05;  // Band Gap Calibration Nominal
+  BGCN6 = $06;  // Band Gap Calibration Nominal
+  BGCN7 = $07;  // Band Gap Calibration Nominal
+  // Band Gap Lock Register
+  BGPL = $00;  
+  BGPLE = $01;  
+  // PLL Control and Status Register
+  PLLCIE = $00;  
+  PLLCIF = $01;  
+  LOCK = $04;  
+  SWEN = $05;  
+  // Port B Override
+  PBOE0 = $00;  
+  PBOE3 = $03;  
+  PBOVCE = $07;  
+  // ADC Synchronization Control and Status Register
+  SCMD0 = $00;  // Synchronization Command
+  SCMD1 = $01;  // Synchronization Command
+  SBSY = $02;  
+  // ADC Synchronization Control and Status Register
+  CADICRB = $00;  
+  CADACRB = $01;  
+  CADICPS = $02;  
+  VADICRB = $04;  
+  VADACRB = $05;  
+  VADICPS = $06;  
+  // ADC Control Register A
+  CKSEL = $00;  
+  ADCMS0 = $01;  // C-ADC Chopper Mode Select
+  ADCMS1 = $02;  // C-ADC Chopper Mode Select
+  ADPSEL = $03;  
+  // ADC Control Register B
+  ADADES0 = $00;  // Accumulated Decimation Ratio Select
+  ADADES1 = $01;  // Accumulated Decimation Ratio Select
+  ADADES2 = $02;  // Accumulated Decimation Ratio Select
+  ADIDES0 = $03;  // Instantaneous Decimation Ratio Select
+  ADIDES1 = $04;  // Instantaneous Decimation Ratio Select
+  // ADC Control Register B
+  CADRCT0 = $00;  // C-ADC Regular Current Count Threshold
+  CADRCT1 = $01;  // C-ADC Regular Current Count Threshold
+  CADRCT2 = $02;  // C-ADC Regular Current Count Threshold
+  CADRCT3 = $03;  // C-ADC Regular Current Count Threshold
+  CADRCM0 = $04;  // C-ADC Regular Current Comparator Mode
+  CADRCM1 = $05;  // C-ADC Regular Current Comparator Mode
+  CADEN = $07;  
+  // ADC Control Register D
+  CADDSEL = $00;  
+  CADPDM0 = $01;  // C-ADC Pin Diagnostics Mode
+  CADPDM1 = $02;  // C-ADC Pin Diagnostics Mode
+  CADG0 = $03;  // C-ADC Gain
+  CADG1 = $04;  // C-ADC Gain
+  CADG2 = $05;  // C-ADC Gain
+  // ADC Control Register E
+  VADMUX0 = $00;  // V-ADC Channel Select
+  VADMUX1 = $01;  // V-ADC Channel Select
+  VADMUX2 = $02;  // V-ADC Channel Select
+  VADPDM0 = $03;  // V-ADC Pin Diagnostics Mode
+  VADPDM1 = $04;  // V-ADC Pin Diagnostics Mode
+  VADREFS = $05;  
+  VADEN = $07;  
+  // ADC Interrupt Flag Register
+  CADICIF = $00;  
+  CADACIF = $01;  
+  CADRCIF = $02;  
+  VADICIF = $04;  
+  VADACIF = $05;  
+  // ADC Interrupt Mask Register
+  CADICIE = $00;  
+  CADACIE = $01;  
+  CADRCIE = $02;  
+  VADICIE = $04;  
+  VADACIE = $05;  
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Timeout Interrupt
+procedure WAKEUP_ISR; external name 'WAKEUP_ISR'; // Interrupt 5 Wakeup Timer Overflow
+procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 6 Timer 1 Input capture
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 7 Timer 1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 8 Timer 1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 9 Timer 1 overflow
+procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 10 Timer 0 Input Capture
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 11 Timer 0 Comapre Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 12 Timer 0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 13 Timer 0 Overflow
+procedure LIN_STATUS_ISR; external name 'LIN_STATUS_ISR'; // Interrupt 14 LIN Status Interrupt
+procedure LIN_ERROR_ISR; external name 'LIN_ERROR_ISR'; // Interrupt 15 LIN Error Interrupt
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 16 SPI Serial transfer complete
+procedure VADC_CONV_ISR; external name 'VADC_CONV_ISR'; // Interrupt 17 Voltage ADC Instantaneous Conversion Complete
+procedure VADC_ACC_ISR; external name 'VADC_ACC_ISR'; // Interrupt 18 Voltage ADC Accumulated Conversion Complete
+procedure CADC_CONV_ISR; external name 'CADC_CONV_ISR'; // Interrupt 19 C-ADC Instantaneous Conversion Complete
+procedure CADC_REG_CUR_ISR; external name 'CADC_REG_CUR_ISR'; // Interrupt 20 C-ADC Regular Current
+procedure CADC_ACC_ISR; external name 'CADC_ACC_ISR'; // Interrupt 21 C-ADC Accumulated Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 22 EEPROM Ready
+procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 23 SPM Ready
+procedure PLL_ISR; external name 'PLL_ISR'; // Interrupt 24 PLL Lock Change Interrupt
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp WDT_ISR
+  jmp WAKEUP_ISR
+  jmp TIMER1_IC_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_IC_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp LIN_STATUS_ISR
+  jmp LIN_ERROR_ISR
+  jmp SPI_STC_ISR
+  jmp VADC_CONV_ISR
+  jmp VADC_ACC_ISR
+  jmp CADC_CONV_ISR
+  jmp CADC_REG_CUR_ISR
+  jmp CADC_ACC_ISR
+  jmp EE_READY_ISR
+  jmp SPM_ISR
+  jmp PLL_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak WAKEUP_ISR
+  .weak TIMER1_IC_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_IC_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak LIN_STATUS_ISR
+  .weak LIN_ERROR_ISR
+  .weak SPI_STC_ISR
+  .weak VADC_CONV_ISR
+  .weak VADC_ACC_ISR
+  .weak CADC_CONV_ISR
+  .weak CADC_REG_CUR_ISR
+  .weak CADC_ACC_ISR
+  .weak EE_READY_ISR
+  .weak SPM_ISR
+  .weak PLL_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set WAKEUP_ISR, Default_IRQ_handler
+  .set TIMER1_IC_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_IC_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set LIN_STATUS_ISR, Default_IRQ_handler
+  .set LIN_ERROR_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set VADC_CONV_ISR, Default_IRQ_handler
+  .set VADC_ACC_ISR, Default_IRQ_handler
+  .set CADC_CONV_ISR, Default_IRQ_handler
+  .set CADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set SPM_ISR, Default_IRQ_handler
+  .set PLL_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega64rfr2.pp

@@ -0,0 +1,2099 @@
+unit ATmega64RFR2;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins Address
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Port B Input Pins Address
+  DDRB: byte absolute $24;  // Port B Data Direction Register
+  PORTB: byte absolute $25;  // Port B Data Register
+  PINC: byte absolute $26;  // Port C Input Pins Address
+  DDRC: byte absolute $27;  // Port C Data Direction Register
+  PORTC: byte absolute $28;  // Port C Data Register
+  PIND: byte absolute $29;  // Port D Input Pins Address
+  DDRD: byte absolute $2A;  // Port D Data Direction Register
+  PORTD: byte absolute $2B;  // Port D Data Register
+  PINE: byte absolute $2C;  // Port E Input Pins Address
+  DDRE: byte absolute $2D;  // Port E Data Direction Register
+  PORTE: byte absolute $2E;  // Port E Data Register
+  PINF: byte absolute $2F;  // Port F Input Pins Address
+  DDRF: byte absolute $30;  // Port F Data Direction Register
+  PORTF: byte absolute $31;  // Port F Data Register
+  PING: byte absolute $32;  // Port G Input Pins Address
+  DDRG: byte absolute $33;  // Port G Data Direction Register
+  PORTG: byte absolute $34;  // Port G Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter0 Interrupt Flag Register
+  TIFR1: byte absolute $36;  // Timer/Counter1 Interrupt Flag Register
+  TIFR2: byte absolute $37;  // Timer/Counter Interrupt Flag Register
+  TIFR3: byte absolute $38;  // Timer/Counter3 Interrupt Flag Register
+  TIFR4: byte absolute $39;  // Timer/Counter4 Interrupt Flag Register
+  TIFR5: byte absolute $3A;  // Timer/Counter5 Interrupt Flag Register
+  PCIFR: byte absolute $3B;  // Pin Change Interrupt Flag Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: word absolute $41;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $41;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $42;  // EEPROM Address Register  Bytes;
+  GTCCR: byte absolute $43;  // General Timer Counter Control register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register A
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register B
+  TCNT0: byte absolute $46;  // Timer/Counter0 Register
+  OCR0A: byte absolute $47;  // Timer/Counter0 Output Compare Register
+  OCR0B: byte absolute $48;  // Timer/Counter0 Output Compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose I/O Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  ACSR: byte absolute $50;  // Analog Comparator Control And Status Register
+  OCDR: byte absolute $51;  // On-Chip Debug Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR2: byte absolute $63;  // Power Reduction Register 2
+  PRR0: byte absolute $64;  // Power Reduction Register0
+  PRR1: byte absolute $65;  // Power Reduction Register 1
+  OSCCAL: byte absolute $66;  // Oscillator Calibration Value
+  BGCR: byte absolute $67;  // Reference Voltage Calibration Register
+  PCICR: byte absolute $68;  // Pin Change Interrupt Control Register
+  EICRA: byte absolute $69;  // External Interrupt Control Register A
+  EICRB: byte absolute $6A;  // External Interrupt Control Register B
+  PCMSK0: byte absolute $6B;  // Pin Change Mask Register 0
+  PCMSK1: byte absolute $6C;  // Pin Change Mask Register 1
+  PCMSK2: byte absolute $6D;  // Pin Change Mask Register 2
+  TIMSK0: byte absolute $6E;  // Timer/Counter0 Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter1 Interrupt Mask Register
+  TIMSK2: byte absolute $70;  // Timer/Counter Interrupt Mask register
+  TIMSK3: byte absolute $71;  // Timer/Counter3 Interrupt Mask Register
+  TIMSK4: byte absolute $72;  // Timer/Counter4 Interrupt Mask Register
+  TIMSK5: byte absolute $73;  // Timer/Counter5 Interrupt Mask Register
+  NEMCR: byte absolute $75;  // Flash Extended-Mode Control-Register
+  ADCSRC: byte absolute $77;  // The ADC Control and Status Register C
+  ADC: word absolute $78;  // ADC Data Register  Bytes
+  ADCL: byte absolute $78;  // ADC Data Register  Bytes
+  ADCH: byte absolute $79;  // ADC Data Register  Bytes;
+  ADCSRA: byte absolute $7A;  // The ADC Control and Status Register A
+  ADCSRB: byte absolute $7B;  // The ADC Control and Status Register B
+  ADMUX: byte absolute $7C;  // The ADC Multiplexer Selection Register
+  DIDR2: byte absolute $7D;  // Digital Input Disable Register 2
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $7F;  // Digital Input Disable Register 1
+  TCCR1A: byte absolute $80;  // Timer/Counter1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCCR1C: byte absolute $82;  // Timer/Counter1 Control Register C
+  TCNT1: word absolute $84;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $84;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $85;  // Timer/Counter1  Bytes;
+  ICR1: word absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $86;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $87;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1A: word absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $88;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $89;  // Timer/Counter1 Output Compare Register A  Bytes;
+  OCR1B: word absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $8A;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $8B;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1C: word absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CL: byte absolute $8C;  // Timer/Counter1 Output Compare Register C  Bytes
+  OCR1CH: byte absolute $8D;  // Timer/Counter1 Output Compare Register C  Bytes;
+  TCCR3A: byte absolute $90;  // Timer/Counter3 Control Register A
+  TCCR3B: byte absolute $91;  // Timer/Counter3 Control Register B
+  TCCR3C: byte absolute $92;  // Timer/Counter3 Control Register C
+  TCNT3: word absolute $94;  // Timer/Counter3  Bytes
+  TCNT3L: byte absolute $94;  // Timer/Counter3  Bytes
+  TCNT3H: byte absolute $95;  // Timer/Counter3  Bytes;
+  ICR3: word absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3L: byte absolute $96;  // Timer/Counter3 Input Capture Register  Bytes
+  ICR3H: byte absolute $97;  // Timer/Counter3 Input Capture Register  Bytes;
+  OCR3A: word absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AL: byte absolute $98;  // Timer/Counter3 Output Compare Register A  Bytes
+  OCR3AH: byte absolute $99;  // Timer/Counter3 Output Compare Register A  Bytes;
+  OCR3B: word absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BL: byte absolute $9A;  // Timer/Counter3 Output Compare Register B  Bytes
+  OCR3BH: byte absolute $9B;  // Timer/Counter3 Output Compare Register B  Bytes;
+  OCR3C: word absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CL: byte absolute $9C;  // Timer/Counter3 Output Compare Register C  Bytes
+  OCR3CH: byte absolute $9D;  // Timer/Counter3 Output Compare Register C  Bytes;
+  TCCR4A: byte absolute $A0;  // Timer/Counter4 Control Register A
+  TCCR4B: byte absolute $A1;  // Timer/Counter4 Control Register B
+  TCCR4C: byte absolute $A2;  // Timer/Counter4 Control Register C
+  TCNT4: word absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4L: byte absolute $A4;  // Timer/Counter4  Bytes
+  TCNT4H: byte absolute $A5;  // Timer/Counter4  Bytes;
+  ICR4: word absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4L: byte absolute $A6;  // Timer/Counter4 Input Capture Register  Bytes
+  ICR4H: byte absolute $A7;  // Timer/Counter4 Input Capture Register  Bytes;
+  OCR4A: word absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AL: byte absolute $A8;  // Timer/Counter4 Output Compare Register A  Bytes
+  OCR4AH: byte absolute $A9;  // Timer/Counter4 Output Compare Register A  Bytes;
+  OCR4B: word absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BL: byte absolute $AA;  // Timer/Counter4 Output Compare Register B  Bytes
+  OCR4BH: byte absolute $AB;  // Timer/Counter4 Output Compare Register B  Bytes;
+  OCR4C: word absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CL: byte absolute $AC;  // Timer/Counter4 Output Compare Register C  Bytes
+  OCR4CH: byte absolute $AD;  // Timer/Counter4 Output Compare Register C  Bytes;
+  TCCR2A: byte absolute $B0;  // Timer/Counter2 Control Register A
+  TCCR2B: byte absolute $B1;  // Timer/Counter2 Control Register B
+  TCNT2: byte absolute $B2;  // Timer/Counter2
+  OCR2A: byte absolute $B3;  // Timer/Counter2 Output Compare Register A
+  OCR2B: byte absolute $B4;  // Timer/Counter2 Output Compare Register B
+  ASSR: byte absolute $B6;  // Asynchronous Status Register
+  TWBR: byte absolute $B8;  // TWI Bit Rate Register
+  TWSR: byte absolute $B9;  // TWI Status Register
+  TWAR: byte absolute $BA;  // TWI (Slave) Address Register
+  TWDR: byte absolute $BB;  // TWI Data Register
+  TWCR: byte absolute $BC;  // TWI Control Register
+  TWAMR: byte absolute $BD;  // TWI (Slave) Address Mask Register
+  IRQ_MASK1: byte absolute $BE;  // Transceiver Interrupt Enable Register 1
+  IRQ_STATUS1: byte absolute $BF;  // Transceiver Interrupt Status Register 1
+  UCSR0A: byte absolute $C0;  // USART0 MSPIM Control and Status Register A
+  UCSR0B: byte absolute $C1;  // USART0 MSPIM Control and Status Register B
+  UCSR0C: byte absolute $C2;  // USART0 MSPIM Control and Status Register C
+  UBRR0: word absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0L: byte absolute $C4;  // USART0 Baud Rate Register  Bytes
+  UBRR0H: byte absolute $C5;  // USART0 Baud Rate Register  Bytes;
+  UDR0: byte absolute $C6;  // USART0 I/O Data Register
+  UCSR1A: byte absolute $C8;  // USART1 MSPIM Control and Status Register A
+  UCSR1B: byte absolute $C9;  // USART1 MSPIM Control and Status Register B
+  UCSR1C: byte absolute $CA;  // USART1 MSPIM Control and Status Register C
+  UBRR1: word absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1L: byte absolute $CC;  // USART1 Baud Rate Register  Bytes
+  UBRR1H: byte absolute $CD;  // USART1 Baud Rate Register  Bytes;
+  UDR1: byte absolute $CE;  // USART1 I/O Data Register
+  SCRSTRLL: byte absolute $D7;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLH: byte absolute $D8;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRHL: byte absolute $D9;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHH: byte absolute $DA;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCCSR: byte absolute $DB;  // Symbol Counter Compare Source Register
+  SCCR0: byte absolute $DC;  // Symbol Counter Control Register 0
+  SCCR1: byte absolute $DD;  // Symbol Counter Control Register 1
+  SCSR: byte absolute $DE;  // Symbol Counter Status Register
+  SCIRQM: byte absolute $DF;  // Symbol Counter Interrupt Mask Register
+  SCIRQS: byte absolute $E0;  // Symbol Counter Interrupt Status Register
+  SCCNTLL: byte absolute $E1;  // Symbol Counter Register LL-Byte
+  SCCNTLH: byte absolute $E2;  // Symbol Counter Register LH-Byte
+  SCCNTHL: byte absolute $E3;  // Symbol Counter Register HL-Byte
+  SCCNTHH: byte absolute $E4;  // Symbol Counter Register HH-Byte
+  SCBTSRLL: byte absolute $E5;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLH: byte absolute $E6;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRHL: byte absolute $E7;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHH: byte absolute $E8;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCTSRLL: byte absolute $E9;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLH: byte absolute $EA;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRHL: byte absolute $EB;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHH: byte absolute $EC;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCOCR3LL: byte absolute $ED;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LH: byte absolute $EE;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3HL: byte absolute $EF;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HH: byte absolute $F0;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR2LL: byte absolute $F1;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LH: byte absolute $F2;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2HL: byte absolute $F3;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HH: byte absolute $F4;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR1LL: byte absolute $F5;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LH: byte absolute $F6;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1HL: byte absolute $F7;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HH: byte absolute $F8;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCTSTRLL: byte absolute $F9;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLH: byte absolute $FA;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRHL: byte absolute $FB;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHH: byte absolute $FC;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  MAFCR0: byte absolute $10C;  // Multiple Address Filter Configuration Register 0
+  MAFCR1: byte absolute $10D;  // Multiple Address Filter Configuration Register 1
+  MAFSA0L: byte absolute $10E;  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0H: byte absolute $10F;  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFPA0L: byte absolute $110;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0H: byte absolute $111;  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFSA1L: byte absolute $112;  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1H: byte absolute $113;  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFPA1L: byte absolute $114;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1H: byte absolute $115;  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFSA2L: byte absolute $116;  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2H: byte absolute $117;  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFPA2L: byte absolute $118;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2H: byte absolute $119;  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFSA3L: byte absolute $11A;  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3H: byte absolute $11B;  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFPA3L: byte absolute $11C;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3H: byte absolute $11D;  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  TCCR5A: byte absolute $120;  // Timer/Counter5 Control Register A
+  TCCR5B: byte absolute $121;  // Timer/Counter5 Control Register B
+  TCCR5C: byte absolute $122;  // Timer/Counter5 Control Register C
+  TCNT5: word absolute $124;  // Timer/Counter5  Bytes
+  TCNT5L: byte absolute $124;  // Timer/Counter5  Bytes
+  TCNT5H: byte absolute $125;  // Timer/Counter5  Bytes;
+  ICR5: word absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5L: byte absolute $126;  // Timer/Counter5 Input Capture Register  Bytes
+  ICR5H: byte absolute $127;  // Timer/Counter5 Input Capture Register  Bytes;
+  OCR5A: word absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AL: byte absolute $128;  // Timer/Counter5 Output Compare Register A  Bytes
+  OCR5AH: byte absolute $129;  // Timer/Counter5 Output Compare Register A  Bytes;
+  OCR5B: word absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BL: byte absolute $12A;  // Timer/Counter5 Output Compare Register B  Bytes
+  OCR5BH: byte absolute $12B;  // Timer/Counter5 Output Compare Register B  Bytes;
+  OCR5C: word absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CL: byte absolute $12C;  // Timer/Counter5 Output Compare Register C  Bytes
+  OCR5CH: byte absolute $12D;  // Timer/Counter5 Output Compare Register C  Bytes;
+  LLCR: byte absolute $12F;  // Low Leakage Voltage Regulator Control Register
+  LLDRL: byte absolute $130;  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRH: byte absolute $131;  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  DRTRAM3: byte absolute $132;  // Data Retention Configuration Register #3
+  DRTRAM2: byte absolute $133;  // Data Retention Configuration Register #2
+  DRTRAM1: byte absolute $134;  // Data Retention Configuration Register #1
+  DRTRAM0: byte absolute $135;  // Data Retention Configuration Register #0
+  DPDS0: byte absolute $136;  // Port Driver Strength Register 0
+  DPDS1: byte absolute $137;  // Port Driver Strength Register 1
+  PARCR: byte absolute $138;  // Power Amplifier Ramp up/down Control Register
+  TRXPR: byte absolute $139;  // Transceiver Pin Register
+  AES_CTRL: byte absolute $13C;  // AES Control Register
+  AES_STATUS: byte absolute $13D;  // AES Status Register
+  AES_STATE: byte absolute $13E;  // AES Plain and Cipher Text Buffer Register
+  AES_KEY: byte absolute $13F;  // AES Encryption and Decryption Key Buffer Register
+  TRX_STATUS: byte absolute $141;  // Transceiver Status Register
+  TRX_STATE: byte absolute $142;  // Transceiver State Control Register
+  TRX_CTRL_0: byte absolute $143;  // Reserved
+  TRX_CTRL_1: byte absolute $144;  // Transceiver Control Register 1
+  PHY_TX_PWR: byte absolute $145;  // Transceiver Transmit Power Control Register
+  PHY_RSSI: byte absolute $146;  // Receiver Signal Strength Indicator Register
+  PHY_ED_LEVEL: byte absolute $147;  // Transceiver Energy Detection Level Register
+  PHY_CC_CCA: byte absolute $148;  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CCA_THRES: byte absolute $149;  // Transceiver CCA Threshold Setting Register
+  RX_CTRL: byte absolute $14A;  // Transceiver Receive Control Register
+  SFD_VALUE: byte absolute $14B;  // Start of Frame Delimiter Value Register
+  TRX_CTRL_2: byte absolute $14C;  // Transceiver Control Register 2
+  ANT_DIV: byte absolute $14D;  // Antenna Diversity Control Register
+  IRQ_MASK: byte absolute $14E;  // Transceiver Interrupt Enable Register
+  IRQ_STATUS: byte absolute $14F;  // Transceiver Interrupt Status Register
+  VREG_CTRL: byte absolute $150;  // Voltage Regulator Control and Status Register
+  BATMON: byte absolute $151;  // Battery Monitor Control and Status Register
+  XOSC_CTRL: byte absolute $152;  // Crystal Oscillator Control Register
+  CC_CTRL_0: byte absolute $153;  // Channel Control Register 0
+  CC_CTRL_1: byte absolute $154;  // Channel Control Register 1
+  RX_SYN: byte absolute $155;  // Transceiver Receiver Sensitivity Control Register
+  TRX_RPC: byte absolute $156;  // Transceiver Reduced Power Consumption Control
+  XAH_CTRL_1: byte absolute $157;  // Transceiver Acknowledgment Frame Control Register 1
+  FTN_CTRL: byte absolute $158;  // Transceiver Filter Tuning Control Register
+  PLL_CF: byte absolute $15A;  // Transceiver Center Frequency Calibration Control Register
+  PLL_DCU: byte absolute $15B;  // Transceiver Delay Cell Calibration Control Register
+  PART_NUM: byte absolute $15C;  // Device Identification Register (Part Number)
+  VERSION_NUM: byte absolute $15D;  // Device Identification Register (Version Number)
+  MAN_ID_0: byte absolute $15E;  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_1: byte absolute $15F;  // Device Identification Register (Manufacture ID High Byte)
+  SHORT_ADDR_0: byte absolute $160;  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_1: byte absolute $161;  // Transceiver MAC Short Address Register (High Byte)
+  PAN_ID_0: byte absolute $162;  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_1: byte absolute $163;  // Transceiver Personal Area Network ID Register (High Byte)
+  IEEE_ADDR_0: byte absolute $164;  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_1: byte absolute $165;  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_2: byte absolute $166;  // Transceiver MAC IEEE Address Register 2
+  IEEE_ADDR_3: byte absolute $167;  // Transceiver MAC IEEE Address Register 3
+  IEEE_ADDR_4: byte absolute $168;  // Transceiver MAC IEEE Address Register 4
+  IEEE_ADDR_5: byte absolute $169;  // Transceiver MAC IEEE Address Register 5
+  IEEE_ADDR_6: byte absolute $16A;  // Transceiver MAC IEEE Address Register 6
+  IEEE_ADDR_7: byte absolute $16B;  // Transceiver MAC IEEE Address Register 7
+  XAH_CTRL_0: byte absolute $16C;  // Transceiver Extended Operating Mode Control Register
+  CSMA_SEED_0: byte absolute $16D;  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_1: byte absolute $16E;  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_BE: byte absolute $16F;  // Transceiver CSMA-CA Back-off Exponent Control Register
+  TST_CTRL_DIGI: byte absolute $176;  // Transceiver Digital Test Control Register
+  TST_RX_LENGTH: byte absolute $17B;  // Transceiver Received Frame Length Register
+  TRXFBST: byte absolute $180;  // Start of frame buffer
+  TRXFBEND: byte absolute $1FF;  // End of frame buffer
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // Port B Data Register
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  PB4 = $04;  
+  PB5 = $05;  
+  PB6 = $06;  
+  PB7 = $07;  
+  // Port C Data Register
+  PC0 = $00;  
+  PC1 = $01;  
+  PC2 = $02;  
+  PC3 = $03;  
+  PC4 = $04;  
+  PC5 = $05;  
+  PC6 = $06;  
+  PC7 = $07;  
+  // Port D Data Register
+  PD0 = $00;  
+  PD1 = $01;  
+  PD2 = $02;  
+  PD3 = $03;  
+  PD4 = $04;  
+  PD5 = $05;  
+  PD6 = $06;  
+  PD7 = $07;  
+  // Port E Data Register
+  PE0 = $00;  
+  PE1 = $01;  
+  PE2 = $02;  
+  PE3 = $03;  
+  PE4 = $04;  
+  PE5 = $05;  
+  PE6 = $06;  
+  PE7 = $07;  
+  // Port F Data Register
+  PF0 = $00;  
+  PF1 = $01;  
+  PF2 = $02;  
+  PF3 = $03;  
+  PF4 = $04;  
+  PF5 = $05;  
+  PF6 = $06;  
+  PF7 = $07;  
+  // Port G Data Register
+  PG0 = $00;  
+  PG1 = $01;  
+  PG2 = $02;  
+  PG3 = $03;  
+  PG4 = $04;  
+  PG5 = $05;  
+  PG6 = $06;  
+  PG7 = $07;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter1 Interrupt Flag Register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  OCF1C = $03;  
+  ICF1 = $05;  
+  // Timer/Counter Interrupt Flag Register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  // Timer/Counter3 Interrupt Flag Register
+  TOV3 = $00;  
+  OCF3A = $01;  
+  OCF3B = $02;  
+  OCF3C = $03;  
+  ICF3 = $05;  
+  // Timer/Counter4 Interrupt Flag Register
+  TOV4 = $00;  
+  OCF4A = $01;  
+  OCF4B = $02;  
+  OCF4C = $03;  
+  ICF4 = $05;  
+  // Timer/Counter5 Interrupt Flag Register
+  TOV5 = $00;  
+  OCF5A = $01;  
+  OCF5B = $02;  
+  OCF5C = $03;  
+  ICF5 = $05;  
+  // Pin Change Interrupt Flag Register
+  PCIF0 = $00;  // Pin Change Interrupt Flags
+  PCIF1 = $01;  // Pin Change Interrupt Flags
+  PCIF2 = $02;  // Pin Change Interrupt Flags
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flag
+  INTF1 = $01;  // External Interrupt Flag
+  INTF2 = $02;  // External Interrupt Flag
+  INTF3 = $03;  // External Interrupt Flag
+  INTF4 = $04;  // External Interrupt Flag
+  INTF5 = $05;  // External Interrupt Flag
+  INTF6 = $06;  // External Interrupt Flag
+  INTF7 = $07;  // External Interrupt Flag
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request Enable
+  INT1 = $01;  // External Interrupt Request Enable
+  INT2 = $02;  // External Interrupt Request Enable
+  INT3 = $03;  // External Interrupt Request Enable
+  INT4 = $04;  // External Interrupt Request Enable
+  INT5 = $05;  // External Interrupt Request Enable
+  INT6 = $06;  // External Interrupt Request Enable
+  INT7 = $07;  // External Interrupt Request Enable
+  // General Purpose IO Register 0
+  GPIOR00 = $00;  
+  GPIOR01 = $01;  
+  GPIOR02 = $02;  
+  GPIOR03 = $03;  
+  GPIOR04 = $04;  
+  GPIOR05 = $05;  
+  GPIOR06 = $06;  
+  GPIOR07 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode
+  EEPM1 = $05;  // EEPROM Programming Mode
+  // General Timer Counter Control register
+  PSRSYNC = $00;  
+  PSRASY = $01;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register A
+  WGM00 = $00;  // Waveform Generation Mode
+  WGM01 = $01;  // Waveform Generation Mode
+  COM0B0 = $04;  // Compare Match Output B Mode
+  COM0B1 = $05;  // Compare Match Output B Mode
+  COM0A0 = $06;  // Compare Match Output A Mode
+  COM0A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter0 Control Register B
+  CS00 = $00;  // Clock Select
+  CS01 = $01;  // Clock Select
+  CS02 = $02;  // Clock Select
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // General Purpose I/O Register 2
+  GPIOR20 = $00;  // General Purpose I/O Register 2 Value
+  GPIOR21 = $01;  // General Purpose I/O Register 2 Value
+  GPIOR22 = $02;  // General Purpose I/O Register 2 Value
+  GPIOR23 = $03;  // General Purpose I/O Register 2 Value
+  GPIOR24 = $04;  // General Purpose I/O Register 2 Value
+  GPIOR25 = $05;  // General Purpose I/O Register 2 Value
+  GPIOR26 = $06;  // General Purpose I/O Register 2 Value
+  GPIOR27 = $07;  // General Purpose I/O Register 2 Value
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Select 1 and 0
+  SPR1 = $01;  // SPI Clock Rate Select 1 and 0
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Analog Comparator Control And Status Register
+  ACIS0 = $00;  // Analog Comparator Interrupt Mode Select
+  ACIS1 = $01;  // Analog Comparator Interrupt Mode Select
+  ACIC = $02;  
+  ACIE = $03;  
+  ACI = $04;  
+  ACO = $05;  
+  ACBG = $06;  
+  ACD = $07;  
+  // On-Chip Debug Register
+  OCDR0 = $00;  // On-Chip Debug Register Data
+  OCDR1 = $01;  // On-Chip Debug Register Data
+  OCDR2 = $02;  // On-Chip Debug Register Data
+  OCDR3 = $03;  // On-Chip Debug Register Data
+  OCDR4 = $04;  // On-Chip Debug Register Data
+  OCDR5 = $05;  // On-Chip Debug Register Data
+  OCDR6 = $06;  // On-Chip Debug Register Data
+  OCDR7 = $07;  // On-Chip Debug Register Data
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  JTRF = $04;  
+  // MCU Control Register
+  IVCE = $00;  
+  IVSEL = $01;  
+  PUD = $04;  
+  JTD = $07;  
+  // Store Program Memory Control Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  BLBSET = $03;  
+  RWWSRE = $04;  
+  SIGRD = $05;  
+  RWWSB = $06;  
+  SPMIE = $07;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 2
+  PRRAM0 = $00;  
+  PRRAM1 = $01;  
+  PRRAM2 = $02;  
+  PRRAM3 = $03;  
+  // Power Reduction Register0
+  PRADC = $00;  
+  PRUSART0 = $01;  
+  PRSPI = $02;  
+  PRTIM1 = $03;  
+  PRPGA = $04;  
+  PRTIM0 = $05;  
+  PRTIM2 = $06;  
+  PRTWI = $07;  
+  // Power Reduction Register 1
+  PRUSART1 = $00;  
+  PRTIM3 = $03;  
+  PRTIM4 = $04;  
+  PRTIM5 = $05;  
+  PRTRX24 = $06;  
+  // Oscillator Calibration Value
+  CAL0 = $00;  // Oscillator Calibration Tuning Value
+  CAL1 = $01;  // Oscillator Calibration Tuning Value
+  CAL2 = $02;  // Oscillator Calibration Tuning Value
+  CAL3 = $03;  // Oscillator Calibration Tuning Value
+  CAL4 = $04;  // Oscillator Calibration Tuning Value
+  CAL5 = $05;  // Oscillator Calibration Tuning Value
+  CAL6 = $06;  // Oscillator Calibration Tuning Value
+  CAL7 = $07;  // Oscillator Calibration Tuning Value
+  OSCCAL0 = $00;  // Oscillator Calibration 
+  OSCCAL1 = $01;  // Oscillator Calibration 
+  OSCCAL2 = $02;  // Oscillator Calibration 
+  OSCCAL3 = $03;  // Oscillator Calibration 
+  OSCCAL4 = $04;  // Oscillator Calibration 
+  OSCCAL5 = $05;  // Oscillator Calibration 
+  OSCCAL6 = $06;  // Oscillator Calibration 
+  OSCCAL7 = $07;  // Oscillator Calibration 
+  // Reference Voltage Calibration Register
+  BGCAL0 = $00;  // Coarse Calibration Bits
+  BGCAL1 = $01;  // Coarse Calibration Bits
+  BGCAL2 = $02;  // Coarse Calibration Bits
+  BGCAL_FINE0 = $03;  // Fine Calibration Bits
+  BGCAL_FINE1 = $04;  // Fine Calibration Bits
+  BGCAL_FINE2 = $05;  // Fine Calibration Bits
+  BGCAL_FINE3 = $06;  // Fine Calibration Bits
+  // Pin Change Interrupt Control Register
+  PCIE0 = $00;  // Pin Change Interrupt Enables
+  PCIE1 = $01;  // Pin Change Interrupt Enables
+  PCIE2 = $02;  // Pin Change Interrupt Enables
+  // External Interrupt Control Register A
+  ISC00 = $00;  // External Interrupt 0 Sense Control Bit
+  ISC01 = $01;  // External Interrupt 0 Sense Control Bit
+  ISC10 = $02;  // External Interrupt 1 Sense Control Bit
+  ISC11 = $03;  // External Interrupt 1 Sense Control Bit
+  ISC20 = $04;  // External Interrupt 2 Sense Control Bit
+  ISC21 = $05;  // External Interrupt 2 Sense Control Bit
+  ISC30 = $06;  // External Interrupt 3 Sense Control Bit
+  ISC31 = $07;  // External Interrupt 3 Sense Control Bit
+  // External Interrupt Control Register B
+  ISC40 = $00;  // External Interrupt 4 Sense Control Bit
+  ISC41 = $01;  // External Interrupt 4 Sense Control Bit
+  ISC50 = $02;  // External Interrupt 5 Sense Control Bit
+  ISC51 = $03;  // External Interrupt 5 Sense Control Bit
+  ISC60 = $04;  // External Interrupt 6 Sense Control Bit
+  ISC61 = $05;  // External Interrupt 6 Sense Control Bit
+  ISC70 = $06;  // External Interrupt 7 Sense Control Bit
+  ISC71 = $07;  // External Interrupt 7 Sense Control Bit
+  // Pin Change Mask Register 2
+  PCINT16 = $00;  // Pin Change Enable Mask
+  PCINT17 = $01;  // Pin Change Enable Mask
+  PCINT18 = $02;  // Pin Change Enable Mask
+  PCINT19 = $03;  // Pin Change Enable Mask
+  PCINT20 = $04;  // Pin Change Enable Mask
+  PCINT21 = $05;  // Pin Change Enable Mask
+  PCINT22 = $06;  // Pin Change Enable Mask
+  PCINT23 = $07;  // Pin Change Enable Mask
+  // Timer/Counter0 Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  OCIE1C = $03;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Mask register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  // Timer/Counter3 Interrupt Mask Register
+  TOIE3 = $00;  
+  OCIE3A = $01;  
+  OCIE3B = $02;  
+  OCIE3C = $03;  
+  ICIE3 = $05;  
+  // Timer/Counter4 Interrupt Mask Register
+  TOIE4 = $00;  
+  OCIE4A = $01;  
+  OCIE4B = $02;  
+  OCIE4C = $03;  
+  ICIE4 = $05;  
+  // Timer/Counter5 Interrupt Mask Register
+  TOIE5 = $00;  
+  OCIE5A = $01;  
+  OCIE5B = $02;  
+  OCIE5C = $03;  
+  ICIE5 = $05;  
+  // Flash Extended-Mode Control-Register
+  AEAM0 = $04;  // Address for Extended Address Mode of Extra Rows
+  AEAM1 = $05;  // Address for Extended Address Mode of Extra Rows
+  ENEAM = $06;  
+  // The ADC Control and Status Register C
+  ADSUT0 = $00;  // ADC Start-up Time
+  ADSUT1 = $01;  // ADC Start-up Time
+  ADSUT2 = $02;  // ADC Start-up Time
+  ADSUT3 = $03;  // ADC Start-up Time
+  ADSUT4 = $04;  // ADC Start-up Time
+  ADTHT0 = $06;  // ADC Track-and-Hold Time
+  ADTHT1 = $07;  // ADC Track-and-Hold Time
+  // The ADC Control and Status Register A
+  ADPS0 = $00;  // ADC  Prescaler Select Bits
+  ADPS1 = $01;  // ADC  Prescaler Select Bits
+  ADPS2 = $02;  // ADC  Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Source
+  ADTS1 = $01;  // ADC Auto Trigger Source
+  ADTS2 = $02;  // ADC Auto Trigger Source
+  MUX5 = $03;  
+  ACCH = $04;  
+  REFOK = $05;  
+  ACME = $06;  
+  AVDDOK = $07;  
+  // The ADC Multiplexer Selection Register
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  ADLAR = $05;  
+  REFS0 = $06;  // Reference Selection Bits
+  REFS1 = $07;  // Reference Selection Bits
+  // Digital Input Disable Register 2
+  ADC8D = $00;  
+  ADC9D = $01;  
+  ADC10D = $02;  
+  ADC11D = $03;  
+  ADC12D = $04;  
+  ADC13D = $05;  
+  ADC14D = $06;  
+  ADC15D = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  AIN0D = $00;  
+  AIN1D = $01;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Waveform Generation Mode
+  WGM11 = $01;  // Waveform Generation Mode
+  COM1C0 = $02;  // Compare Output Mode for Channel C
+  COM1C1 = $03;  // Compare Output Mode for Channel C
+  COM1B0 = $04;  // Compare Output Mode for Channel B
+  COM1B1 = $05;  // Compare Output Mode for Channel B
+  COM1A0 = $06;  // Compare Output Mode for Channel A
+  COM1A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select
+  CS11 = $01;  // Clock Select
+  CS12 = $02;  // Clock Select
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1C = $05;  
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // Timer/Counter3 Control Register A
+  WGM30 = $00;  // Waveform Generation Mode
+  WGM31 = $01;  // Waveform Generation Mode
+  COM3C0 = $02;  // Compare Output Mode for Channel C
+  COM3C1 = $03;  // Compare Output Mode for Channel C
+  COM3B0 = $04;  // Compare Output Mode for Channel B
+  COM3B1 = $05;  // Compare Output Mode for Channel B
+  COM3A0 = $06;  // Compare Output Mode for Channel A
+  COM3A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter3 Control Register B
+  CS30 = $00;  // Clock Select
+  CS31 = $01;  // Clock Select
+  CS32 = $02;  // Clock Select
+  ICES3 = $06;  
+  ICNC3 = $07;  
+  // Timer/Counter3 Control Register C
+  FOC3C = $05;  
+  FOC3B = $06;  
+  FOC3A = $07;  
+  // Timer/Counter4 Control Register A
+  WGM40 = $00;  // Waveform Generation Mode
+  WGM41 = $01;  // Waveform Generation Mode
+  COM4C0 = $02;  // Compare Output Mode for Channel C
+  COM4C1 = $03;  // Compare Output Mode for Channel C
+  COM4B0 = $04;  // Compare Output Mode for Channel B
+  COM4B1 = $05;  // Compare Output Mode for Channel B
+  COM4A0 = $06;  // Compare Output Mode for Channel A
+  COM4A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter4 Control Register B
+  CS40 = $00;  // Clock Select
+  CS41 = $01;  // Clock Select
+  CS42 = $02;  // Clock Select
+  ICES4 = $06;  
+  ICNC4 = $07;  
+  // Timer/Counter4 Control Register C
+  FOC4C = $05;  
+  FOC4B = $06;  
+  FOC4A = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Waveform Generation Mode
+  WGM21 = $01;  // Waveform Generation Mode
+  COM2B0 = $04;  // Compare Match Output B Mode
+  COM2B1 = $05;  // Compare Match Output B Mode
+  COM2A0 = $06;  // Compare Match Output A Mode
+  COM2A1 = $07;  // Compare Match Output A Mode
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select
+  CS21 = $01;  // Clock Select
+  CS22 = $02;  // Clock Select
+  WGM22 = $03;  
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Asynchronous Status Register
+  TCR2BUB = $00;  
+  TCR2AUB = $01;  
+  OCR2BUB = $02;  
+  OCR2AUB = $03;  
+  TCN2UB = $04;  
+  AS2 = $05;  
+  EXCLK = $06;  
+  EXCLKAMR = $07;  
+  // TWI Status Register
+  TWPS0 = $00;  // TWI Prescaler Bits
+  TWPS1 = $01;  // TWI Prescaler Bits
+  TWS3 = $03;  // TWI Status
+  TWS4 = $04;  // TWI Status
+  TWS5 = $05;  // TWI Status
+  TWS6 = $06;  // TWI Status
+  TWS7 = $07;  // TWI Status
+  // TWI (Slave) Address Register
+  TWGCE = $00;  
+  TWA0 = $01;  // TWI (Slave) Address
+  TWA1 = $02;  // TWI (Slave) Address
+  TWA2 = $03;  // TWI (Slave) Address
+  TWA3 = $04;  // TWI (Slave) Address
+  TWA4 = $05;  // TWI (Slave) Address
+  TWA5 = $06;  // TWI (Slave) Address
+  TWA6 = $07;  // TWI (Slave) Address
+  // TWI Control Register
+  TWIE = $00;  
+  TWEN = $02;  
+  TWWC = $03;  
+  TWSTO = $04;  
+  TWSTA = $05;  
+  TWEA = $06;  
+  TWINT = $07;  
+  // TWI (Slave) Address Mask Register
+  TWAM0 = $01;  // TWI Address Mask
+  TWAM1 = $02;  // TWI Address Mask
+  TWAM2 = $03;  // TWI Address Mask
+  TWAM3 = $04;  // TWI Address Mask
+  TWAM4 = $05;  // TWI Address Mask
+  TWAM5 = $06;  // TWI Address Mask
+  TWAM6 = $07;  // TWI Address Mask
+  // Transceiver Interrupt Enable Register 1
+  TX_START_EN = $00;  
+  MAF_0_AMI_EN = $01;  
+  MAF_1_AMI_EN = $02;  
+  MAF_2_AMI_EN = $03;  
+  MAF_3_AMI_EN = $04;  
+  // Transceiver Interrupt Status Register 1
+  TX_START = $00;  
+  MAF_0_AMI = $01;  
+  MAF_1_AMI = $02;  
+  MAF_2_AMI = $03;  
+  MAF_3_AMI = $04;  
+  // USART0 MSPIM Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART0 MSPIM Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART0 MSPIM Control and Status Register C
+  UCPOL0 = $00;  
+  UCPHA0 = $01;  
+  UDORD0 = $02;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode
+  UPM01 = $05;  // Parity Mode
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART1 MSPIM Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // USART1 MSPIM Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART1 MSPIM Control and Status Register C
+  UCPOL1 = $00;  
+  UCPHA1 = $01;  
+  UDORD1 = $02;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode
+  UPM11 = $05;  // Parity Mode
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL0 = $00;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL1 = $01;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL2 = $02;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL3 = $03;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL4 = $04;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL5 = $05;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL6 = $06;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  SCRSTRLL7 = $07;  // Symbol Counter Received Frame Timestamp Register LL-Byte
+  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH0 = $00;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH1 = $01;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH2 = $02;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH3 = $03;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH4 = $04;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH5 = $05;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH6 = $06;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  SCRSTRLH7 = $07;  // Symbol Counter Received Frame Timestamp Register LH-Byte
+  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL0 = $00;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL1 = $01;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL2 = $02;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL3 = $03;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL4 = $04;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL5 = $05;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL6 = $06;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  SCRSTRHL7 = $07;  // Symbol Counter Received Frame Timestamp Register HL-Byte
+  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH0 = $00;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH1 = $01;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH2 = $02;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH3 = $03;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH4 = $04;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH5 = $05;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH6 = $06;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  SCRSTRHH7 = $07;  // Symbol Counter Received Frame Timestamp Register HH-Byte
+  // Symbol Counter Compare Source Register
+  SCCS10 = $00;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS11 = $01;  // Symbol Counter Compare Source select register for Compare Units
+  SCCS20 = $02;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS21 = $03;  // Symbol Counter Compare Source select register for Compare Unit 2
+  SCCS30 = $04;  // Symbol Counter Compare Source select register for Compare Unit 3
+  SCCS31 = $05;  // Symbol Counter Compare Source select register for Compare Unit 3
+  // Symbol Counter Control Register 0
+  SCCMP1 = $00;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP2 = $01;  // Symbol Counter Compare Unit 3 Mode select
+  SCCMP3 = $02;  // Symbol Counter Compare Unit 3 Mode select
+  SCTSE = $03;  
+  SCCKSEL = $04;  
+  SCEN = $05;  
+  SCMBTS = $06;  
+  SCRES = $07;  
+  // Symbol Counter Control Register 1
+  SCENBO = $00;  
+  SCEECLK = $01;  
+  SCCKDIV0 = $02;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV1 = $03;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCCKDIV2 = $04;  // Clock divider for synchronous clock source (16MHz Transceiver Clock)
+  SCBTSM = $05;  
+  Res5 = $06;  // Reserved Bit
+  Res6 = $07;  // Reserved Bit
+  // Symbol Counter Status Register
+  SCBSY = $00;  
+  // Symbol Counter Interrupt Mask Register
+  IRQMCP1 = $00;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP2 = $01;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMCP3 = $02;  // Symbol Counter Compare Match 3 IRQ enable
+  IRQMOF = $03;  
+  IRQMBO = $04;  
+  // Symbol Counter Interrupt Status Register
+  IRQSCP1 = $00;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP2 = $01;  // Compare Unit 3 Compare Match IRQ
+  IRQSCP3 = $02;  // Compare Unit 3 Compare Match IRQ
+  IRQSOF = $03;  
+  IRQSBO = $04;  
+  // Symbol Counter Register LL-Byte
+  SCCNTLL0 = $00;  // Symbol Counter Register LL-Byte
+  SCCNTLL1 = $01;  // Symbol Counter Register LL-Byte
+  SCCNTLL2 = $02;  // Symbol Counter Register LL-Byte
+  SCCNTLL3 = $03;  // Symbol Counter Register LL-Byte
+  SCCNTLL4 = $04;  // Symbol Counter Register LL-Byte
+  SCCNTLL5 = $05;  // Symbol Counter Register LL-Byte
+  SCCNTLL6 = $06;  // Symbol Counter Register LL-Byte
+  SCCNTLL7 = $07;  // Symbol Counter Register LL-Byte
+  // Symbol Counter Register LH-Byte
+  SCCNTLH0 = $00;  // Symbol Counter Register LH-Byte
+  SCCNTLH1 = $01;  // Symbol Counter Register LH-Byte
+  SCCNTLH2 = $02;  // Symbol Counter Register LH-Byte
+  SCCNTLH3 = $03;  // Symbol Counter Register LH-Byte
+  SCCNTLH4 = $04;  // Symbol Counter Register LH-Byte
+  SCCNTLH5 = $05;  // Symbol Counter Register LH-Byte
+  SCCNTLH6 = $06;  // Symbol Counter Register LH-Byte
+  SCCNTLH7 = $07;  // Symbol Counter Register LH-Byte
+  // Symbol Counter Register HL-Byte
+  SCCNTHL0 = $00;  // Symbol Counter Register HL-Byte
+  SCCNTHL1 = $01;  // Symbol Counter Register HL-Byte
+  SCCNTHL2 = $02;  // Symbol Counter Register HL-Byte
+  SCCNTHL3 = $03;  // Symbol Counter Register HL-Byte
+  SCCNTHL4 = $04;  // Symbol Counter Register HL-Byte
+  SCCNTHL5 = $05;  // Symbol Counter Register HL-Byte
+  SCCNTHL6 = $06;  // Symbol Counter Register HL-Byte
+  SCCNTHL7 = $07;  // Symbol Counter Register HL-Byte
+  // Symbol Counter Register HH-Byte
+  SCCNTHH0 = $00;  // Symbol Counter Register HH-Byte
+  SCCNTHH1 = $01;  // Symbol Counter Register HH-Byte
+  SCCNTHH2 = $02;  // Symbol Counter Register HH-Byte
+  SCCNTHH3 = $03;  // Symbol Counter Register HH-Byte
+  SCCNTHH4 = $04;  // Symbol Counter Register HH-Byte
+  SCCNTHH5 = $05;  // Symbol Counter Register HH-Byte
+  SCCNTHH6 = $06;  // Symbol Counter Register HH-Byte
+  SCCNTHH7 = $07;  // Symbol Counter Register HH-Byte
+  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL0 = $00;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL1 = $01;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL2 = $02;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL3 = $03;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL4 = $04;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL5 = $05;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL6 = $06;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  SCBTSRLL7 = $07;  // Symbol Counter Beacon Timestamp Register LL-Byte
+  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH0 = $00;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH1 = $01;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH2 = $02;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH3 = $03;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH4 = $04;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH5 = $05;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH6 = $06;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  SCBTSRLH7 = $07;  // Symbol Counter Beacon Timestamp Register LH-Byte
+  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL0 = $00;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL1 = $01;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL2 = $02;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL3 = $03;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL4 = $04;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL5 = $05;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL6 = $06;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  SCBTSRHL7 = $07;  // Symbol Counter Beacon Timestamp Register HL-Byte
+  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH0 = $00;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH1 = $01;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH2 = $02;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH3 = $03;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH4 = $04;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH5 = $05;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH6 = $06;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  SCBTSRHH7 = $07;  // Symbol Counter Beacon Timestamp Register HH-Byte
+  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL0 = $00;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL1 = $01;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL2 = $02;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL3 = $03;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL4 = $04;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL5 = $05;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL6 = $06;  // Symbol Counter Frame Timestamp Register LL-Byte
+  SCTSRLL7 = $07;  // Symbol Counter Frame Timestamp Register LL-Byte
+  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH0 = $00;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH1 = $01;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH2 = $02;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH3 = $03;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH4 = $04;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH5 = $05;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH6 = $06;  // Symbol Counter Frame Timestamp Register LH-Byte
+  SCTSRLH7 = $07;  // Symbol Counter Frame Timestamp Register LH-Byte
+  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL0 = $00;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL1 = $01;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL2 = $02;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL3 = $03;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL4 = $04;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL5 = $05;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL6 = $06;  // Symbol Counter Frame Timestamp Register HL-Byte
+  SCTSRHL7 = $07;  // Symbol Counter Frame Timestamp Register HL-Byte
+  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH0 = $00;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH1 = $01;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH2 = $02;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH3 = $03;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH4 = $04;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH5 = $05;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH6 = $06;  // Symbol Counter Frame Timestamp Register HH-Byte
+  SCTSRHH7 = $07;  // Symbol Counter Frame Timestamp Register HH-Byte
+  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL0 = $00;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL1 = $01;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL2 = $02;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL3 = $03;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL4 = $04;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL5 = $05;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL6 = $06;  // Symbol Counter Output Compare Register 3 LL-Byte
+  SCOCR3LL7 = $07;  // Symbol Counter Output Compare Register 3 LL-Byte
+  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH0 = $00;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH1 = $01;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH2 = $02;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH3 = $03;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH4 = $04;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH5 = $05;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH6 = $06;  // Symbol Counter Output Compare Register 3 LH-Byte
+  SCOCR3LH7 = $07;  // Symbol Counter Output Compare Register 3 LH-Byte
+  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL0 = $00;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL1 = $01;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL2 = $02;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL3 = $03;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL4 = $04;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL5 = $05;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL6 = $06;  // Symbol Counter Output Compare Register 3 HL-Byte
+  SCOCR3HL7 = $07;  // Symbol Counter Output Compare Register 3 HL-Byte
+  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH0 = $00;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH1 = $01;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH2 = $02;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH3 = $03;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH4 = $04;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH5 = $05;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH6 = $06;  // Symbol Counter Output Compare Register 3 HH-Byte
+  SCOCR3HH7 = $07;  // Symbol Counter Output Compare Register 3 HH-Byte
+  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL0 = $00;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL1 = $01;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL2 = $02;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL3 = $03;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL4 = $04;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL5 = $05;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL6 = $06;  // Symbol Counter Output Compare Register 2 LL-Byte
+  SCOCR2LL7 = $07;  // Symbol Counter Output Compare Register 2 LL-Byte
+  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH0 = $00;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH1 = $01;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH2 = $02;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH3 = $03;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH4 = $04;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH5 = $05;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH6 = $06;  // Symbol Counter Output Compare Register 2 LH-Byte
+  SCOCR2LH7 = $07;  // Symbol Counter Output Compare Register 2 LH-Byte
+  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL0 = $00;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL1 = $01;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL2 = $02;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL3 = $03;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL4 = $04;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL5 = $05;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL6 = $06;  // Symbol Counter Output Compare Register 2 HL-Byte
+  SCOCR2HL7 = $07;  // Symbol Counter Output Compare Register 2 HL-Byte
+  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH0 = $00;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH1 = $01;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH2 = $02;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH3 = $03;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH4 = $04;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH5 = $05;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH6 = $06;  // Symbol Counter Output Compare Register 2 HH-Byte
+  SCOCR2HH7 = $07;  // Symbol Counter Output Compare Register 2 HH-Byte
+  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL0 = $00;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL1 = $01;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL2 = $02;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL3 = $03;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL4 = $04;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL5 = $05;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL6 = $06;  // Symbol Counter Output Compare Register 1 LL-Byte
+  SCOCR1LL7 = $07;  // Symbol Counter Output Compare Register 1 LL-Byte
+  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH0 = $00;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH1 = $01;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH2 = $02;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH3 = $03;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH4 = $04;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH5 = $05;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH6 = $06;  // Symbol Counter Output Compare Register 1 LH-Byte
+  SCOCR1LH7 = $07;  // Symbol Counter Output Compare Register 1 LH-Byte
+  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL0 = $00;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL1 = $01;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL2 = $02;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL3 = $03;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL4 = $04;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL5 = $05;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL6 = $06;  // Symbol Counter Output Compare Register 1 HL-Byte
+  SCOCR1HL7 = $07;  // Symbol Counter Output Compare Register 1 HL-Byte
+  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH0 = $00;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH1 = $01;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH2 = $02;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH3 = $03;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH4 = $04;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH5 = $05;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH6 = $06;  // Symbol Counter Output Compare Register 1 HH-Byte
+  SCOCR1HH7 = $07;  // Symbol Counter Output Compare Register 1 HH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  SCTSTRLL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  SCTSTRLH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register LH-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  SCTSTRHL7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HL-Byte
+  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH0 = $00;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH1 = $01;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH2 = $02;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH3 = $03;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH4 = $04;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH5 = $05;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH6 = $06;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  SCTSTRHH7 = $07;  // Symbol Counter Transmit Frame Timestamp Register HH-Byte
+  // Multiple Address Filter Configuration Register 0
+  MAF0EN = $00;  
+  MAF1EN = $01;  
+  MAF2EN = $02;  
+  MAF3EN = $03;  
+  // Multiple Address Filter Configuration Register 1
+  AACK_0_I_AM_COORD = $00;  
+  AACK_0_SET_PD = $01;  
+  AACK_1_I_AM_COORD = $02;  
+  AACK_1_SET_PD = $03;  
+  AACK_2_I_AM_COORD = $04;  
+  AACK_2_SET_PD = $05;  
+  AACK_3_I_AM_COORD = $06;  
+  AACK_3_SET_PD = $07;  
+  // Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)
+  MAFSA0L0 = $00;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L1 = $01;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L2 = $02;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L3 = $03;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L4 = $04;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L5 = $05;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L6 = $06;  // MAC Short Address low Byte for Frame Filter 0
+  MAFSA0L7 = $07;  // MAC Short Address low Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)
+  MAFSA0H0 = $00;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H1 = $01;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H2 = $02;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H3 = $03;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H4 = $04;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H5 = $05;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H6 = $06;  // MAC Short Address high Byte for Frame Filter 0
+  MAFSA0H7 = $07;  // MAC Short Address high Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)
+  MAFPA0L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  MAFPA0L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 0
+  // Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)
+  MAFPA0H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  MAFPA0H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 0
+  // Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)
+  MAFSA1L0 = $00;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L1 = $01;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L2 = $02;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L3 = $03;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L4 = $04;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L5 = $05;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L6 = $06;  // MAC Short Address low Byte for Frame Filter 1
+  MAFSA1L7 = $07;  // MAC Short Address low Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)
+  MAFSA1H0 = $00;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H1 = $01;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H2 = $02;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H3 = $03;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H4 = $04;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H5 = $05;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H6 = $06;  // MAC Short Address high Byte for Frame Filter 1
+  MAFSA1H7 = $07;  // MAC Short Address high Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)
+  MAFPA1L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  MAFPA1L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 1
+  // Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)
+  MAFPA1H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  MAFPA1H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 1
+  // Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)
+  MAFSA2L0 = $00;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L1 = $01;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L2 = $02;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L3 = $03;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L4 = $04;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L5 = $05;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L6 = $06;  // MAC Short Address low Byte for Frame Filter 2
+  MAFSA2L7 = $07;  // MAC Short Address low Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)
+  MAFSA2H0 = $00;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H1 = $01;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H2 = $02;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H3 = $03;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H4 = $04;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H5 = $05;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H6 = $06;  // MAC Short Address high Byte for Frame Filter 2
+  MAFSA2H7 = $07;  // MAC Short Address high Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)
+  MAFPA2L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  MAFPA2L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 2
+  // Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)
+  MAFPA2H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  MAFPA2H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 2
+  // Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)
+  MAFSA3L0 = $00;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L1 = $01;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L2 = $02;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L3 = $03;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L4 = $04;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L5 = $05;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L6 = $06;  // MAC Short Address low Byte for Frame Filter 3
+  MAFSA3L7 = $07;  // MAC Short Address low Byte for Frame Filter 3
+  // Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)
+  MAFSA3H0 = $00;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H1 = $01;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H2 = $02;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H3 = $03;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H4 = $04;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H5 = $05;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H6 = $06;  // MAC Short Address high Byte for Frame Filter 3
+  MAFSA3H7 = $07;  // MAC Short Address high Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)
+  MAFPA3L0 = $00;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L1 = $01;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L2 = $02;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L3 = $03;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L4 = $04;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L5 = $05;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L6 = $06;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  MAFPA3L7 = $07;  // MAC Personal Area Network ID low Byte for Frame Filter 3
+  // Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)
+  MAFPA3H0 = $00;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H1 = $01;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H2 = $02;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H3 = $03;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H4 = $04;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H5 = $05;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H6 = $06;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  MAFPA3H7 = $07;  // MAC Personal Area Network ID high Byte for Frame Filter 3
+  // Timer/Counter5 Control Register A
+  WGM50 = $00;  // Waveform Generation Mode
+  WGM51 = $01;  // Waveform Generation Mode
+  COM5C0 = $02;  // Compare Output Mode for Channel C
+  COM5C1 = $03;  // Compare Output Mode for Channel C
+  COM5B0 = $04;  // Compare Output Mode for Channel B
+  COM5B1 = $05;  // Compare Output Mode for Channel B
+  COM5A0 = $06;  // Compare Output Mode for Channel A
+  COM5A1 = $07;  // Compare Output Mode for Channel A
+  // Timer/Counter5 Control Register B
+  CS50 = $00;  // Clock Select
+  CS51 = $01;  // Clock Select
+  CS52 = $02;  // Clock Select
+  ICES5 = $06;  
+  ICNC5 = $07;  
+  // Timer/Counter5 Control Register C
+  FOC5C = $05;  
+  FOC5B = $06;  
+  FOC5A = $07;  
+  // Low Leakage Voltage Regulator Control Register
+  LLENCAL = $00;  
+  LLSHORT = $01;  
+  LLTCO = $02;  
+  LLCAL = $03;  
+  LLCOMP = $04;  
+  LLDONE = $05;  
+  // Low Leakage Voltage Regulator Data Register (Low-Byte)
+  LLDRL0 = $00;  // Low-Byte Data Register Bits
+  LLDRL1 = $01;  // Low-Byte Data Register Bits
+  LLDRL2 = $02;  // Low-Byte Data Register Bits
+  LLDRL3 = $03;  // Low-Byte Data Register Bits
+  // Low Leakage Voltage Regulator Data Register (High-Byte)
+  LLDRH0 = $00;  // High-Byte Data Register Bits
+  LLDRH1 = $01;  // High-Byte Data Register Bits
+  LLDRH2 = $02;  // High-Byte Data Register Bits
+  LLDRH3 = $03;  // High-Byte Data Register Bits
+  LLDRH4 = $04;  // High-Byte Data Register Bits
+  // Data Retention Configuration Register #0
+  ENDRT = $04;  
+  DRTSWOK = $05;  
+  // Port Driver Strength Register 0
+  PBDRV0 = $00;  // Driver Strength Port B
+  PBDRV1 = $01;  // Driver Strength Port B
+  PDDRV0 = $02;  // Driver Strength Port D
+  PDDRV1 = $03;  // Driver Strength Port D
+  PEDRV0 = $04;  // Driver Strength Port E
+  PEDRV1 = $05;  // Driver Strength Port E
+  PFDRV0 = $06;  // Driver Strength Port F
+  PFDRV1 = $07;  // Driver Strength Port F
+  // Port Driver Strength Register 1
+  PGDRV0 = $00;  // Driver Strength Port G
+  PGDRV1 = $01;  // Driver Strength Port G
+  // Power Amplifier Ramp up/down Control Register
+  PARUFI = $00;  
+  PARDFI = $01;  
+  PALTU0 = $02;  // ext. PA Ramp Up Lead Time
+  PALTU1 = $03;  // ext. PA Ramp Up Lead Time
+  PALTU2 = $04;  // ext. PA Ramp Up Lead Time
+  PALTD0 = $05;  // ext. PA Ramp Down Lead Time
+  PALTD1 = $06;  // ext. PA Ramp Down Lead Time
+  PALTD2 = $07;  // ext. PA Ramp Down Lead Time
+  // Transceiver Pin Register
+  TRXRST = $00;  
+  SLPTR = $01;  
+  // AES Control Register
+  AES_IM = $02;  
+  AES_DIR = $03;  
+  AES_MODE = $05;  
+  AES_REQUEST = $07;  
+  // AES Status Register
+  AES_DONE = $00;  
+  AES_ER = $07;  
+  // AES Plain and Cipher Text Buffer Register
+  AES_STATE0 = $00;  // AES Plain and Cipher Text Buffer
+  AES_STATE1 = $01;  // AES Plain and Cipher Text Buffer
+  AES_STATE2 = $02;  // AES Plain and Cipher Text Buffer
+  AES_STATE3 = $03;  // AES Plain and Cipher Text Buffer
+  AES_STATE4 = $04;  // AES Plain and Cipher Text Buffer
+  AES_STATE5 = $05;  // AES Plain and Cipher Text Buffer
+  AES_STATE6 = $06;  // AES Plain and Cipher Text Buffer
+  AES_STATE7 = $07;  // AES Plain and Cipher Text Buffer
+  // AES Encryption and Decryption Key Buffer Register
+  AES_KEY0 = $00;  // AES Encryption/Decryption Key Buffer
+  AES_KEY1 = $01;  // AES Encryption/Decryption Key Buffer
+  AES_KEY2 = $02;  // AES Encryption/Decryption Key Buffer
+  AES_KEY3 = $03;  // AES Encryption/Decryption Key Buffer
+  AES_KEY4 = $04;  // AES Encryption/Decryption Key Buffer
+  AES_KEY5 = $05;  // AES Encryption/Decryption Key Buffer
+  AES_KEY6 = $06;  // AES Encryption/Decryption Key Buffer
+  AES_KEY7 = $07;  // AES Encryption/Decryption Key Buffer
+  // Transceiver Status Register
+  TRX_STATUS0 = $00;  // Transceiver Main Status
+  TRX_STATUS1 = $01;  // Transceiver Main Status
+  TRX_STATUS2 = $02;  // Transceiver Main Status
+  TRX_STATUS3 = $03;  // Transceiver Main Status
+  TRX_STATUS4 = $04;  // Transceiver Main Status
+  TST_STATUS = $05;  
+  CCA_STATUS = $06;  
+  CCA_DONE = $07;  
+  // Transceiver State Control Register
+  TRX_CMD0 = $00;  // State Control Command
+  TRX_CMD1 = $01;  // State Control Command
+  TRX_CMD2 = $02;  // State Control Command
+  TRX_CMD3 = $03;  // State Control Command
+  TRX_CMD4 = $04;  // State Control Command
+  TRAC_STATUS0 = $05;  // Transaction Status
+  TRAC_STATUS1 = $06;  // Transaction Status
+  TRAC_STATUS2 = $07;  // Transaction Status
+  // Reserved
+  PMU_IF_INV = $04;  
+  PMU_START = $05;  
+  PMU_EN = $06;  
+  Res7 = $07;  
+  // Transceiver Control Register 1
+  PLL_TX_FLT = $04;  
+  TX_AUTO_CRC_ON = $05;  
+  IRQ_2_EXT_EN = $06;  
+  PA_EXT_EN = $07;  
+  // Transceiver Transmit Power Control Register
+  TX_PWR0 = $00;  // Transmit Power Setting
+  TX_PWR1 = $01;  // Transmit Power Setting
+  TX_PWR2 = $02;  // Transmit Power Setting
+  TX_PWR3 = $03;  // Transmit Power Setting
+  // Receiver Signal Strength Indicator Register
+  RSSI0 = $00;  // Receiver Signal Strength Indicator
+  RSSI1 = $01;  // Receiver Signal Strength Indicator
+  RSSI2 = $02;  // Receiver Signal Strength Indicator
+  RSSI3 = $03;  // Receiver Signal Strength Indicator
+  RSSI4 = $04;  // Receiver Signal Strength Indicator
+  RND_VALUE0 = $05;  // Random Value
+  RND_VALUE1 = $06;  // Random Value
+  RX_CRC_VALID = $07;  
+  // Transceiver Energy Detection Level Register
+  ED_LEVEL0 = $00;  // Energy Detection Level
+  ED_LEVEL1 = $01;  // Energy Detection Level
+  ED_LEVEL2 = $02;  // Energy Detection Level
+  ED_LEVEL3 = $03;  // Energy Detection Level
+  ED_LEVEL4 = $04;  // Energy Detection Level
+  ED_LEVEL5 = $05;  // Energy Detection Level
+  ED_LEVEL6 = $06;  // Energy Detection Level
+  ED_LEVEL7 = $07;  // Energy Detection Level
+  // Transceiver Clear Channel Assessment (CCA) Control Register
+  CHANNEL0 = $00;  // RX/TX Channel Selection
+  CHANNEL1 = $01;  // RX/TX Channel Selection
+  CHANNEL2 = $02;  // RX/TX Channel Selection
+  CHANNEL3 = $03;  // RX/TX Channel Selection
+  CHANNEL4 = $04;  // RX/TX Channel Selection
+  CCA_MODE0 = $05;  // Select CCA Measurement Mode
+  CCA_MODE1 = $06;  // Select CCA Measurement Mode
+  CCA_REQUEST = $07;  
+  // Transceiver CCA Threshold Setting Register
+  CCA_ED_THRES0 = $00;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES1 = $01;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES2 = $02;  // ED Threshold Level for CCA Measurement
+  CCA_ED_THRES3 = $03;  // ED Threshold Level for CCA Measurement
+  CCA_CS_THRES0 = $04;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES1 = $05;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES2 = $06;  // CS Threshold Level for CCA Measurement
+  CCA_CS_THRES3 = $07;  // CS Threshold Level for CCA Measurement
+  // Transceiver Receive Control Register
+  PDT_THRES0 = $00;  // Receiver Sensitivity Control
+  PDT_THRES1 = $01;  // Receiver Sensitivity Control
+  PDT_THRES2 = $02;  // Receiver Sensitivity Control
+  PDT_THRES3 = $03;  // Receiver Sensitivity Control
+  // Start of Frame Delimiter Value Register
+  SFD_VALUE0 = $00;  // Start of Frame Delimiter Value
+  SFD_VALUE1 = $01;  // Start of Frame Delimiter Value
+  SFD_VALUE2 = $02;  // Start of Frame Delimiter Value
+  SFD_VALUE3 = $03;  // Start of Frame Delimiter Value
+  SFD_VALUE4 = $04;  // Start of Frame Delimiter Value
+  SFD_VALUE5 = $05;  // Start of Frame Delimiter Value
+  SFD_VALUE6 = $06;  // Start of Frame Delimiter Value
+  SFD_VALUE7 = $07;  // Start of Frame Delimiter Value
+  // Transceiver Control Register 2
+  OQPSK_DATA_RATE0 = $00;  // Data Rate Selection
+  OQPSK_DATA_RATE1 = $01;  // Data Rate Selection
+  RX_SAFE_MODE = $07;  
+  // Antenna Diversity Control Register
+  ANT_CTRL0 = $00;  // Static Antenna Diversity Switch Control
+  ANT_CTRL1 = $01;  // Static Antenna Diversity Switch Control
+  ANT_EXT_SW_EN = $02;  
+  ANT_DIV_EN = $03;  
+  ANT_SEL = $07;  
+  // Transceiver Interrupt Enable Register
+  PLL_LOCK_EN = $00;  
+  PLL_UNLOCK_EN = $01;  
+  RX_START_EN = $02;  
+  RX_END_EN = $03;  
+  CCA_ED_DONE_EN = $04;  
+  AMI_EN = $05;  
+  TX_END_EN = $06;  
+  AWAKE_EN = $07;  
+  // Transceiver Interrupt Status Register
+  PLL_LOCK = $00;  
+  PLL_UNLOCK = $01;  
+  RX_START = $02;  
+  RX_END = $03;  
+  CCA_ED_DONE = $04;  
+  AMI = $05;  
+  TX_END = $06;  
+  AWAKE = $07;  
+  // Voltage Regulator Control and Status Register
+  DVDD_OK = $02;  
+  DVREG_EXT = $03;  
+  AVDD_OK = $06;  
+  AVREG_EXT = $07;  
+  // Battery Monitor Control and Status Register
+  BATMON_VTH0 = $00;  // Battery Monitor Threshold Voltage
+  BATMON_VTH1 = $01;  // Battery Monitor Threshold Voltage
+  BATMON_VTH2 = $02;  // Battery Monitor Threshold Voltage
+  BATMON_VTH3 = $03;  // Battery Monitor Threshold Voltage
+  BATMON_HR = $04;  
+  BATMON_OK = $05;  
+  BAT_LOW_EN = $06;  
+  BAT_LOW = $07;  
+  // Crystal Oscillator Control Register
+  XTAL_TRIM0 = $00;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM1 = $01;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM2 = $02;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_TRIM3 = $03;  // Crystal Oscillator Load Capacitance Trimming
+  XTAL_MODE0 = $04;  // Crystal Oscillator Operating Mode
+  XTAL_MODE1 = $05;  // Crystal Oscillator Operating Mode
+  XTAL_MODE2 = $06;  // Crystal Oscillator Operating Mode
+  XTAL_MODE3 = $07;  // Crystal Oscillator Operating Mode
+  // Channel Control Register 0
+  CC_NUMBER0 = $00;  // Channel Number
+  CC_NUMBER1 = $01;  // Channel Number
+  CC_NUMBER2 = $02;  // Channel Number
+  CC_NUMBER3 = $03;  // Channel Number
+  CC_NUMBER4 = $04;  // Channel Number
+  CC_NUMBER5 = $05;  // Channel Number
+  CC_NUMBER6 = $06;  // Channel Number
+  CC_NUMBER7 = $07;  // Channel Number
+  // Channel Control Register 1
+  CC_BAND0 = $00;  // Channel Band
+  CC_BAND1 = $01;  // Channel Band
+  CC_BAND2 = $02;  // Channel Band
+  CC_BAND3 = $03;  // Channel Band
+  // Transceiver Receiver Sensitivity Control Register
+  RX_PDT_LEVEL0 = $00;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL1 = $01;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL2 = $02;  // Reduce Receiver Sensitivity
+  RX_PDT_LEVEL3 = $03;  // Reduce Receiver Sensitivity
+  RX_OVERRIDE = $06;  
+  RX_PDT_DIS = $07;  
+  // Transceiver Reduced Power Consumption Control
+  XAH_RPC_EN = $00;  
+  IPAN_RPC_EN = $01;  
+  Res0 = $02;  
+  PLL_RPC_EN = $03;  
+  PDT_RPC_EN = $04;  
+  RX_RPC_EN = $05;  
+  RX_RPC_CTRL0 = $06;  // Smart Receiving Mode Timing
+  RX_RPC_CTRL1 = $07;  // Smart Receiving Mode Timing
+  // Transceiver Acknowledgment Frame Control Register 1
+  AACK_PROM_MODE = $01;  
+  AACK_ACK_TIME = $02;  
+  AACK_UPLD_RES_FT = $04;  
+  AACK_FLTR_RES_FT = $05;  
+  // Transceiver Filter Tuning Control Register
+  FTN_START = $07;  
+  // Transceiver Center Frequency Calibration Control Register
+  PLL_CF_START = $07;  
+  // Transceiver Delay Cell Calibration Control Register
+  PLL_DCU_START = $07;  
+  // Device Identification Register (Part Number)
+  PART_NUM0 = $00;  // Part Number
+  PART_NUM1 = $01;  // Part Number
+  PART_NUM2 = $02;  // Part Number
+  PART_NUM3 = $03;  // Part Number
+  PART_NUM4 = $04;  // Part Number
+  PART_NUM5 = $05;  // Part Number
+  PART_NUM6 = $06;  // Part Number
+  PART_NUM7 = $07;  // Part Number
+  // Device Identification Register (Version Number)
+  VERSION_NUM0 = $00;  // Version Number
+  VERSION_NUM1 = $01;  // Version Number
+  VERSION_NUM2 = $02;  // Version Number
+  VERSION_NUM3 = $03;  // Version Number
+  VERSION_NUM4 = $04;  // Version Number
+  VERSION_NUM5 = $05;  // Version Number
+  VERSION_NUM6 = $06;  // Version Number
+  VERSION_NUM7 = $07;  // Version Number
+  // Device Identification Register (Manufacture ID Low Byte)
+  MAN_ID_00 = $00;  
+  MAN_ID_01 = $01;  
+  MAN_ID_02 = $02;  
+  MAN_ID_03 = $03;  
+  MAN_ID_04 = $04;  
+  MAN_ID_05 = $05;  
+  MAN_ID_06 = $06;  
+  MAN_ID_07 = $07;  
+  // Device Identification Register (Manufacture ID High Byte)
+  MAN_ID_10 = $00;  // Manufacturer ID (High Byte)
+  MAN_ID_11 = $01;  // Manufacturer ID (High Byte)
+  MAN_ID_12 = $02;  // Manufacturer ID (High Byte)
+  MAN_ID_13 = $03;  // Manufacturer ID (High Byte)
+  MAN_ID_14 = $04;  // Manufacturer ID (High Byte)
+  MAN_ID_15 = $05;  // Manufacturer ID (High Byte)
+  MAN_ID_16 = $06;  // Manufacturer ID (High Byte)
+  MAN_ID_17 = $07;  // Manufacturer ID (High Byte)
+  // Transceiver MAC Short Address Register (Low Byte)
+  SHORT_ADDR_00 = $00;  
+  SHORT_ADDR_01 = $01;  
+  SHORT_ADDR_02 = $02;  
+  SHORT_ADDR_03 = $03;  
+  SHORT_ADDR_04 = $04;  
+  SHORT_ADDR_05 = $05;  
+  SHORT_ADDR_06 = $06;  
+  SHORT_ADDR_07 = $07;  
+  // Transceiver MAC Short Address Register (High Byte)
+  SHORT_ADDR_10 = $00;  // MAC Short Address
+  SHORT_ADDR_11 = $01;  // MAC Short Address
+  SHORT_ADDR_12 = $02;  // MAC Short Address
+  SHORT_ADDR_13 = $03;  // MAC Short Address
+  SHORT_ADDR_14 = $04;  // MAC Short Address
+  SHORT_ADDR_15 = $05;  // MAC Short Address
+  SHORT_ADDR_16 = $06;  // MAC Short Address
+  SHORT_ADDR_17 = $07;  // MAC Short Address
+  // Transceiver Personal Area Network ID Register (Low Byte)
+  PAN_ID_00 = $00;  
+  PAN_ID_01 = $01;  
+  PAN_ID_02 = $02;  
+  PAN_ID_03 = $03;  
+  PAN_ID_04 = $04;  
+  PAN_ID_05 = $05;  
+  PAN_ID_06 = $06;  
+  PAN_ID_07 = $07;  
+  // Transceiver Personal Area Network ID Register (High Byte)
+  PAN_ID_10 = $00;  // MAC Personal Area Network ID
+  PAN_ID_11 = $01;  // MAC Personal Area Network ID
+  PAN_ID_12 = $02;  // MAC Personal Area Network ID
+  PAN_ID_13 = $03;  // MAC Personal Area Network ID
+  PAN_ID_14 = $04;  // MAC Personal Area Network ID
+  PAN_ID_15 = $05;  // MAC Personal Area Network ID
+  PAN_ID_16 = $06;  // MAC Personal Area Network ID
+  PAN_ID_17 = $07;  // MAC Personal Area Network ID
+  // Transceiver MAC IEEE Address Register 0
+  IEEE_ADDR_00 = $00;  
+  IEEE_ADDR_01 = $01;  
+  IEEE_ADDR_02 = $02;  
+  IEEE_ADDR_03 = $03;  
+  IEEE_ADDR_04 = $04;  
+  IEEE_ADDR_05 = $05;  
+  IEEE_ADDR_06 = $06;  
+  IEEE_ADDR_07 = $07;  
+  // Transceiver MAC IEEE Address Register 1
+  IEEE_ADDR_10 = $00;  // MAC IEEE Address
+  IEEE_ADDR_11 = $01;  // MAC IEEE Address
+  IEEE_ADDR_12 = $02;  // MAC IEEE Address
+  IEEE_ADDR_13 = $03;  // MAC IEEE Address
+  IEEE_ADDR_14 = $04;  // MAC IEEE Address
+  IEEE_ADDR_15 = $05;  // MAC IEEE Address
+  IEEE_ADDR_16 = $06;  // MAC IEEE Address
+  IEEE_ADDR_17 = $07;  // MAC IEEE Address
+  // Transceiver Extended Operating Mode Control Register
+  SLOTTED_OPERATION = $00;  
+  MAX_CSMA_RETRIES0 = $01;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES1 = $02;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_CSMA_RETRIES2 = $03;  // Maximum Number of CSMA-CA Procedure Repetition Attempts
+  MAX_FRAME_RETRIES0 = $04;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES1 = $05;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES2 = $06;  // Maximum Number of Frame Re-transmission Attempts
+  MAX_FRAME_RETRIES3 = $07;  // Maximum Number of Frame Re-transmission Attempts
+  // Transceiver CSMA-CA Random Number Generator Seed Register
+  CSMA_SEED_00 = $00;  
+  CSMA_SEED_01 = $01;  
+  CSMA_SEED_02 = $02;  
+  CSMA_SEED_03 = $03;  
+  CSMA_SEED_04 = $04;  
+  CSMA_SEED_05 = $05;  
+  CSMA_SEED_06 = $06;  
+  CSMA_SEED_07 = $07;  
+  // Transceiver Acknowledgment Frame Control Register 2
+  CSMA_SEED_10 = $00;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_11 = $01;  // Seed Value for CSMA Random Number Generator
+  CSMA_SEED_12 = $02;  // Seed Value for CSMA Random Number Generator
+  AACK_I_AM_COORD = $03;  
+  AACK_DIS_ACK = $04;  
+  AACK_SET_PD = $05;  
+  AACK_FVN_MODE0 = $06;  // Acknowledgment Frame Filter Mode
+  AACK_FVN_MODE1 = $07;  // Acknowledgment Frame Filter Mode
+  // Transceiver CSMA-CA Back-off Exponent Control Register
+  MIN_BE0 = $00;  // Minimum Back-off Exponent
+  MIN_BE1 = $01;  // Minimum Back-off Exponent
+  MIN_BE2 = $02;  // Minimum Back-off Exponent
+  MIN_BE3 = $03;  // Minimum Back-off Exponent
+  MAX_BE0 = $04;  // Maximum Back-off Exponent
+  MAX_BE1 = $05;  // Maximum Back-off Exponent
+  MAX_BE2 = $06;  // Maximum Back-off Exponent
+  MAX_BE3 = $07;  // Maximum Back-off Exponent
+  // Transceiver Digital Test Control Register
+  TST_CTRL_DIG0 = $00;  // Digital Test Controller Register
+  TST_CTRL_DIG1 = $01;  // Digital Test Controller Register
+  TST_CTRL_DIG2 = $02;  // Digital Test Controller Register
+  TST_CTRL_DIG3 = $03;  // Digital Test Controller Register
+  // Transceiver Received Frame Length Register
+  RX_LENGTH0 = $00;  // Received Frame Length
+  RX_LENGTH1 = $01;  // Received Frame Length
+  RX_LENGTH2 = $02;  // Received Frame Length
+  RX_LENGTH3 = $03;  // Received Frame Length
+  RX_LENGTH4 = $04;  // Received Frame Length
+  RX_LENGTH5 = $05;  // Received Frame Length
+  RX_LENGTH6 = $06;  // Received Frame Length
+  RX_LENGTH7 = $07;  // Received Frame Length
+
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
+procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3
+procedure INT4_ISR; external name 'INT4_ISR'; // Interrupt 5 External Interrupt Request 4
+procedure INT5_ISR; external name 'INT5_ISR'; // Interrupt 6 External Interrupt Request 5
+procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6
+procedure INT7_ISR; external name 'INT7_ISR'; // Interrupt 8 External Interrupt Request 7
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 10 Pin Change Interrupt Request 1
+procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 11 Pin Change Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 13 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 14 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 15 Timer/Counter2 Overflow
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B
+procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 25 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 26 USART0 Data register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 27 USART0, Tx Complete
+procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready
+procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event
+procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A
+procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B
+procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C
+procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 36 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 37 USART1 Data register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 38 USART1, Tx Complete
+procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 39 2-wire Serial Interface
+procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 40 Store Program Memory Read
+procedure TIMER4_CAPT_ISR; external name 'TIMER4_CAPT_ISR'; // Interrupt 41 Timer/Counter4 Capture Event
+procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 42 Timer/Counter4 Compare Match A
+procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 43 Timer/Counter4 Compare Match B
+procedure TIMER4_COMPC_ISR; external name 'TIMER4_COMPC_ISR'; // Interrupt 44 Timer/Counter4 Compare Match C
+procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 45 Timer/Counter4 Overflow
+procedure TIMER5_CAPT_ISR; external name 'TIMER5_CAPT_ISR'; // Interrupt 46 Timer/Counter5 Capture Event
+procedure TIMER5_COMPA_ISR; external name 'TIMER5_COMPA_ISR'; // Interrupt 47 Timer/Counter5 Compare Match A
+procedure TIMER5_COMPB_ISR; external name 'TIMER5_COMPB_ISR'; // Interrupt 48 Timer/Counter5 Compare Match B
+procedure TIMER5_COMPC_ISR; external name 'TIMER5_COMPC_ISR'; // Interrupt 49 Timer/Counter5 Compare Match C
+procedure TIMER5_OVF_ISR; external name 'TIMER5_OVF_ISR'; // Interrupt 50 Timer/Counter5 Overflow
+procedure TRX24_PLL_LOCK_ISR; external name 'TRX24_PLL_LOCK_ISR'; // Interrupt 57 TRX24 - PLL lock interrupt
+procedure TRX24_PLL_UNLOCK_ISR; external name 'TRX24_PLL_UNLOCK_ISR'; // Interrupt 58 TRX24 - PLL unlock interrupt
+procedure TRX24_RX_START_ISR; external name 'TRX24_RX_START_ISR'; // Interrupt 59 TRX24 - Receive start interrupt
+procedure TRX24_RX_END_ISR; external name 'TRX24_RX_END_ISR'; // Interrupt 60 TRX24 - RX_END interrupt
+procedure TRX24_CCA_ED_DONE_ISR; external name 'TRX24_CCA_ED_DONE_ISR'; // Interrupt 61 TRX24 - CCA/ED done interrupt
+procedure TRX24_XAH_AMI_ISR; external name 'TRX24_XAH_AMI_ISR'; // Interrupt 62 TRX24 - XAH - AMI
+procedure TRX24_TX_END_ISR; external name 'TRX24_TX_END_ISR'; // Interrupt 63 TRX24 - TX_END interrupt
+procedure TRX24_AWAKE_ISR; external name 'TRX24_AWAKE_ISR'; // Interrupt 64 TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+procedure SCNT_CMP1_ISR; external name 'SCNT_CMP1_ISR'; // Interrupt 65 Symbol counter - compare match 1 interrupt
+procedure SCNT_CMP2_ISR; external name 'SCNT_CMP2_ISR'; // Interrupt 66 Symbol counter - compare match 2 interrupt
+procedure SCNT_CMP3_ISR; external name 'SCNT_CMP3_ISR'; // Interrupt 67 Symbol counter - compare match 3 interrupt
+procedure SCNT_OVFL_ISR; external name 'SCNT_OVFL_ISR'; // Interrupt 68 Symbol counter - overflow interrupt
+procedure SCNT_BACKOFF_ISR; external name 'SCNT_BACKOFF_ISR'; // Interrupt 69 Symbol counter - backoff interrupt
+procedure AES_READY_ISR; external name 'AES_READY_ISR'; // Interrupt 70 AES engine ready interrupt
+procedure BAT_LOW_ISR; external name 'BAT_LOW_ISR'; // Interrupt 71 Battery monitor indicates supply voltage below threshold
+procedure TRX24_TX_START_ISR; external name 'TRX24_TX_START_ISR'; // Interrupt 72 TRX24 TX start interrupt
+procedure TRX24_AMI0_ISR; external name 'TRX24_AMI0_ISR'; // Interrupt 73 Address match interrupt of address filter 0
+procedure TRX24_AMI1_ISR; external name 'TRX24_AMI1_ISR'; // Interrupt 74 Address match interrupt of address filter 1
+procedure TRX24_AMI2_ISR; external name 'TRX24_AMI2_ISR'; // Interrupt 75 Address match interrupt of address filter 2
+procedure TRX24_AMI3_ISR; external name 'TRX24_AMI3_ISR'; // Interrupt 76 Address match interrupt of address filter 3
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp INT0_ISR
+  jmp INT1_ISR
+  jmp INT2_ISR
+  jmp INT3_ISR
+  jmp INT4_ISR
+  jmp INT5_ISR
+  jmp INT6_ISR
+  jmp INT7_ISR
+  jmp PCINT0_ISR
+  jmp PCINT1_ISR
+  jmp PCINT2_ISR
+  jmp WDT_ISR
+  jmp TIMER2_COMPA_ISR
+  jmp TIMER2_COMPB_ISR
+  jmp TIMER2_OVF_ISR
+  jmp TIMER1_CAPT_ISR
+  jmp TIMER1_COMPA_ISR
+  jmp TIMER1_COMPB_ISR
+  jmp TIMER1_COMPC_ISR
+  jmp TIMER1_OVF_ISR
+  jmp TIMER0_COMPA_ISR
+  jmp TIMER0_COMPB_ISR
+  jmp TIMER0_OVF_ISR
+  jmp SPI_STC_ISR
+  jmp USART0_RX_ISR
+  jmp USART0_UDRE_ISR
+  jmp USART0_TX_ISR
+  jmp ANALOG_COMP_ISR
+  jmp ADC_ISR
+  jmp EE_READY_ISR
+  jmp TIMER3_CAPT_ISR
+  jmp TIMER3_COMPA_ISR
+  jmp TIMER3_COMPB_ISR
+  jmp TIMER3_COMPC_ISR
+  jmp TIMER3_OVF_ISR
+  jmp USART1_RX_ISR
+  jmp USART1_UDRE_ISR
+  jmp USART1_TX_ISR
+  jmp TWI_ISR
+  jmp SPM_READY_ISR
+  jmp TIMER4_CAPT_ISR
+  jmp TIMER4_COMPA_ISR
+  jmp TIMER4_COMPB_ISR
+  jmp TIMER4_COMPC_ISR
+  jmp TIMER4_OVF_ISR
+  jmp TIMER5_CAPT_ISR
+  jmp TIMER5_COMPA_ISR
+  jmp TIMER5_COMPB_ISR
+  jmp TIMER5_COMPC_ISR
+  jmp TIMER5_OVF_ISR
+  jmp TRX24_PLL_LOCK_ISR
+  jmp TRX24_PLL_UNLOCK_ISR
+  jmp TRX24_RX_START_ISR
+  jmp TRX24_RX_END_ISR
+  jmp TRX24_CCA_ED_DONE_ISR
+  jmp TRX24_XAH_AMI_ISR
+  jmp TRX24_TX_END_ISR
+  jmp TRX24_AWAKE_ISR
+  jmp SCNT_CMP1_ISR
+  jmp SCNT_CMP2_ISR
+  jmp SCNT_CMP3_ISR
+  jmp SCNT_OVFL_ISR
+  jmp SCNT_BACKOFF_ISR
+  jmp AES_READY_ISR
+  jmp BAT_LOW_ISR
+  jmp TRX24_TX_START_ISR
+  jmp TRX24_AMI0_ISR
+  jmp TRX24_AMI1_ISR
+  jmp TRX24_AMI2_ISR
+  jmp TRX24_AMI3_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak INT3_ISR
+  .weak INT4_ISR
+  .weak INT5_ISR
+  .weak INT6_ISR
+  .weak INT7_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak PCINT2_ISR
+  .weak WDT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_COMPC_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak ANALOG_COMP_ISR
+  .weak ADC_ISR
+  .weak EE_READY_ISR
+  .weak TIMER3_CAPT_ISR
+  .weak TIMER3_COMPA_ISR
+  .weak TIMER3_COMPB_ISR
+  .weak TIMER3_COMPC_ISR
+  .weak TIMER3_OVF_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_ISR
+  .weak SPM_READY_ISR
+  .weak TIMER4_CAPT_ISR
+  .weak TIMER4_COMPA_ISR
+  .weak TIMER4_COMPB_ISR
+  .weak TIMER4_COMPC_ISR
+  .weak TIMER4_OVF_ISR
+  .weak TIMER5_CAPT_ISR
+  .weak TIMER5_COMPA_ISR
+  .weak TIMER5_COMPB_ISR
+  .weak TIMER5_COMPC_ISR
+  .weak TIMER5_OVF_ISR
+  .weak TRX24_PLL_LOCK_ISR
+  .weak TRX24_PLL_UNLOCK_ISR
+  .weak TRX24_RX_START_ISR
+  .weak TRX24_RX_END_ISR
+  .weak TRX24_CCA_ED_DONE_ISR
+  .weak TRX24_XAH_AMI_ISR
+  .weak TRX24_TX_END_ISR
+  .weak TRX24_AWAKE_ISR
+  .weak SCNT_CMP1_ISR
+  .weak SCNT_CMP2_ISR
+  .weak SCNT_CMP3_ISR
+  .weak SCNT_OVFL_ISR
+  .weak SCNT_BACKOFF_ISR
+  .weak AES_READY_ISR
+  .weak BAT_LOW_ISR
+  .weak TRX24_TX_START_ISR
+  .weak TRX24_AMI0_ISR
+  .weak TRX24_AMI1_ISR
+  .weak TRX24_AMI2_ISR
+  .weak TRX24_AMI3_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set INT3_ISR, Default_IRQ_handler
+  .set INT4_ISR, Default_IRQ_handler
+  .set INT5_ISR, Default_IRQ_handler
+  .set INT6_ISR, Default_IRQ_handler
+  .set INT7_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set PCINT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_COMPC_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set ANALOG_COMP_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+  .set TIMER3_CAPT_ISR, Default_IRQ_handler
+  .set TIMER3_COMPA_ISR, Default_IRQ_handler
+  .set TIMER3_COMPB_ISR, Default_IRQ_handler
+  .set TIMER3_COMPC_ISR, Default_IRQ_handler
+  .set TIMER3_OVF_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_ISR, Default_IRQ_handler
+  .set SPM_READY_ISR, Default_IRQ_handler
+  .set TIMER4_CAPT_ISR, Default_IRQ_handler
+  .set TIMER4_COMPA_ISR, Default_IRQ_handler
+  .set TIMER4_COMPB_ISR, Default_IRQ_handler
+  .set TIMER4_COMPC_ISR, Default_IRQ_handler
+  .set TIMER4_OVF_ISR, Default_IRQ_handler
+  .set TIMER5_CAPT_ISR, Default_IRQ_handler
+  .set TIMER5_COMPA_ISR, Default_IRQ_handler
+  .set TIMER5_COMPB_ISR, Default_IRQ_handler
+  .set TIMER5_COMPC_ISR, Default_IRQ_handler
+  .set TIMER5_OVF_ISR, Default_IRQ_handler
+  .set TRX24_PLL_LOCK_ISR, Default_IRQ_handler
+  .set TRX24_PLL_UNLOCK_ISR, Default_IRQ_handler
+  .set TRX24_RX_START_ISR, Default_IRQ_handler
+  .set TRX24_RX_END_ISR, Default_IRQ_handler
+  .set TRX24_CCA_ED_DONE_ISR, Default_IRQ_handler
+  .set TRX24_XAH_AMI_ISR, Default_IRQ_handler
+  .set TRX24_TX_END_ISR, Default_IRQ_handler
+  .set TRX24_AWAKE_ISR, Default_IRQ_handler
+  .set SCNT_CMP1_ISR, Default_IRQ_handler
+  .set SCNT_CMP2_ISR, Default_IRQ_handler
+  .set SCNT_CMP3_ISR, Default_IRQ_handler
+  .set SCNT_OVFL_ISR, Default_IRQ_handler
+  .set SCNT_BACKOFF_ISR, Default_IRQ_handler
+  .set AES_READY_ISR, Default_IRQ_handler
+  .set BAT_LOW_ISR, Default_IRQ_handler
+  .set TRX24_TX_START_ISR, Default_IRQ_handler
+  .set TRX24_AMI0_ISR, Default_IRQ_handler
+  .set TRX24_AMI1_ISR, Default_IRQ_handler
+  .set TRX24_AMI2_ISR, Default_IRQ_handler
+  .set TRX24_AMI3_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/atmega8hva.pp

@@ -0,0 +1,413 @@
+unit ATmega8HVA;
+
+{$goto on}
+interface
+
+var
+  PINA: byte absolute $20;  // Port A Input Pins
+  DDRA: byte absolute $21;  // Port A Data Direction Register
+  PORTA: byte absolute $22;  // Port A Data Register
+  PINB: byte absolute $23;  // Input Pins, Port B
+  DDRB: byte absolute $24;  // Data Direction Register, Port B
+  PORTB: byte absolute $25;  // Data Register, Port B
+  PINC: byte absolute $26;  // Port C Input Pins
+  PORTC: byte absolute $28;  // Port C Data Register
+  TIFR0: byte absolute $35;  // Timer/Counter Interrupt Flag register
+  TIFR1: byte absolute $36;  // Timer/Counter Interrupt Flag register
+  OSICSR: byte absolute $37;  // Oscillator Sampling Interface Control and Status Register
+  EIFR: byte absolute $3C;  // External Interrupt Flag Register
+  EIMSK: byte absolute $3D;  // External Interrupt Mask Register
+  GPIOR0: byte absolute $3E;  // General Purpose IO Register 0
+  EECR: byte absolute $3F;  // EEPROM Control Register
+  EEDR: byte absolute $40;  // EEPROM Data Register
+  EEAR: byte absolute $41;  // EEPROM Read/Write Access
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  TCCR0A: byte absolute $44;  // Timer/Counter0 Control Register
+  TCCR0B: byte absolute $45;  // Timer/Counter0 Control Register
+  TCNT0: word absolute $46;  // Timer Counter 0  Bytes
+  TCNT0L: byte absolute $46;  // Timer Counter 0  Bytes
+  TCNT0H: byte absolute $47;  // Timer Counter 0  Bytes;
+  OCR0A: byte absolute $48;  // Output compare Register A
+  OCR0B: byte absolute $49;  // Output compare Register B
+  GPIOR1: byte absolute $4A;  // General Purpose IO Register 1
+  GPIOR2: byte absolute $4B;  // General Purpose IO Register 2
+  SPCR: byte absolute $4C;  // SPI Control Register
+  SPSR: byte absolute $4D;  // SPI Status Register
+  SPDR: byte absolute $4E;  // SPI Data Register
+  SMCR: byte absolute $53;  // Sleep Mode Control Register
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  WDTCSR: byte absolute $60;  // Watchdog Timer Control Register
+  CLKPR: byte absolute $61;  // Clock Prescale Register
+  PRR0: byte absolute $64;  // Power Reduction Register 0
+  FOSCCAL: byte absolute $66;  // Fast Oscillator Calibration Value
+  EICRA: byte absolute $69;  // External Interrupt Control Register
+  TIMSK0: byte absolute $6E;  // Timer/Counter Interrupt Mask Register
+  TIMSK1: byte absolute $6F;  // Timer/Counter Interrupt Mask Register
+  VADC: word absolute $78;  // VADC Data Register  Bytes
+  VADCL: byte absolute $78;  // VADC Data Register  Bytes
+  VADCH: byte absolute $79;  // VADC Data Register  Bytes;
+  VADCSR: byte absolute $7A;  // The VADC Control and Status register
+  VADMUX: byte absolute $7C;  // The VADC multiplexer Selection Register
+  DIDR0: byte absolute $7E;  // Digital Input Disable Register
+  TCCR1A: byte absolute $80;  // Timer/Counter 1 Control Register A
+  TCCR1B: byte absolute $81;  // Timer/Counter1 Control Register B
+  TCNT1: word absolute $84;  // Timer Counter 1  Bytes
+  TCNT1L: byte absolute $84;  // Timer Counter 1  Bytes
+  TCNT1H: byte absolute $85;  // Timer Counter 1  Bytes;
+  OCR1A: byte absolute $88;  // Output Compare Register 1A
+  OCR1B: byte absolute $89;  // Output Compare Register B
+  ROCR: byte absolute $C8;  // Regulator Operating Condition Register
+  BGCCR: byte absolute $D0;  // Bandgap Calibration Register
+  BGCRR: byte absolute $D1;  // Bandgap Calibration of Resistor Ladder
+  CADAC0: byte absolute $E0;  // ADC Accumulate Current
+  CADAC1: byte absolute $E1;  // ADC Accumulate Current
+  CADAC2: byte absolute $E2;  // ADC Accumulate Current
+  CADAC3: byte absolute $E3;  // ADC Accumulate Current
+  CADCSRA: byte absolute $E4;  // CC-ADC Control and Status Register A
+  CADCSRB: byte absolute $E5;  // CC-ADC Control and Status Register B
+  CADRC: byte absolute $E6;  // CC-ADC Regular Current
+  CADIC: word absolute $E8;  // CC-ADC Instantaneous Current
+  CADICL: byte absolute $E8;  // CC-ADC Instantaneous Current
+  CADICH: byte absolute $E9;  // CC-ADC Instantaneous Current;
+  FCSR: byte absolute $F0;  // FET Control and Status Register
+  BPIMSK: byte absolute $F2;  // Battery Protection Interrupt Mask Register
+  BPIFR: byte absolute $F3;  // Battery Protection Interrupt Flag Register
+  BPSCD: byte absolute $F5;  // Battery Protection Short-Circuit Detection Level Register
+  BPDOCD: byte absolute $F6;  // Battery Protection Discharge-Over-current Detection Level Register
+  BPCOCD: byte absolute $F7;  // Battery Protection Charge-Over-current Detection Level Register
+  BPDHCD: byte absolute $F8;  // Battery Protection Discharge-High-current Detection Level Register
+  BPCHCD: byte absolute $F9;  // Battery Protection Charge-High-current Detection Level Register
+  BPSCTR: byte absolute $FA;  // Battery Protection Short-current Timing Register
+  BPOCTR: byte absolute $FB;  // Battery Protection Over-current Timing Register
+  BPHCTR: byte absolute $FC;  // Battery Protection Short-current Timing Register
+  BPCR: byte absolute $FD;  // Battery Protection Control Register
+  BPPLR: byte absolute $FE;  // Battery Protection Parameter Lock Register
+
+const
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  // Data Register, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  // Port C Data Register
+  PC0 = $00;  
+  // Timer/Counter Interrupt Flag register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  ICF0 = $03;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $03;  
+  // Oscillator Sampling Interface Control and Status Register
+  OSIEN = $00;  
+  OSIST = $01;  
+  OSISEL0 = $04;  
+  // External Interrupt Flag Register
+  INTF0 = $00;  // External Interrupt Flags
+  INTF1 = $01;  // External Interrupt Flags
+  INTF2 = $02;  // External Interrupt Flags
+  // External Interrupt Mask Register
+  INT0 = $00;  // External Interrupt Request 2 Enable
+  INT1 = $01;  // External Interrupt Request 2 Enable
+  INT2 = $02;  // External Interrupt Request 2 Enable
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;
+  EEPM1 = $05;
+  // General Timer/Counter Control Register
+  PSRSYNC = $00;  
+  TSM = $07;  
+  // Timer/Counter0 Control Register
+  WGM00 = $00;  
+  ICS0 = $03;  
+  ICES0 = $04;  
+  ICNC0 = $05;  
+  ICEN0 = $06;  
+  TCW0 = $07;  
+  // Timer/Counter0 Control Register
+  CS00 = $00;  
+  CS01 = $01;  
+  CS02 = $02;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // Sleep Mode Control Register
+  SE = $00;  
+  SM0 = $01;  // Sleep Mode Select bits
+  SM1 = $02;  // Sleep Mode Select bits
+  SM2 = $03;  // Sleep Mode Select bits
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BODRF = $02;  
+  WDRF = $03;  
+  OCDRF = $04;  
+  // MCU Control Register
+  PUD = $04;  
+  CKOE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  RFLB = $03;  
+  CTPB = $04;  
+  SIGRD = $05;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Watchdog Timer Control Register
+  WDE = $03;  
+  WDCE = $04;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPCE = $07;  
+  // Power Reduction Register 0
+  PRVADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRSPI = $03;  
+  PRVRM = $05;  
+  // External Interrupt Control Register
+  ISC00 = $00;  // External Interrupt Sense Control 0 Bits
+  ISC01 = $01;  // External Interrupt Sense Control 0 Bits
+  ISC10 = $02;  // External Interrupt Sense Control 1 Bits
+  ISC11 = $03;  // External Interrupt Sense Control 1 Bits
+  ISC20 = $04;  // External Interrupt Sense Control 2 Bits
+  ISC21 = $05;  // External Interrupt Sense Control 2 Bits
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  ICIE0 = $03;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $03;  
+  // The VADC Control and Status register
+  VADCCIE = $00;  
+  VADCCIF = $01;  
+  VADSC = $02;  
+  VADEN = $03;  
+  // The VADC multiplexer Selection Register
+  VADMUX0 = $00;  // Analog Channel and Gain Selection Bits
+  VADMUX1 = $01;  // Analog Channel and Gain Selection Bits
+  VADMUX2 = $02;  // Analog Channel and Gain Selection Bits
+  VADMUX3 = $03;  // Analog Channel and Gain Selection Bits
+  // Digital Input Disable Register
+  PA0DID = $00;  
+  PA1DID = $01;  
+  // Timer/Counter 1 Control Register A
+  WGM10 = $00;  
+  ICS1 = $03;  
+  ICES1 = $04;  
+  ICNC1 = $05;  
+  ICEN1 = $06;  
+  TCW1 = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select1 bis
+  CS11 = $01;  // Clock Select1 bis
+  CS12 = $02;  // Clock Select1 bis
+  // Regulator Operating Condition Register
+  ROCWIE = $00;  
+  ROCWIF = $01;  
+  ROCS = $07;  
+  // Bandgap Calibration Register
+  BGCC0 = $00;  // BG Calibration of PTAT Current Bits
+  BGCC1 = $01;  // BG Calibration of PTAT Current Bits
+  BGCC2 = $02;  // BG Calibration of PTAT Current Bits
+  BGCC3 = $03;  // BG Calibration of PTAT Current Bits
+  BGCC4 = $04;  // BG Calibration of PTAT Current Bits
+  BGCC5 = $05;  // BG Calibration of PTAT Current Bits
+  BGD = $07;  
+  // Bandgap Calibration of Resistor Ladder
+  BGCR0 = $00;  // Bandgap calibration bits
+  BGCR1 = $01;  // Bandgap calibration bits
+  BGCR2 = $02;  // Bandgap calibration bits
+  BGCR3 = $03;  // Bandgap calibration bits
+  BGCR4 = $04;  // Bandgap calibration bits
+  BGCR5 = $05;  // Bandgap calibration bits
+  BGCR6 = $06;  // Bandgap calibration bits
+  BGCR7 = $07;  // Bandgap calibration bits
+  // CC-ADC Control and Status Register A
+  CADSE = $00;  
+  CADSI0 = $01;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADSI1 = $02;  // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+  CADAS0 = $03;  // CC_ADC Accumulate Current Select Bits
+  CADAS1 = $04;  // CC_ADC Accumulate Current Select Bits
+  CADUB = $05;  
+  CADPOL = $06;  
+  CADEN = $07;  
+  // CC-ADC Control and Status Register B
+  CADICIF = $00;  
+  CADRCIF = $01;  
+  CADACIF = $02;  
+  CADICIE = $04;  
+  CADRCIE = $05;  
+  CADACIE = $06;  
+  // FET Control and Status Register
+  CFE = $00;  
+  DFE = $01;  
+  CPS = $02;  
+  DUVRD = $03;  
+  // Battery Protection Interrupt Mask Register
+  CHCIE = $00;  
+  DHCIE = $01;  
+  COCIE = $02;  
+  DOCIE = $03;  
+  SCIE = $04;  
+  // Battery Protection Interrupt Flag Register
+  CHCIF = $00;  
+  DHCIF = $01;  
+  COCIF = $02;  
+  DOCIF = $03;  
+  SCIF = $04;  
+  // Battery Protection Control Register
+  CHCD = $00;  
+  DHCD = $01;  
+  COCD = $02;  
+  DOCD = $03;  
+  SCD = $04;  
+  // Battery Protection Parameter Lock Register
+  BPPL = $00;  
+  BPPLE = $01;  
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
+procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
+procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
+procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 6 Watchdog Timeout Interrupt
+procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 7 Timer 1 Input capture
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 8 Timer 1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 9 Timer 1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 10 Timer 1 overflow
+procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 11 Timer 0 Input Capture
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 12 Timer 0 Comapre Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 13 Timer 0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 14 Timer 0 Overflow
+procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 15 SPI Serial transfer complete
+procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 16 Voltage ADC Conversion Complete
+procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 17 Coulomb Counter ADC Conversion Complete
+procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 18 Coloumb Counter ADC Regular Current
+procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 19 Coloumb Counter ADC Accumulator
+procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 20 EEPROM Ready
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp BPINT_ISR
+  rjmp VREGMON_ISR
+  rjmp INT0_ISR
+  rjmp INT1_ISR
+  rjmp INT2_ISR
+  rjmp WDT_ISR
+  rjmp TIMER1_IC_ISR
+  rjmp TIMER1_COMPA_ISR
+  rjmp TIMER1_COMPB_ISR
+  rjmp TIMER1_OVF_ISR
+  rjmp TIMER0_IC_ISR
+  rjmp TIMER0_COMPA_ISR
+  rjmp TIMER0_COMPB_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp SPI_STC_ISR
+  rjmp VADC_ISR
+  rjmp CCADC_CONV_ISR
+  rjmp CCADC_REG_CUR_ISR
+  rjmp CCADC_ACC_ISR
+  rjmp EE_READY_ISR
+
+  {$i start.inc}
+
+  .weak BPINT_ISR
+  .weak VREGMON_ISR
+  .weak INT0_ISR
+  .weak INT1_ISR
+  .weak INT2_ISR
+  .weak WDT_ISR
+  .weak TIMER1_IC_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_IC_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak SPI_STC_ISR
+  .weak VADC_ISR
+  .weak CCADC_CONV_ISR
+  .weak CCADC_REG_CUR_ISR
+  .weak CCADC_ACC_ISR
+  .weak EE_READY_ISR
+
+  .set BPINT_ISR, Default_IRQ_handler
+  .set VREGMON_ISR, Default_IRQ_handler
+  .set INT0_ISR, Default_IRQ_handler
+  .set INT1_ISR, Default_IRQ_handler
+  .set INT2_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER1_IC_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_IC_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set SPI_STC_ISR, Default_IRQ_handler
+  .set VADC_ISR, Default_IRQ_handler
+  .set CCADC_CONV_ISR, Default_IRQ_handler
+  .set CCADC_REG_CUR_ISR, Default_IRQ_handler
+  .set CCADC_ACC_ISR, Default_IRQ_handler
+  .set EE_READY_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/attiny1624.pp

@@ -0,0 +1,2522 @@
+unit ATtiny1624;
+
+{$goto on}
+interface
+
+type
+  TAC = object //Analog Comparator
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    MUXCTRLA: byte;  //Mux Control A
+    Reserved3: byte;
+    DACREF: byte;  //Referance scale control
+    Reserved5: byte;
+    INTCTRL: byte;  //Interrupt Control
+    STATUS: byte;  //Status
+  const
+    // Enable
+    ENABLEbm = $01;
+    // AC_HYSMODE
+    HYSMODEmask = $06;
+    HYSMODE_OFF = $00;
+    HYSMODE_10mV = $02;
+    HYSMODE_25mV = $04;
+    HYSMODE_50mV = $06;
+    // AC_INTMODE
+    INTMODEmask = $30;
+    INTMODE_BOTHEDGE = $00;
+    INTMODE_NEGEDGE = $20;
+    INTMODE_POSEDGE = $30;
+    // AC_LPMODE
+    LPMODEmask = $08;
+    LPMODE_DIS = $00;
+    LPMODE_EN = $08;
+    // Output Buffer Enable
+    OUTENbm = $40;
+    // Run in Standby Mode
+    RUNSTDBYbm = $80;
+    // DAC voltage reference
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Analog Comparator 0 Interrupt Enable
+    CMPbm = $01;
+    // Invert AC Output
+    INVERTbm = $80;
+    // AC_MUXNEG
+    MUXNEGmask = $03;
+    MUXNEG_PIN0 = $00;
+    MUXNEG_PIN1 = $01;
+    MUXNEG_PIN2 = $02;
+    MUXNEG_DACREF = $03;
+    // AC_MUXPOS
+    MUXPOSmask = $18;
+    MUXPOS_PIN0 = $00;
+    MUXPOS_PIN1 = $08;
+    MUXPOS_PIN2 = $10;
+    MUXPOS_PIN3 = $18;
+    // Analog Comparator State
+    STATEbm = $10;
+  end;
+
+  TADC = object //Analog to Digital Converter
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status register
+    DBGCTRL: byte;  //Debug Control
+    CTRLE: byte;  //Control E
+    CTRLF: byte;  //Control F
+    COMMAND: byte;  //Command register
+    PGACTRL: byte;  //PGA Control
+    MUXPOS: byte;  //Positive mux input
+    MUXNEG: byte;  //Negative mux input
+    Reserved14: byte;
+    Reserved15: byte;
+    RESULT: dword;  //Result
+    SAMPLE: word;  //Sample
+    Reserved22: byte;
+    Reserved23: byte;
+    TEMP0: byte;  //Temporary Data 0
+    TEMP1: byte;  //Temporary Data 1
+    TEMP2: byte;  //Temporary Data 2
+    Reserved27: byte;
+    WINLT: word;  //Window Low Threshold
+    WINHT: word;  //Window High Threshold
+  const
+    // Differential mode
+    DIFFbm = $80;
+    // ADC_MODE
+    MODEmask = $70;
+    MODE_SINGLE_8BIT = $00;
+    MODE_SINGLE_12BIT = $10;
+    MODE_SERIES = $20;
+    MODE_SERIES_TRUNCATION = $30;
+    MODE_BURST = $40;
+    MODE_BURST_TRUNCATION = $50;
+    // ADC_START
+    STARTmask = $07;
+    START_STOP = $00;
+    START_IMMEDIATE = $01;
+    START_MUXPOS_WRITE = $02;
+    START_MUXNEG_WRITE = $03;
+    START_EVENT_TRIGGER = $04;
+    // ADC Enable
+    ENABLEbm = $01;
+    // ADC Low latency mode
+    LOWLATbm = $20;
+    // Run standby mode
+    RUNSTDBYbm = $80;
+    // ADC_PRESC
+    PRESCmask = $0F;
+    PRESC_DIV2 = $00;
+    PRESC_DIV4 = $01;
+    PRESC_DIV6 = $02;
+    PRESC_DIV8 = $03;
+    PRESC_DIV10 = $04;
+    PRESC_DIV12 = $05;
+    PRESC_DIV14 = $06;
+    PRESC_DIV16 = $07;
+    PRESC_DIV20 = $08;
+    PRESC_DIV24 = $09;
+    PRESC_DIV28 = $0A;
+    PRESC_DIV32 = $0B;
+    PRESC_DIV40 = $0C;
+    PRESC_DIV48 = $0D;
+    PRESC_DIV56 = $0E;
+    PRESC_DIV64 = $0F;
+    // ADC_REFSEL
+    REFSELmask = $07;
+    REFSEL_VDD = $00;
+    REFSEL_VREFA = $02;
+    REFSEL_1024MV = $04;
+    REFSEL_2048MV = $05;
+    REFSEL_2500MV = $06;
+    REFSEL_4096MV = $07;
+    // Reference Selection
+    TIMEBASE0bm = $08;
+    TIMEBASE1bm = $10;
+    TIMEBASE2bm = $20;
+    TIMEBASE3bm = $40;
+    TIMEBASE4bm = $80;
+    // ADC_WINCM
+    WINCMmask = $07;
+    WINCM_NONE = $00;
+    WINCM_BELOW = $01;
+    WINCM_ABOVE = $02;
+    WINCM_INSIDE = $03;
+    WINCM_OUTSIDE = $04;
+    // ADC_WINSRC
+    WINSRCmask = $08;
+    WINSRC_RESULT = $00;
+    WINSRC_SAMPLE = $08;
+    // Sampling time
+    SAMPDUR0bm = $01;
+    SAMPDUR1bm = $02;
+    SAMPDUR2bm = $04;
+    SAMPDUR3bm = $08;
+    SAMPDUR4bm = $10;
+    SAMPDUR5bm = $20;
+    SAMPDUR6bm = $40;
+    SAMPDUR7bm = $80;
+    // Free running mode
+    FREERUNbm = $20;
+    // Left adjust
+    LEFTADJbm = $10;
+    // ADC_SAMPNUM
+    SAMPNUMmask = $0F;
+    SAMPNUM_NONE = $00;
+    SAMPNUM_ACC2 = $01;
+    SAMPNUM_ACC4 = $02;
+    SAMPNUM_ACC8 = $03;
+    SAMPNUM_ACC16 = $04;
+    SAMPNUM_ACC32 = $05;
+    SAMPNUM_ACC64 = $06;
+    SAMPNUM_ACC128 = $07;
+    SAMPNUM_ACC256 = $08;
+    SAMPNUM_ACC512 = $09;
+    SAMPNUM_ACC1024 = $0A;
+    // Debug run
+    DBGRUNbm = $01;
+    // Result Overwritten Interrupt Enable
+    RESOVRbm = $08;
+    // Result Ready Interrupt Enable
+    RESRDYbm = $01;
+    // Sample Overwritten Interrupt Enable
+    SAMPOVRbm = $10;
+    // Sample Ready Interrupt Enable
+    SAMPRDYbm = $02;
+    // Trigger Overrun Interrupt Enable
+    TRIGOVRbm = $20;
+    // Window Comparator Interrupt Enable
+    WCMPbm = $04;
+    // ADC_MUXNEG
+    MUXNEGmask = $3F;
+    MUXNEG_AIN1 = $01;
+    MUXNEG_AIN2 = $02;
+    MUXNEG_AIN3 = $03;
+    MUXNEG_AIN4 = $04;
+    MUXNEG_AIN5 = $05;
+    MUXNEG_AIN6 = $06;
+    MUXNEG_AIN7 = $07;
+    MUXNEG_GND = $30;
+    MUXNEG_VDDDIV10 = $31;
+    MUXNEG_DAC = $33;
+    // ADC_VIA
+    VIAmask = $C0;
+    VIA_ADC = $00;
+    VIA_PGA = $40;
+    // ADC_MUXPOS
+    MUXPOSmask = $3F;
+    MUXPOS_AIN1 = $01;
+    MUXPOS_AIN2 = $02;
+    MUXPOS_AIN3 = $03;
+    MUXPOS_AIN4 = $04;
+    MUXPOS_AIN5 = $05;
+    MUXPOS_AIN6 = $06;
+    MUXPOS_AIN7 = $07;
+    MUXPOS_AIN8 = $08;
+    MUXPOS_AIN9 = $09;
+    MUXPOS_AIN10 = $0A;
+    MUXPOS_AIN11 = $0B;
+    MUXPOS_AIN12 = $0C;
+    MUXPOS_AIN13 = $0D;
+    MUXPOS_AIN14 = $0E;
+    MUXPOS_AIN15 = $0F;
+    MUXPOS_GND = $30;
+    MUXPOS_VDDDIV10 = $31;
+    MUXPOS_TEMPSENSE = $32;
+    MUXPOS_DAC = $33;
+    // ADC_ADCPGASAMPDUR
+    ADCPGASAMPDURmask = $06;
+    ADCPGASAMPDUR_6CLK = $00;
+    ADCPGASAMPDUR_15CLK = $02;
+    ADCPGASAMPDUR_20CLK = $04;
+    ADCPGASAMPDUR_32CLK = $06;
+    // ADC_GAIN
+    GAINmask = $E0;
+    GAIN_1X = $00;
+    GAIN_2X = $20;
+    GAIN_4X = $40;
+    GAIN_8X = $60;
+    GAIN_16X = $80;
+    // ADC_PGABIASSEL
+    PGABIASSELmask = $18;
+    PGABIASSEL_1X = $00;
+    PGABIASSEL_3_4X = $08;
+    PGABIASSEL_1_2X = $10;
+    PGABIASSEL_1_4X = $18;
+    // PGA Enable
+    PGAENbm = $01;
+    // ADC Busy
+    ADCBUSYbm = $01;
+    // Temporary
+    TEMP0bm = $01;
+    TEMP1bm = $02;
+    TEMP2bm = $04;
+    TEMP3bm = $08;
+    TEMP4bm = $10;
+    TEMP5bm = $20;
+    TEMP6bm = $40;
+    TEMP7bm = $80;
+  end;
+
+  TBOD = object //Bod interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    VLMCTRLA: byte;  //Voltage level monitor Control
+    INTCTRL: byte;  //Voltage level monitor interrupt Control
+    INTFLAGS: byte;  //Voltage level monitor interrupt Flags
+    STATUS: byte;  //Voltage level monitor status
+  const
+    // BOD_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // BOD_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // BOD_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // BOD_LVL
+    LVLmask = $07;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $02;
+    LVL_BODLEVEL7 = $07;
+    // BOD_VLMCFG
+    VLMCFGmask = $06;
+    VLMCFG_BELOW = $00;
+    VLMCFG_ABOVE = $02;
+    VLMCFG_CROSS = $04;
+    // voltage level monitor interrrupt enable
+    VLMIEbm = $01;
+    // Voltage level monitor interrupt flag
+    VLMIFbm = $01;
+    // Voltage level monitor status
+    VLMSbm = $01;
+    // BOD_VLMLVL
+    VLMLVLmask = $03;
+    VLMLVL_5ABOVE = $00;
+    VLMLVL_15ABOVE = $01;
+    VLMLVL_25ABOVE = $02;
+  end;
+
+  TCCL = object //Configurable Custom Logic
+    CTRLA: byte;  //Control Register A
+    SEQCTRL0: byte;  //Sequential Control 0
+    SEQCTRL1: byte;  //Sequential Control 1
+    Reserved3: byte;
+    Reserved4: byte;
+    INTCTRL0: byte;  //Interrupt Control 0
+    Reserved6: byte;
+    INTFLAGS: byte;  //Interrupt Flags
+    LUT0CTRLA: byte;  //LUT Control 0 A
+    LUT0CTRLB: byte;  //LUT Control 0 B
+    LUT0CTRLC: byte;  //LUT Control 0 C
+    TRUTH0: byte;  //Truth 0
+    LUT1CTRLA: byte;  //LUT Control 1 A
+    LUT1CTRLB: byte;  //LUT Control 1 B
+    LUT1CTRLC: byte;  //LUT Control 1 C
+    TRUTH1: byte;  //Truth 1
+    LUT2CTRLA: byte;  //LUT Control 2 A
+    LUT2CTRLB: byte;  //LUT Control 2 B
+    LUT2CTRLC: byte;  //LUT Control 2 C
+    TRUTH2: byte;  //Truth 2
+    LUT3CTRLA: byte;  //LUT Control 3 A
+    LUT3CTRLB: byte;  //LUT Control 3 B
+    LUT3CTRLC: byte;  //LUT Control 3 C
+    TRUTH3: byte;  //Truth 3
+  const
+    // Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $40;
+    // CCL_INTMODE0
+    INTMODE0mask = $03;
+    INTMODE0_INTDISABLE = $00;
+    INTMODE0_RISING = $01;
+    INTMODE0_FALLING = $02;
+    INTMODE0_BOTH = $03;
+    // CCL_INTMODE1
+    INTMODE1mask = $0C;
+    INTMODE1_INTDISABLE = $00;
+    INTMODE1_RISING = $04;
+    INTMODE1_FALLING = $08;
+    INTMODE1_BOTH = $0C;
+    // CCL_INTMODE2
+    INTMODE2mask = $30;
+    INTMODE2_INTDISABLE = $00;
+    INTMODE2_RISING = $10;
+    INTMODE2_FALLING = $20;
+    INTMODE2_BOTH = $30;
+    // CCL_INTMODE3
+    INTMODE3mask = $C0;
+    INTMODE3_INTDISABLE = $00;
+    INTMODE3_RISING = $40;
+    INTMODE3_FALLING = $80;
+    INTMODE3_BOTH = $C0;
+    // Interrupt Flags
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    // CCL_CLKSRC
+    CLKSRCmask = $0E;
+    CLKSRC_CLKPER = $00;
+    CLKSRC_IN2 = $02;
+    CLKSRC_OSC20M = $08;
+    CLKSRC_OSCULP32K = $0A;
+    CLKSRC_OSCULP1K = $0C;
+    // CCL_EDGEDET
+    EDGEDETmask = $80;
+    EDGEDET_DIS = $00;
+    EDGEDET_EN = $80;
+    // CCL_FILTSEL
+    FILTSELmask = $30;
+    FILTSEL_DISABLE = $00;
+    FILTSEL_SYNCH = $10;
+    FILTSEL_FILTER = $20;
+    // Output Enable
+    OUTENbm = $40;
+    // CCL_INSEL0
+    INSEL0mask = $0F;
+    INSEL0_MASK = $00;
+    INSEL0_FEEDBACK = $01;
+    INSEL0_LINK = $02;
+    INSEL0_EVENTA = $03;
+    INSEL0_EVENTB = $04;
+    INSEL0_IO = $05;
+    INSEL0_AC0 = $06;
+    INSEL0_USART0 = $08;
+    INSEL0_SPI0 = $09;
+    INSEL0_TCA0 = $0A;
+    INSEL0_TCB0 = $0C;
+    // CCL_INSEL1
+    INSEL1mask = $F0;
+    INSEL1_MASK = $00;
+    INSEL1_FEEDBACK = $10;
+    INSEL1_LINK = $20;
+    INSEL1_EVENTA = $30;
+    INSEL1_EVENTB = $40;
+    INSEL1_IO = $50;
+    INSEL1_AC0 = $60;
+    INSEL1_USART1 = $80;
+    INSEL1_SPI0 = $90;
+    INSEL1_TCA0 = $A0;
+    INSEL1_TCB1 = $C0;
+    // CCL_INSEL2
+    INSEL2mask = $0F;
+    INSEL2_MASK = $00;
+    INSEL2_FEEDBACK = $01;
+    INSEL2_LINK = $02;
+    INSEL2_EVENTA = $03;
+    INSEL2_EVENTB = $04;
+    INSEL2_IO = $05;
+    INSEL2_AC0 = $06;
+    INSEL2_SPI0 = $09;
+    INSEL2_TCA0 = $0A;
+    // CCL_SEQSEL0
+    SEQSEL0mask = $07;
+    SEQSEL0_DISABLE = $00;
+    SEQSEL0_DFF = $01;
+    SEQSEL0_JK = $02;
+    SEQSEL0_LATCH = $03;
+    SEQSEL0_RS = $04;
+    // CCL_SEQSEL1
+    SEQSEL1mask = $07;
+    SEQSEL1_DISABLE = $00;
+    SEQSEL1_DFF = $01;
+    SEQSEL1_JK = $02;
+    SEQSEL1_LATCH = $03;
+    SEQSEL1_RS = $04;
+  end;
+
+  TCLKCTRL = object //Clock controller
+    MCLKCTRLA: byte;  //MCLK Control A
+    MCLKCTRLB: byte;  //MCLK Control B
+    MCLKLOCK: byte;  //MCLK Lock
+    MCLKSTATUS: byte;  //MCLK Status
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    OSC20MCTRLA: byte;  //OSC20M Control A
+    OSC20MCALIBA: byte;  //OSC20M Calibration A
+    OSC20MCALIBB: byte;  //OSC20M Calibration B
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSC32KCTRLA: byte;  //OSC32K Control A
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    XOSC32KCTRLA: byte;  //XOSC32K Control A
+  const
+    // System clock out
+    CLKOUTbm = $80;
+    // CLKCTRL_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_OSC20M = $00;
+    CLKSEL_OSCULP32K = $01;
+    CLKSEL_XOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // CLKCTRL_PDIV
+    PDIVmask = $1E;
+    PDIV_2X = $00;
+    PDIV_4X = $02;
+    PDIV_8X = $04;
+    PDIV_16X = $06;
+    PDIV_32X = $08;
+    PDIV_64X = $0A;
+    PDIV_6X = $10;
+    PDIV_10X = $12;
+    PDIV_12X = $14;
+    PDIV_24X = $16;
+    PDIV_48X = $18;
+    // Prescaler enable
+    PENbm = $01;
+    // lock ebable
+    LOCKENbm = $01;
+    // External Clock status
+    EXTSbm = $80;
+    // 20MHz oscillator status
+    OSC20MSbm = $10;
+    // 32KHz oscillator status
+    OSC32KSbm = $20;
+    // System Oscillator changing
+    SOSCbm = $01;
+    // 32.768 kHz Crystal Oscillator status
+    XOSC32KSbm = $40;
+    // Calibration
+    CAL20M0bm = $01;
+    CAL20M1bm = $02;
+    CAL20M2bm = $04;
+    CAL20M3bm = $08;
+    CAL20M4bm = $10;
+    CAL20M5bm = $20;
+    CAL20M6bm = $40;
+    // Lock
+    LOCKbm = $80;
+    // Oscillator temperature coefficient
+    TEMPCAL20M0bm = $01;
+    TEMPCAL20M1bm = $02;
+    TEMPCAL20M2bm = $04;
+    TEMPCAL20M3bm = $08;
+    // Run standby
+    RUNSTDBYbm = $02;
+    // CLKCTRL_CSUT
+    CSUTmask = $30;
+    CSUT_1K = $00;
+    CSUT_16K = $10;
+    CSUT_32K = $20;
+    CSUT_64K = $30;
+    // Enable
+    ENABLEbm = $01;
+    // Select
+    SELbm = $04;
+  end;
+
+  TCPU = object //CPU
+    Reserved0: byte;
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    CCP: byte;  //Configuration Change Protection
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    RAMPZ: byte;  //Extended Z-pointer Register
+    Reserved12: byte;
+    SPL: byte;  //Stack Pointer Low
+    SPH: byte;  //Stack Pointer High
+    SREG: byte;  //Status Register
+  const
+    // CPU_CCP
+    CCPmask = $FF;
+    CCP_SPM = $9D;
+    CCP_IOREG = $D8;
+    // Carry Flag
+    Cbm = $01;
+    // Half Carry Flag
+    Hbm = $20;
+    // Global Interrupt Enable Flag
+    Ibm = $80;
+    // Negative Flag
+    Nbm = $04;
+    // N Exclusive Or V Flag
+    Sbm = $10;
+    // Transfer Bit
+    Tbm = $40;
+    // Two's Complement Overflow Flag
+    Vbm = $08;
+    // Zero Flag
+    Zbm = $02;
+  end;
+
+  TCPUINT = object //Interrupt Controller
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    LVL0PRI: byte;  //Interrupt Level 0 Priority
+    LVL1VEC: byte;  //Interrupt Level 1 Priority Vector
+  const
+    // Compact Vector Table
+    CVTbm = $20;
+    // Interrupt Vector Select
+    IVSELbm = $40;
+    // Round-robin Scheduling Enable
+    LVL0RRbm = $01;
+    // Interrupt Level Priority
+    LVL0PRI0bm = $01;
+    LVL0PRI1bm = $02;
+    LVL0PRI2bm = $04;
+    LVL0PRI3bm = $08;
+    LVL0PRI4bm = $10;
+    LVL0PRI5bm = $20;
+    LVL0PRI6bm = $40;
+    LVL0PRI7bm = $80;
+    // Interrupt Vector with High Priority
+    LVL1VEC0bm = $01;
+    LVL1VEC1bm = $02;
+    LVL1VEC2bm = $04;
+    LVL1VEC3bm = $08;
+    LVL1VEC4bm = $10;
+    LVL1VEC5bm = $20;
+    LVL1VEC6bm = $40;
+    LVL1VEC7bm = $80;
+    // Level 0 Interrupt Executing
+    LVL0EXbm = $01;
+    // Level 1 Interrupt Executing
+    LVL1EXbm = $02;
+    // Non-maskable Interrupt Executing
+    NMIEXbm = $80;
+  end;
+
+  TCRCSCAN = object //CRCSCAN
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+  const
+    // Enable CRC scan
+    ENABLEbm = $01;
+    // Enable NMI Trigger
+    NMIENbm = $02;
+    // Reset CRC scan
+    RESETbm = $80;
+    // CRCSCAN_SRC
+    SRCmask = $03;
+    SRC_FLASH = $00;
+    SRC_APPLICATION = $01;
+    SRC_BOOT = $02;
+    // CRC Busy
+    BUSYbm = $01;
+    // CRC Ok
+    OKbm = $02;
+  end;
+
+  TEVSYS = object //Event System
+    SWEVENTA: byte;  //Software Event A
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    CHANNEL0: byte;  //Multiplexer Channel 0
+    CHANNEL1: byte;  //Multiplexer Channel 1
+    CHANNEL2: byte;  //Multiplexer Channel 2
+    CHANNEL3: byte;  //Multiplexer Channel 3
+    CHANNEL4: byte;  //Multiplexer Channel 4
+    CHANNEL5: byte;  //Multiplexer Channel 5
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    USERCCLLUT0A: byte;  //User CCL LUT0 Event A
+    USERCCLLUT0B: byte;  //User CCL LUT0 Event B
+    USERCCLLUT1A: byte;  //User CCL LUT1 Event A
+    USERCCLLUT1B: byte;  //User CCL LUT1 Event B
+    USERCCLLUT2A: byte;  //User CCL LUT2 Event A
+    USERCCLLUT2B: byte;  //User CCL LUT2 Event B
+    USERCCLLUT3A: byte;  //User CCL LUT3 Event A
+    USERCCLLUT3B: byte;  //User CCL LUT3 Event B
+    USERADC0START: byte;  //User ADC0
+    USEREVSYSEVOUTA: byte;  //User EVOUT Port A
+    USEREVSYSEVOUTB: byte;  //User EVOUT Port B
+    USEREVSYSEVOUTC: byte;  //User EVOUT Port C
+    USERUSART0IRDA: byte;  //User USART0
+    USERUSART1IRDA: byte;  //User USART1
+    USERTCA0CNTA: byte;  //User TCA0 count event
+    USERTCA0CNTB: byte;  //User TCA0 Restart event
+    USERTCB0CAPT: byte;  //User TCB0 Event in A
+    USERTCB0COUNT: byte;  //User TCB0 Event in B
+    USERTCB1CAPT: byte;  //User TCB1 Event in A
+    USERTCB1COUNT: byte;  //User TCB1 Event in B
+  const
+    // EVSYS_CHANNEL0
+    CHANNEL0mask = $FF;
+    CHANNEL0_OFF = $00;
+    CHANNEL0_UPDI = $01;
+    CHANNEL0_RTC_OVF = $06;
+    CHANNEL0_RTC_CMP = $07;
+    CHANNEL0_RTC_PIT_DIV8192 = $08;
+    CHANNEL0_RTC_PIT_DIV4096 = $09;
+    CHANNEL0_RTC_PIT_DIV2048 = $0A;
+    CHANNEL0_RTC_PIT_DIV1024 = $0B;
+    CHANNEL0_CCL_LUT0 = $10;
+    CHANNEL0_CCL_LUT1 = $11;
+    CHANNEL0_CCL_LUT2 = $12;
+    CHANNEL0_CCL_LUT3 = $13;
+    CHANNEL0_AC0_OUT = $20;
+    CHANNEL0_ADC0_RES = $24;
+    CHANNEL0_ADC0_SAMP = $25;
+    CHANNEL0_ADC0_WCMP = $26;
+    CHANNEL0_PORTA_PIN0 = $40;
+    CHANNEL0_PORTA_PIN1 = $41;
+    CHANNEL0_PORTA_PIN2 = $42;
+    CHANNEL0_PORTA_PIN3 = $43;
+    CHANNEL0_PORTA_PIN4 = $44;
+    CHANNEL0_PORTA_PIN5 = $45;
+    CHANNEL0_PORTA_PIN6 = $46;
+    CHANNEL0_PORTA_PIN7 = $47;
+    CHANNEL0_PORTB_PIN0 = $48;
+    CHANNEL0_PORTB_PIN1 = $49;
+    CHANNEL0_PORTB_PIN2 = $4A;
+    CHANNEL0_PORTB_PIN3 = $4B;
+    CHANNEL0_PORTB_PIN4 = $4C;
+    CHANNEL0_PORTB_PIN5 = $4D;
+    CHANNEL0_PORTB_PIN6 = $4E;
+    CHANNEL0_PORTB_PIN7 = $4F;
+    CHANNEL0_USART0_XCK = $60;
+    CHANNEL0_USART1_XCK = $61;
+    CHANNEL0_SPI0_SCK = $68;
+    CHANNEL0_TCA0_OVF_LUNF = $80;
+    CHANNEL0_TCA0_HUNF = $81;
+    CHANNEL0_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL0_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL0_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL0_TCB0_CAPT = $A0;
+    CHANNEL0_TCB0_OVF = $A1;
+    CHANNEL0_TCB1_CAPT = $A2;
+    CHANNEL0_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL1
+    CHANNEL1mask = $FF;
+    CHANNEL1_OFF = $00;
+    CHANNEL1_UPDI = $01;
+    CHANNEL1_RTC_OVF = $06;
+    CHANNEL1_RTC_CMP = $07;
+    CHANNEL1_RTC_PIT_DIV512 = $08;
+    CHANNEL1_RTC_PIT_DIV256 = $09;
+    CHANNEL1_RTC_PIT_DIV128 = $0A;
+    CHANNEL1_RTC_PIT_DIV64 = $0B;
+    CHANNEL1_CCL_LUT0 = $10;
+    CHANNEL1_CCL_LUT1 = $11;
+    CHANNEL1_CCL_LUT2 = $12;
+    CHANNEL1_CCL_LUT3 = $13;
+    CHANNEL1_AC0_OUT = $20;
+    CHANNEL1_ADC0_RES = $24;
+    CHANNEL1_ADC0_SAMP = $25;
+    CHANNEL1_ADC0_WCMP = $26;
+    CHANNEL1_PORTA_PIN0 = $40;
+    CHANNEL1_PORTA_PIN1 = $41;
+    CHANNEL1_PORTA_PIN2 = $42;
+    CHANNEL1_PORTA_PIN3 = $43;
+    CHANNEL1_PORTA_PIN4 = $44;
+    CHANNEL1_PORTA_PIN5 = $45;
+    CHANNEL1_PORTA_PIN6 = $46;
+    CHANNEL1_PORTA_PIN7 = $47;
+    CHANNEL1_PORTB_PIN0 = $48;
+    CHANNEL1_PORTB_PIN1 = $49;
+    CHANNEL1_PORTB_PIN2 = $4A;
+    CHANNEL1_PORTB_PIN3 = $4B;
+    CHANNEL1_PORTB_PIN4 = $4C;
+    CHANNEL1_PORTB_PIN5 = $4D;
+    CHANNEL1_PORTB_PIN6 = $4E;
+    CHANNEL1_PORTB_PIN7 = $4F;
+    CHANNEL1_USART0_XCK = $60;
+    CHANNEL1_USART1_XCK = $61;
+    CHANNEL1_SPI0_SCK = $68;
+    CHANNEL1_TCA0_OVF_LUNF = $80;
+    CHANNEL1_TCA0_HUNF = $81;
+    CHANNEL1_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL1_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL1_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL1_TCB0_CAPT = $A0;
+    CHANNEL1_TCB0_OVF = $A1;
+    CHANNEL1_TCB1_CAPT = $A2;
+    CHANNEL1_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL2
+    CHANNEL2mask = $FF;
+    CHANNEL2_OFF = $00;
+    CHANNEL2_UPDI = $01;
+    CHANNEL2_RTC_OVF = $06;
+    CHANNEL2_RTC_CMP = $07;
+    CHANNEL2_RTC_PIT_DIV8192 = $08;
+    CHANNEL2_RTC_PIT_DIV4096 = $09;
+    CHANNEL2_RTC_PIT_DIV2048 = $0A;
+    CHANNEL2_RTC_PIT_DIV1024 = $0B;
+    CHANNEL2_CCL_LUT0 = $10;
+    CHANNEL2_CCL_LUT1 = $11;
+    CHANNEL2_CCL_LUT2 = $12;
+    CHANNEL2_CCL_LUT3 = $13;
+    CHANNEL2_AC0_OUT = $20;
+    CHANNEL2_ADC0_RES = $24;
+    CHANNEL2_ADC0_SAMP = $25;
+    CHANNEL2_ADC0_WCMP = $26;
+    CHANNEL2_PORTC_PIN0 = $40;
+    CHANNEL2_PORTC_PIN1 = $41;
+    CHANNEL2_PORTC_PIN2 = $42;
+    CHANNEL2_PORTC_PIN3 = $43;
+    CHANNEL2_PORTC_PIN4 = $44;
+    CHANNEL2_PORTC_PIN5 = $45;
+    CHANNEL2_PORTC_PIN6 = $46;
+    CHANNEL2_PORTC_PIN7 = $47;
+    CHANNEL2_PORTA_PIN0 = $48;
+    CHANNEL2_PORTA_PIN1 = $49;
+    CHANNEL2_PORTA_PIN2 = $4A;
+    CHANNEL2_PORTA_PIN3 = $4B;
+    CHANNEL2_PORTA_PIN4 = $4C;
+    CHANNEL2_PORTA_PIN5 = $4D;
+    CHANNEL2_PORTA_PIN6 = $4E;
+    CHANNEL2_PORTA_PIN7 = $4F;
+    CHANNEL2_USART0_XCK = $60;
+    CHANNEL2_USART1_XCK = $61;
+    CHANNEL2_SPI0_SCK = $68;
+    CHANNEL2_TCA0_OVF_LUNF = $80;
+    CHANNEL2_TCA0_HUNF = $81;
+    CHANNEL2_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL2_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL2_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL2_TCB0_CAPT = $A0;
+    CHANNEL2_TCB0_OVF = $A1;
+    CHANNEL2_TCB1_CAPT = $A2;
+    CHANNEL2_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL3
+    CHANNEL3mask = $FF;
+    CHANNEL3_OFF = $00;
+    CHANNEL3_UPDI = $01;
+    CHANNEL3_RTC_OVF = $06;
+    CHANNEL3_RTC_CMP = $07;
+    CHANNEL3_RTC_PIT_DIV512 = $08;
+    CHANNEL3_RTC_PIT_DIV256 = $09;
+    CHANNEL3_RTC_PIT_DIV128 = $0A;
+    CHANNEL3_RTC_PIT_DIV64 = $0B;
+    CHANNEL3_CCL_LUT0 = $10;
+    CHANNEL3_CCL_LUT1 = $11;
+    CHANNEL3_CCL_LUT2 = $12;
+    CHANNEL3_CCL_LUT3 = $13;
+    CHANNEL3_AC0_OUT = $20;
+    CHANNEL3_ADC0_RES = $24;
+    CHANNEL3_ADC0_SAMP = $25;
+    CHANNEL3_ADC0_WCMP = $26;
+    CHANNEL3_PORTC_PIN0 = $40;
+    CHANNEL3_PORTC_PIN1 = $41;
+    CHANNEL3_PORTC_PIN2 = $42;
+    CHANNEL3_PORTC_PIN3 = $43;
+    CHANNEL3_PORTC_PIN4 = $44;
+    CHANNEL3_PORTC_PIN5 = $45;
+    CHANNEL3_PORTC_PIN6 = $46;
+    CHANNEL3_PORTC_PIN7 = $47;
+    CHANNEL3_PORTA_PIN0 = $48;
+    CHANNEL3_PORTA_PIN1 = $49;
+    CHANNEL3_PORTA_PIN2 = $4A;
+    CHANNEL3_PORTA_PIN3 = $4B;
+    CHANNEL3_PORTA_PIN4 = $4C;
+    CHANNEL3_PORTA_PIN5 = $4D;
+    CHANNEL3_PORTA_PIN6 = $4E;
+    CHANNEL3_PORTA_PIN7 = $4F;
+    CHANNEL3_USART0_XCK = $60;
+    CHANNEL3_USART1_XCK = $61;
+    CHANNEL3_SPI0_SCK = $68;
+    CHANNEL3_TCA0_OVF_LUNF = $80;
+    CHANNEL3_TCA0_HUNF = $81;
+    CHANNEL3_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL3_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL3_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL3_TCB0_CAPT = $A0;
+    CHANNEL3_TCB0_OVF = $A1;
+    CHANNEL3_TCB1_CAPT = $A2;
+    CHANNEL3_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL4
+    CHANNEL4mask = $FF;
+    CHANNEL4_OFF = $00;
+    CHANNEL4_UPDI = $01;
+    CHANNEL4_RTC_OVF = $06;
+    CHANNEL4_RTC_CMP = $07;
+    CHANNEL4_RTC_PIT_DIV8192 = $08;
+    CHANNEL4_RTC_PIT_DIV4096 = $09;
+    CHANNEL4_RTC_PIT_DIV2048 = $0A;
+    CHANNEL4_RTC_PIT_DIV1024 = $0B;
+    CHANNEL4_CCL_LUT0 = $10;
+    CHANNEL4_CCL_LUT1 = $11;
+    CHANNEL4_CCL_LUT2 = $12;
+    CHANNEL4_CCL_LUT3 = $13;
+    CHANNEL4_AC0_OUT = $20;
+    CHANNEL4_ADC0_RES = $24;
+    CHANNEL4_ADC0_SAMP = $25;
+    CHANNEL4_ADC0_WCMP = $26;
+    CHANNEL4_PORTB_PIN0 = $40;
+    CHANNEL4_PORTB_PIN1 = $41;
+    CHANNEL4_PORTB_PIN2 = $42;
+    CHANNEL4_PORTB_PIN3 = $43;
+    CHANNEL4_PORTB_PIN4 = $44;
+    CHANNEL4_PORTB_PIN5 = $45;
+    CHANNEL4_PORTB_PIN6 = $46;
+    CHANNEL4_PORTB_PIN7 = $47;
+    CHANNEL4_PORTC_PIN0 = $48;
+    CHANNEL4_PORTC_PIN1 = $49;
+    CHANNEL4_PORTC_PIN2 = $4A;
+    CHANNEL4_PORTC_PIN3 = $4B;
+    CHANNEL4_PORTC_PIN4 = $4C;
+    CHANNEL4_PORTC_PIN5 = $4D;
+    CHANNEL4_PORTC_PIN6 = $4E;
+    CHANNEL4_PORTC_PIN7 = $4F;
+    CHANNEL4_USART0_XCK = $60;
+    CHANNEL4_USART1_XCK = $61;
+    CHANNEL4_SPI0_SCK = $68;
+    CHANNEL4_TCA0_OVF_LUNF = $80;
+    CHANNEL4_TCA0_HUNF = $81;
+    CHANNEL4_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL4_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL4_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL4_TCB0_CAPT = $A0;
+    CHANNEL4_TCB0_OVF = $A1;
+    CHANNEL4_TCB1_CAPT = $A2;
+    CHANNEL4_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL5
+    CHANNEL5mask = $FF;
+    CHANNEL5_OFF = $00;
+    CHANNEL5_UPDI = $01;
+    CHANNEL5_RTC_OVF = $06;
+    CHANNEL5_RTC_CMP = $07;
+    CHANNEL5_RTC_PIT_DIV512 = $08;
+    CHANNEL5_RTC_PIT_DIV256 = $09;
+    CHANNEL5_RTC_PIT_DIV128 = $0A;
+    CHANNEL5_RTC_PIT_DIV64 = $0B;
+    CHANNEL5_CCL_LUT0 = $10;
+    CHANNEL5_CCL_LUT1 = $11;
+    CHANNEL5_CCL_LUT2 = $12;
+    CHANNEL5_CCL_LUT3 = $13;
+    CHANNEL5_AC0_OUT = $20;
+    CHANNEL5_ADC0_RES = $24;
+    CHANNEL5_ADC0_SAMP = $25;
+    CHANNEL5_ADC0_WCMP = $26;
+    CHANNEL5_PORTB_PIN0 = $40;
+    CHANNEL5_PORTB_PIN1 = $41;
+    CHANNEL5_PORTB_PIN2 = $42;
+    CHANNEL5_PORTB_PIN3 = $43;
+    CHANNEL5_PORTB_PIN4 = $44;
+    CHANNEL5_PORTB_PIN5 = $45;
+    CHANNEL5_PORTB_PIN6 = $46;
+    CHANNEL5_PORTB_PIN7 = $47;
+    CHANNEL5_PORTC_PIN0 = $48;
+    CHANNEL5_PORTC_PIN1 = $49;
+    CHANNEL5_PORTC_PIN2 = $4A;
+    CHANNEL5_PORTC_PIN3 = $4B;
+    CHANNEL5_PORTC_PIN4 = $4C;
+    CHANNEL5_PORTC_PIN5 = $4D;
+    CHANNEL5_PORTC_PIN6 = $4E;
+    CHANNEL5_PORTC_PIN7 = $4F;
+    CHANNEL5_USART0_XCK = $60;
+    CHANNEL5_USART1_XCK = $61;
+    CHANNEL5_SPI0_SCK = $68;
+    CHANNEL5_TCA0_OVF_LUNF = $80;
+    CHANNEL5_TCA0_HUNF = $81;
+    CHANNEL5_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL5_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL5_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL5_TCB0_CAPT = $A0;
+    CHANNEL5_TCB0_OVF = $A1;
+    CHANNEL5_TCB1_CAPT = $A2;
+    CHANNEL5_TCB1_OVF = $A3;
+    // EVSYS_SWEVENTA
+    SWEVENTAmask = $FF;
+    SWEVENTA_CH0 = $01;
+    SWEVENTA_CH1 = $02;
+    SWEVENTA_CH2 = $04;
+    SWEVENTA_CH3 = $08;
+    SWEVENTA_CH4 = $10;
+    SWEVENTA_CH5 = $20;
+    // EVSYS_USER
+    USERmask = $FF;
+    USER_OFF = $00;
+    USER_CHANNEL0 = $01;
+    USER_CHANNEL1 = $02;
+    USER_CHANNEL2 = $03;
+    USER_CHANNEL3 = $04;
+    USER_CHANNEL4 = $05;
+    USER_CHANNEL5 = $06;
+  end;
+
+  TFUSE = object //Fuses
+    WDTCFG: byte;  //Watchdog Configuration
+    BODCFG: byte;  //BOD Configuration
+    OSCCFG: byte;  //Oscillator Configuration
+    Reserved3: byte;
+    Reserved4: byte;
+    SYSCFG0: byte;  //System Configuration 0
+    SYSCFG1: byte;  //System Configuration 1
+    APPEND: byte;  //Application Code Section End
+    BOOTEND: byte;  //Boot Section End
+  const
+    // FUSE_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // FUSE_LVL
+    LVLmask = $E0;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $40;
+    LVL_BODLEVEL7 = $E0;
+    // FUSE_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // FUSE_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // FUSE_FREQSEL
+    FREQSELmask = $03;
+    FREQSEL_16MHZ = $01;
+    FREQSEL_20MHZ = $02;
+    // Oscillator Lock
+    OSCLOCKbm = $80;
+    // FUSE_CRCSRC
+    CRCSRCmask = $C0;
+    CRCSRC_FLASH = $00;
+    CRCSRC_BOOT = $40;
+    CRCSRC_BOOTAPP = $80;
+    CRCSRC_NOCRC = $C0;
+    // EEPROM Save
+    EESAVEbm = $01;
+    // FUSE_RSTPINCFG
+    RSTPINCFGmask = $0C;
+    RSTPINCFG_GPIO = $00;
+    RSTPINCFG_UPDI = $04;
+    RSTPINCFG_RST = $08;
+    RSTPINCFG_PDIRST = $0C;
+    // FUSE_SUT
+    SUTmask = $07;
+    SUT_0MS = $00;
+    SUT_1MS = $01;
+    SUT_2MS = $02;
+    SUT_4MS = $03;
+    SUT_8MS = $04;
+    SUT_16MS = $05;
+    SUT_32MS = $06;
+    SUT_64MS = $07;
+    // FUSE_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // FUSE_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+  end;
+
+  TGPIO = object //General Purpose IO
+    GPIOR0: byte;  //General Purpose IO Register 0
+    GPIOR1: byte;  //General Purpose IO Register 1
+    GPIOR2: byte;  //General Purpose IO Register 2
+    GPIOR3: byte;  //General Purpose IO Register 3
+  end;
+
+  TLOCKBIT = object //Lockbit
+    LOCKBIT: byte;  //Lock Bits
+  const
+    // LOCKBIT_LB
+    LBmask = $FF;
+    LB_RWLOCK = $3A;
+    LB_NOLOCK = $C5;
+  end;
+
+  TNVMBIST = object //BIST in the NVMCTRL module
+    CTRLA: byte;  //Control A
+    ADDRPAT: byte;  //Address pattern
+    DATAPAT: byte;  //Data pattern
+    STATUS: byte;  //Status
+    CNT: word;
+    END_: dword;
+  const
+    // NVMBIST_AMODE
+    AMODEmask = $70;
+    AMODE_NORMAL = $00;
+    AMODE_COMPLEMENT = $40;
+    // NVMBIST_XMODE
+    XMODEmask = $03;
+    XMODE_STATIC = $00;
+    XMODE_CARRY = $01;
+    XMODE_INC = $02;
+    XMODE_DEC = $03;
+    // NVMBIST_YMODE
+    YMODEmask = $0C;
+    YMODE_STATIC = $00;
+    YMODE_CARRY = $04;
+    YMODE_INC = $08;
+    YMODE_DEC = $0C;
+    // Faults counter
+    CNT0bm = $01;
+    CNT1bm = $02;
+    CNT2bm = $04;
+    CNT3bm = $08;
+    CNT4bm = $10;
+    CNT5bm = $20;
+    CNT6bm = $40;
+    CNT7bm = $80;
+    // NVMBIST_CMD
+    CMDmask = $07;
+    CMD_NOCMD = $00;
+    CMD_START = $01;
+    CMD_RESTART = $02;
+    CMD_BREAK = $03;
+    // Stop at fault
+    SAFbm = $08;
+    // NVMBIST_PATTERN
+    PATTERNmask = $03;
+    PATTERN_ZEROES = $00;
+    PATTERN_CHECK = $01;
+    PATTERN_INVCHECK = $02;
+    PATTERN_ONES = $03;
+    // 
+    END0bm = $01;
+    END1bm = $02;
+    END2bm = $04;
+    END3bm = $08;
+    END4bm = $10;
+    END5bm = $20;
+    END6bm = $40;
+    END7bm = $80;
+    // NVMBIST_STATE
+    STATEmask = $0F;
+    STATE_IDLE = $00;
+    STATE_BREAK = $01;
+    STATE_FAILED0 = $04;
+    STATE_FAILED1 = $05;
+    STATE_FAILED2 = $06;
+    STATE_SUCCESS = $07;
+    STATE_START0 = $08;
+    STATE_START1 = $09;
+    STATE_RESTART0 = $0A;
+    STATE_RESTART1 = $0B;
+    STATE_RUNNING = $0C;
+    STATE_FINISH0 = $0E;
+    STATE_FINISH1 = $0F;
+  end;
+
+  TNVMCTRL = object //Non-volatile Memory Controller
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved5: byte;
+    DATA: word;  //Data
+    ADDR: word;  //Address
+  const
+    // NVMCTRL_CMD
+    CMDmask = $07;
+    CMD_NONE = $00;
+    CMD_PAGEWRITE = $01;
+    CMD_PAGEERASE = $02;
+    CMD_PAGEERASEWRITE = $03;
+    CMD_PAGEBUFCLR = $04;
+    CMD_CHIPERASE = $05;
+    CMD_EEERASE = $06;
+    CMD_FUSEWRITE = $07;
+    // Application code write protect
+    APCWPbm = $01;
+    // Boot Lock
+    BOOTLOCKbm = $02;
+    // EEPROM Ready
+    EEREADYbm = $01;
+    // EEPROM busy
+    EEBUSYbm = $02;
+    // Flash busy
+    FBUSYbm = $01;
+    // Write error
+    WRERRORbm = $04;
+  end;
+
+  TPORT = object //I/O Ports
+    DIR: byte;  //Data Direction
+    DIRSET: byte;  //Data Direction Set
+    DIRCLR: byte;  //Data Direction Clear
+    DIRTGL: byte;  //Data Direction Toggle
+    OUT_: byte;  //Output Value
+    OUTSET: byte;  //Output Value Set
+    OUTCLR: byte;  //Output Value Clear
+    OUTTGL: byte;  //Output Value Toggle
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+    PORTCTRL: byte;  //Port Control
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    PIN0CTRL: byte;  //Pin 0 Control
+    PIN1CTRL: byte;  //Pin 1 Control
+    PIN2CTRL: byte;  //Pin 2 Control
+    PIN3CTRL: byte;  //Pin 3 Control
+    PIN4CTRL: byte;  //Pin 4 Control
+    PIN5CTRL: byte;  //Pin 5 Control
+    PIN6CTRL: byte;  //Pin 6 Control
+    PIN7CTRL: byte;  //Pin 7 Control
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+    // Inverted I/O Enable
+    INVENbm = $80;
+    // PORT_ISC
+    ISCmask = $07;
+    ISC_INTDISABLE = $00;
+    ISC_BOTHEDGES = $01;
+    ISC_RISING = $02;
+    ISC_FALLING = $03;
+    ISC_INPUT_DISABLE = $04;
+    ISC_LEVEL = $05;
+    // Pullup enable
+    PULLUPENbm = $08;
+    // Slew Rate Limit Enable
+    SRLbm = $01;
+  end;
+
+  TPORTMUX = object //Port Multiplexer
+    EVSYSROUTEA: byte;  //Port Multiplexer EVSYS
+    CCLROUTEA: byte;  //Port Multiplexer CCL
+    USARTROUTEA: byte;  //Port Multiplexer USART register A
+    SPIROUTEA: byte;  //Port Multiplexer TWI and SPI
+    TCAROUTEA: byte;  //Port Multiplexer TCA
+    TCBROUTEA: byte;  //Port Multiplexer TCB
+  const
+    // CCL LUT0
+    LUT0bm = $01;
+    // CCL LUT1
+    LUT1bm = $02;
+    // CCL LUT2
+    LUT2bm = $04;
+    // CCL LUT3
+    LUT3bm = $08;
+    // Event Output 0
+    EVOUT0bm = $01;
+    // Event Output 1
+    EVOUT1bm = $02;
+    // Event Output 2
+    EVOUT2bm = $04;
+    // Event Output 3
+    EVOUT3bm = $08;
+    // Event Output 4
+    EVOUT4bm = $10;
+    // Event Output 5
+    EVOUT5bm = $20;
+    // PORTMUX_SPI0
+    SPI0mask = $03;
+    SPI0_DEFAULT = $00;
+    SPI0_ALT1 = $01;
+    SPI0_ALT2 = $02;
+    SPI0_NONE = $03;
+    // PORTMUX_TWI0
+    TWI0mask = $30;
+    TWI0_DEFAULT = $00;
+    TWI0_ALT1 = $10;
+    TWI0_ALT2 = $20;
+    TWI0_NONE = $30;
+    // PORTMUX_TCA0
+    TCA0mask = $07;
+    TCA0_PORTA = $00;
+    TCA0_PORTB = $01;
+    TCA0_PORTC = $02;
+    TCA0_PORTD = $03;
+    TCA0_PORTE = $04;
+    TCA0_PORTF = $05;
+    // Port Multiplexer TCB0
+    TCB0bm = $01;
+    // Port Multiplexer TCB1
+    TCB1bm = $02;
+    // Port Multiplexer TCB2
+    TCB2bm = $04;
+    // Port Multiplexer TCB3
+    TCB3bm = $08;
+    // PORTMUX_USART0
+    USART0mask = $03;
+    USART0_DEFAULT = $00;
+    USART0_ALT1 = $01;
+    USART0_NONE = $03;
+    // PORTMUX_USART1
+    USART1mask = $0C;
+    USART1_DEFAULT = $00;
+    USART1_ALT1 = $04;
+    USART1_NONE = $0C;
+  end;
+
+  TRSTCTRL = object //Reset controller
+    RSTFR: byte;  //Reset Flags
+    SWRR: byte;  //Software Reset
+  const
+    // Brown out detector Reset flag
+    BORFbm = $02;
+    // External Reset flag
+    EXTRFbm = $04;
+    // Power on Reset flag
+    PORFbm = $01;
+    // Software Reset flag
+    SWRFbm = $10;
+    // UPDI Reset flag
+    UPDIRFbm = $20;
+    // Watch dog Reset flag
+    WDRFbm = $08;
+    // Software reset enable
+    SWREbm = $01;
+  end;
+
+  TRTC = object //Real-Time Counter
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    TEMP: byte;  //Temporary
+    DBGCTRL: byte;  //Debug control
+    CALIB: byte;  //Calibration
+    CLKSEL: byte;  //RTC Clock
+    CNT: word;  //Counter
+    PER: word;  //Period
+    CMP: word;  //Compare
+    Reserved14: byte;
+    Reserved15: byte;
+    PITCTRLA: byte;  //PIT Control A
+    PITSTATUS: byte;  //PIT Status
+    PITINTCTRL: byte;  //PIT Interrupt Control
+    PITINTFLAGS: byte;  //PIT Interrupt Flags
+    Reserved20: byte;
+    PITDBGCTRL: byte;  //PIT Debug control
+  const
+    // Error Correction Value
+    ERROR0bm = $01;
+    ERROR1bm = $02;
+    ERROR2bm = $04;
+    ERROR3bm = $08;
+    ERROR4bm = $10;
+    ERROR5bm = $20;
+    ERROR6bm = $40;
+    // Error Correction Sign Bit
+    SIGNbm = $80;
+    // RTC_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_INT32K = $00;
+    CLKSEL_INT1K = $01;
+    CLKSEL_TOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // Correction enable
+    CORRENbm = $04;
+    // RTC_PRESCALER
+    PRESCALERmask = $78;
+    PRESCALER_DIV1 = $00;
+    PRESCALER_DIV2 = $08;
+    PRESCALER_DIV4 = $10;
+    PRESCALER_DIV8 = $18;
+    PRESCALER_DIV16 = $20;
+    PRESCALER_DIV32 = $28;
+    PRESCALER_DIV64 = $30;
+    PRESCALER_DIV128 = $38;
+    PRESCALER_DIV256 = $40;
+    PRESCALER_DIV512 = $48;
+    PRESCALER_DIV1024 = $50;
+    PRESCALER_DIV2048 = $58;
+    PRESCALER_DIV4096 = $60;
+    PRESCALER_DIV8192 = $68;
+    PRESCALER_DIV16384 = $70;
+    PRESCALER_DIV32768 = $78;
+    // Enable
+    RTCENbm = $01;
+    // Run In Standby
+    RUNSTDBYbm = $80;
+    // Run in debug
+    DBGRUNbm = $01;
+    // Compare Match Interrupt enable
+    CMPbm = $02;
+    // Overflow Interrupt enable
+    OVFbm = $01;
+    // RTC_PERIOD
+    PERIODmask = $78;
+    PERIOD_OFF = $00;
+    PERIOD_CYC4 = $08;
+    PERIOD_CYC8 = $10;
+    PERIOD_CYC16 = $18;
+    PERIOD_CYC32 = $20;
+    PERIOD_CYC64 = $28;
+    PERIOD_CYC128 = $30;
+    PERIOD_CYC256 = $38;
+    PERIOD_CYC512 = $40;
+    PERIOD_CYC1024 = $48;
+    PERIOD_CYC2048 = $50;
+    PERIOD_CYC4096 = $58;
+    PERIOD_CYC8192 = $60;
+    PERIOD_CYC16384 = $68;
+    PERIOD_CYC32768 = $70;
+    // Enable
+    PITENbm = $01;
+    // Periodic Interrupt
+    PIbm = $01;
+    // CTRLA Synchronization Busy Flag
+    CTRLBUSYbm = $01;
+    // Comparator Synchronization Busy Flag
+    CMPBUSYbm = $08;
+    // Count Synchronization Busy Flag
+    CNTBUSYbm = $02;
+    // CTRLA Synchronization Busy Flag
+    CTRLABUSYbm = $01;
+    // Period Synchronization Busy Flag
+    PERBUSYbm = $04;
+  end;
+
+  TSIGROW = object //Signature row
+    DEVICEID0: byte;  //Device ID Byte 0
+    DEVICEID1: byte;  //Device ID Byte 1
+    DEVICEID2: byte;  //Device ID Byte 2
+    SERNUM0: byte;  //Serial Number Byte 0
+    SERNUM1: byte;  //Serial Number Byte 1
+    SERNUM2: byte;  //Serial Number Byte 2
+    SERNUM3: byte;  //Serial Number Byte 3
+    SERNUM4: byte;  //Serial Number Byte 4
+    SERNUM5: byte;  //Serial Number Byte 5
+    SERNUM6: byte;  //Serial Number Byte 6
+    SERNUM7: byte;  //Serial Number Byte 7
+    SERNUM8: byte;  //Serial Number Byte 8
+    SERNUM9: byte;  //Serial Number Byte 9
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    OSCCAL32K: byte;  //Oscillator Calibration for 32kHz ULP
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSCCAL16M0: byte;  //Oscillator Calibration 16 MHz Byte 0
+    OSCCAL16M1: byte;  //Oscillator Calibration 16 MHz Byte 1
+    OSCCAL20M0: byte;  //Oscillator Calibration 20 MHz Byte 0
+    OSCCAL20M1: byte;  //Oscillator Calibration 20 MHz Byte 1
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    TEMPSENSE0: byte;  //Temperature Sensor Calibration Byte 0
+    TEMPSENSE1: byte;  //Temperature Sensor Calibration Byte 1
+    OSC16ERR3V: byte;  //OSC16 error at 3V
+    OSC16ERR5V: byte;  //OSC16 error at 5V
+    OSC20ERR3V: byte;  //OSC20 error at 3V
+    OSC20ERR5V: byte;  //OSC20 error at 5V
+    Reserved38: byte;
+    Reserved39: byte;
+    Reserved40: byte;
+    Reserved41: byte;
+    Reserved42: byte;
+    Reserved43: byte;
+    Reserved44: byte;
+    Reserved45: byte;
+    Reserved46: byte;
+    CHECKSUM1: byte;  //CRC Checksum Byte 1
+  end;
+
+  TSLPCTRL = object //Sleep Controller
+    CTRLA: byte;  //Control
+  const
+    // Sleep enable
+    SENbm = $01;
+    // SLPCTRL_SMODE
+    SMODEmask = $06;
+    SMODE_IDLE = $00;
+    SMODE_STDBY = $02;
+    SMODE_PDOWN = $04;
+  end;
+
+  TSPI = object //Serial Peripheral Interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    DATA: byte;  //Data
+  const
+    // Enable Double Speed
+    CLK2Xbm = $10;
+    // Data Order Setting
+    DORDbm = $40;
+    // Enable Module
+    ENABLEbm = $01;
+    // Master Operation Enable
+    MASTERbm = $20;
+    // SPI_PRESC
+    PRESCmask = $06;
+    PRESC_DIV4 = $00;
+    PRESC_DIV16 = $02;
+    PRESC_DIV64 = $04;
+    PRESC_DIV128 = $06;
+    // Buffer Mode Enable
+    BUFENbm = $80;
+    // Buffer Mode Wait for Receive
+    BUFWRbm = $40;
+    // SPI_MODE
+    MODEmask = $03;
+    MODE_0 = $00;
+    MODE_1 = $01;
+    MODE_2 = $02;
+    MODE_3 = $03;
+    // Slave Select Disable
+    SSDbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Interrupt Enable
+    IEbm = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Slave Select Trigger Interrupt Enable
+    SSIEbm = $10;
+    // Transfer Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Buffer Overflow
+    BUFOVFbm = $01;
+    // Data Register Empty Interrupt Flag
+    DREIFbm = $20;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // Slave Select Trigger Interrupt Flag
+    SSIFbm = $10;
+    // Transfer Complete Interrupt Flag
+    TXCIFbm = $40;
+    // Interrupt Flag
+    IFbm = $80;
+    // Write Collision
+    WRCOLbm = $40;
+  end;
+
+  TSYSCFG = object //System Configuration Registers
+    Reserved0: byte;
+    REVID: byte;  //Revision ID
+    EXTBRK: byte;  //External Break
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OCDM: byte;  //OCD Message Register
+    OCDMS: byte;  //OCD Message Status
+  const
+    // External break enable
+    ENEXTBRKbm = $01;
+    // OCD Message Read
+    OCDMRbm = $01;
+  end;
+
+  TTCA_SINGLE = object //16-bit Timer/Counter Type A - Single Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    CTRLFCLR: byte;  //Control F Clear
+    CTRLFSET: byte;  //Control F Set
+    Reserved8: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    TEMP: byte;  //Temporary data for 16-bit Access
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    CNT: word;  //Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    PER: word;  //Period
+    CMP0: word;  //Compare 0
+    CMP1: word;  //Compare 1
+    CMP2: word;  //Compare 2
+    Reserved46: byte;
+    Reserved47: byte;
+    Reserved48: byte;
+    Reserved49: byte;
+    Reserved50: byte;
+    Reserved51: byte;
+    Reserved52: byte;
+    Reserved53: byte;
+    PERBUF: word;  //Period Buffer
+    CMP0BUF: word;  //Compare 0 Buffer
+    CMP1BUF: word;  //Compare 1 Buffer
+    CMP2BUF: word;  //Compare 2 Buffer
+  const
+    // TCA_SINGLE_CLKSEL
+    SINGLE_CLKSELmask = $0E;
+    SINGLE_CLKSEL_DIV1 = $00;
+    SINGLE_CLKSEL_DIV2 = $02;
+    SINGLE_CLKSEL_DIV4 = $04;
+    SINGLE_CLKSEL_DIV8 = $06;
+    SINGLE_CLKSEL_DIV16 = $08;
+    SINGLE_CLKSEL_DIV64 = $0A;
+    SINGLE_CLKSEL_DIV256 = $0C;
+    SINGLE_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // Auto Lock Update
+    ALUPDbm = $08;
+    // Compare 0 Enable
+    CMP0ENbm = $10;
+    // Compare 1 Enable
+    CMP1ENbm = $20;
+    // Compare 2 Enable
+    CMP2ENbm = $40;
+    // TCA_SINGLE_WGMODE
+    SINGLE_WGMODEmask = $07;
+    SINGLE_WGMODE_NORMAL = $00;
+    SINGLE_WGMODE_FRQ = $01;
+    SINGLE_WGMODE_SINGLESLOPE = $03;
+    SINGLE_WGMODE_DSTOP = $05;
+    SINGLE_WGMODE_DSBOTH = $06;
+    SINGLE_WGMODE_DSBOTTOM = $07;
+    // Compare 0 Waveform Output Value
+    CMP0OVbm = $01;
+    // Compare 1 Waveform Output Value
+    CMP1OVbm = $02;
+    // Compare 2 Waveform Output Value
+    CMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SINGLE_CMD
+    SINGLE_CMDmask = $0C;
+    SINGLE_CMD_NONE = $00;
+    SINGLE_CMD_UPDATE = $04;
+    SINGLE_CMD_RESTART = $08;
+    SINGLE_CMD_RESET = $0C;
+    // Direction
+    DIRbm = $01;
+    // Lock Update
+    LUPDbm = $02;
+    // Compare 0 Buffer Valid
+    CMP0BVbm = $02;
+    // Compare 1 Buffer Valid
+    CMP1BVbm = $04;
+    // Compare 2 Buffer Valid
+    CMP2BVbm = $08;
+    // Period Buffer Valid
+    PERBVbm = $01;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Count on Event Input A
+    CNTAEIbm = $01;
+    // Count on Event Input B
+    CNTBEIbm = $10;
+    // TCA_SINGLE_EVACTA
+    SINGLE_EVACTAmask = $0E;
+    SINGLE_EVACTA_CNT_POSEDGE = $00;
+    SINGLE_EVACTA_CNT_ANYEDGE = $02;
+    SINGLE_EVACTA_CNT_HIGHLVL = $04;
+    SINGLE_EVACTA_UPDOWN = $06;
+    // TCA_SINGLE_EVACTB
+    SINGLE_EVACTBmask = $E0;
+    SINGLE_EVACTB_UPDOWN = $60;
+    SINGLE_EVACTB_RESTART_POSEDGE = $80;
+    SINGLE_EVACTB_RESTART_ANYEDGE = $A0;
+    SINGLE_EVACTB_RESTART_HIGHLVL = $C0;
+    // Compare 0 Interrupt
+    CMP0bm = $10;
+    // Compare 1 Interrupt
+    CMP1bm = $20;
+    // Compare 2 Interrupt
+    CMP2bm = $40;
+    // Overflow Interrupt
+    OVFbm = $01;
+  end;
+
+  TTCA_SPLIT = object //16-bit Timer/Counter Type A - Split Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    LCNT: byte;  //Low Count
+    HCNT: byte;  //High Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    LPER: byte;  //Low Period
+    HPER: byte;  //High Period
+    LCMP0: byte;  //Low Compare
+    HCMP0: byte;  //High Compare
+    LCMP1: byte;  //Low Compare
+    HCMP1: byte;  //High Compare
+    LCMP2: byte;  //Low Compare
+    HCMP2: byte;  //High Compare
+  const
+    // TCA_SPLIT_CLKSEL
+    SPLIT_CLKSELmask = $0E;
+    SPLIT_CLKSEL_DIV1 = $00;
+    SPLIT_CLKSEL_DIV2 = $02;
+    SPLIT_CLKSEL_DIV4 = $04;
+    SPLIT_CLKSEL_DIV8 = $06;
+    SPLIT_CLKSEL_DIV16 = $08;
+    SPLIT_CLKSEL_DIV64 = $0A;
+    SPLIT_CLKSEL_DIV256 = $0C;
+    SPLIT_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // High Compare 0 Enable
+    HCMP0ENbm = $10;
+    // High Compare 1 Enable
+    HCMP1ENbm = $20;
+    // High Compare 2 Enable
+    HCMP2ENbm = $40;
+    // Low Compare 0 Enable
+    LCMP0ENbm = $01;
+    // Low Compare 1 Enable
+    LCMP1ENbm = $02;
+    // Low Compare 2 Enable
+    LCMP2ENbm = $04;
+    // High Compare 0 Output Value
+    HCMP0OVbm = $10;
+    // High Compare 1 Output Value
+    HCMP1OVbm = $20;
+    // High Compare 2 Output Value
+    HCMP2OVbm = $40;
+    // Low Compare 0 Output Value
+    LCMP0OVbm = $01;
+    // Low Compare 1 Output Value
+    LCMP1OVbm = $02;
+    // Low Compare 2 Output Value
+    LCMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SPLIT_CMD
+    SPLIT_CMDmask = $0C;
+    SPLIT_CMD_NONE = $00;
+    SPLIT_CMD_UPDATE = $04;
+    SPLIT_CMD_RESTART = $08;
+    SPLIT_CMD_RESET = $0C;
+    // TCA_SPLIT_CMDEN
+    SPLIT_CMDENmask = $03;
+    SPLIT_CMDEN_NONE = $00;
+    SPLIT_CMDEN_BOTH = $03;
+    // Debug Run
+    DBGRUNbm = $01;
+    // High Underflow Interrupt Enable
+    HUNFbm = $02;
+    // Low Compare 0 Interrupt Enable
+    LCMP0bm = $10;
+    // Low Compare 1 Interrupt Enable
+    LCMP1bm = $20;
+    // Low Compare 2 Interrupt Enable
+    LCMP2bm = $40;
+    // Low Underflow Interrupt Enable
+    LUNFbm = $01;
+  end;
+
+  TTCA = record //16-bit Timer/Counter Type A
+    case byte of
+      0: (SINGLE: TTCA_SINGLE);
+      1: (SPLIT: TTCA_SPLIT);
+  end;
+
+  TTCB = object //16-bit Timer Type B
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control Register B
+    Reserved2: byte;
+    Reserved3: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status
+    DBGCTRL: byte;  //Debug Control
+    TEMP: byte;  //Temporary Value
+    CNT: word;  //Count
+    CCMP: word;  //Compare or Capture
+  const
+    // Cascade two timers
+    CASCADEbm = $20;
+    // TCB_CLKSEL
+    CLKSELmask = $0E;
+    CLKSEL_DIV1 = $00;
+    CLKSEL_DIV2 = $02;
+    CLKSEL_TCA0 = $04;
+    CLKSEL_EVENT = $0E;
+    // Enable
+    ENABLEbm = $01;
+    // Run Standby
+    RUNSTDBYbm = $40;
+    // Synchronize Update
+    SYNCUPDbm = $10;
+    // Asynchronous Enable
+    ASYNCbm = $40;
+    // Pin Output Enable
+    CCMPENbm = $10;
+    // Pin Initial State
+    CCMPINITbm = $20;
+    // TCB_CNTMODE
+    CNTMODEmask = $07;
+    CNTMODE_INT = $00;
+    CNTMODE_TIMEOUT = $01;
+    CNTMODE_CAPT = $02;
+    CNTMODE_FRQ = $03;
+    CNTMODE_PW = $04;
+    CNTMODE_FRQPW = $05;
+    CNTMODE_SINGLE = $06;
+    CNTMODE_PWM8 = $07;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Event Input Enable
+    CAPTEIbm = $01;
+    // Event Edge
+    EDGEbm = $10;
+    // Input Capture Noise Cancellation Filter
+    FILTERbm = $40;
+    // Capture or Timeout
+    CAPTbm = $01;
+    // Overflow
+    OVFbm = $02;
+    // Run
+    RUNbm = $01;
+  end;
+
+  TTWI = object //Two-Wire Interface
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    DBGCTRL: byte;  //Debug Control Register
+    MCTRLA: byte;  //Master Control A
+    MCTRLB: byte;  //Master Control B
+    MSTATUS: byte;  //Master Status
+    MBAUD: byte;  //Master Baud Rate Control
+    MADDR: byte;  //Master Address
+    MDATA: byte;  //Master Data
+    SCTRLA: byte;  //Slave Control A
+    SCTRLB: byte;  //Slave Control B
+    SSTATUS: byte;  //Slave Status
+    SADDR: byte;  //Slave Address
+    SDATA: byte;  //Slave Data
+    SADDRMASK: byte;  //Slave Address Mask
+  const
+    // FM Plus Enable
+    FMPENbm = $02;
+    // TWI_DEFAULT_SDAHOLD
+    DEFAULT_SDAHOLDmask = $0C;
+    DEFAULT_SDAHOLD_OFF = $00;
+    DEFAULT_SDAHOLD_50NS = $04;
+    DEFAULT_SDAHOLD_300NS = $08;
+    DEFAULT_SDAHOLD_500NS = $0C;
+    // TWI_DEFAULT_SDASETUP
+    DEFAULT_SDASETUPmask = $10;
+    DEFAULT_SDASETUP_4CYC = $00;
+    DEFAULT_SDASETUP_8CYC = $10;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Enable TWI Master
+    ENABLEbm = $01;
+    // Quick Command Enable
+    QCENbm = $10;
+    // Read Interrupt Enable
+    RIENbm = $80;
+    // Smart Mode Enable
+    SMENbm = $02;
+    // TWI_TIMEOUT
+    TIMEOUTmask = $0C;
+    TIMEOUT_DISABLED = $00;
+    TIMEOUT_50US = $04;
+    TIMEOUT_100US = $08;
+    TIMEOUT_200US = $0C;
+    // Write Interrupt Enable
+    WIENbm = $40;
+    // TWI_ACKACT
+    ACKACTmask = $04;
+    ACKACT_ACK = $00;
+    ACKACT_NACK = $04;
+    // Flush
+    FLUSHbm = $08;
+    // TWI_MCMD
+    MCMDmask = $03;
+    MCMD_NOACT = $00;
+    MCMD_REPSTART = $01;
+    MCMD_RECVTRANS = $02;
+    MCMD_STOP = $03;
+    // Arbitration Lost
+    ARBLOSTbm = $08;
+    // Bus Error
+    BUSERRbm = $04;
+    // TWI_BUSSTATE
+    BUSSTATEmask = $03;
+    BUSSTATE_UNKNOWN = $00;
+    BUSSTATE_IDLE = $01;
+    BUSSTATE_OWNER = $02;
+    BUSSTATE_BUSY = $03;
+    // Clock Hold
+    CLKHOLDbm = $20;
+    // Read Interrupt Flag
+    RIFbm = $80;
+    // Received Acknowledge
+    RXACKbm = $10;
+    // Write Interrupt Flag
+    WIFbm = $40;
+    // Address Enable
+    ADDRENbm = $01;
+    // Address Mask
+    ADDRMASK0bm = $02;
+    ADDRMASK1bm = $04;
+    ADDRMASK2bm = $08;
+    ADDRMASK3bm = $10;
+    ADDRMASK4bm = $20;
+    ADDRMASK5bm = $40;
+    ADDRMASK6bm = $80;
+    // Address/Stop Interrupt Enable
+    APIENbm = $40;
+    // Data Interrupt Enable
+    DIENbm = $80;
+    // Stop Interrupt Enable
+    PIENbm = $20;
+    // Permissive Mode Enable
+    PMENbm = $04;
+    // TWI_SCMD
+    SCMDmask = $03;
+    SCMD_NOACT = $00;
+    SCMD_COMPTRANS = $02;
+    SCMD_RESPONSE = $03;
+    // TWI_AP
+    APmask = $01;
+    AP_STOP = $00;
+    AP_ADR = $01;
+    // Address/Stop Interrupt Flag
+    APIFbm = $40;
+    // Collision
+    COLLbm = $08;
+    // Data Interrupt Flag
+    DIFbm = $80;
+    // Read/Write Direction
+    DIRbm = $02;
+  end;
+
+  TUSART = object //Universal Synchronous and Asynchronous Receiver and Transmitter
+    RXDATAL: byte;  //Receive Data Low Byte
+    RXDATAH: byte;  //Receive Data High Byte
+    TXDATAL: byte;  //Transmit Data Low Byte
+    TXDATAH: byte;  //Transmit Data High Byte
+    STATUS: byte;  //Status
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    BAUD: word;  //Baud Rate
+    CTRLD: byte;  //Control D
+    DBGCTRL: byte;  //Debug Control
+    EVCTRL: byte;  //Event Control
+    TXPLCTRL: byte;  //IRCOM Transmitter Pulse Length Control
+    RXPLCTRL: byte;  //IRCOM Receiver Pulse Length Control
+  const
+    // Auto-baud Error Interrupt Enable
+    ABEIEbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Loop-back Mode Enable
+    LBMEbm = $08;
+    // USART_RS485
+    RS485mask = $01;
+    RS485_DISABLE = $00;
+    RS485_ENABLE = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Receiver Start Frame Interrupt Enable
+    RXSIEbm = $10;
+    // Transmit Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Multi-processor Communication Mode
+    MPCMbm = $01;
+    // Open Drain Mode Enable
+    ODMEbm = $08;
+    // Reciever enable
+    RXENbm = $80;
+    // USART_RXMODE
+    RXMODEmask = $06;
+    RXMODE_NORMAL = $00;
+    RXMODE_CLK2X = $02;
+    RXMODE_GENAUTO = $04;
+    RXMODE_LINAUTO = $06;
+    // Start Frame Detection Enable
+    SFDENbm = $10;
+    // Transmitter Enable
+    TXENbm = $40;
+    // USART_MSPI_CMODE
+    MSPI_CMODEmask = $C0;
+    MSPI_CMODE_ASYNCHRONOUS = $00;
+    MSPI_CMODE_SYNCHRONOUS = $40;
+    MSPI_CMODE_IRCOM = $80;
+    MSPI_CMODE_MSPI = $C0;
+    // SPI Master Mode, Clock Phase
+    UCPHAbm = $02;
+    // SPI Master Mode, Data Order
+    UDORDbm = $04;
+    // USART_NORMAL_CHSIZE
+    NORMAL_CHSIZEmask = $07;
+    NORMAL_CHSIZE_5BIT = $00;
+    NORMAL_CHSIZE_6BIT = $01;
+    NORMAL_CHSIZE_7BIT = $02;
+    NORMAL_CHSIZE_8BIT = $03;
+    NORMAL_CHSIZE_9BITL = $06;
+    NORMAL_CHSIZE_9BITH = $07;
+    // USART_NORMAL_CMODE
+    NORMAL_CMODEmask = $C0;
+    NORMAL_CMODE_ASYNCHRONOUS = $00;
+    NORMAL_CMODE_SYNCHRONOUS = $40;
+    NORMAL_CMODE_IRCOM = $80;
+    NORMAL_CMODE_MSPI = $C0;
+    // USART_NORMAL_PMODE
+    NORMAL_PMODEmask = $30;
+    NORMAL_PMODE_DISABLED = $00;
+    NORMAL_PMODE_EVEN = $20;
+    NORMAL_PMODE_ODD = $30;
+    // USART_NORMAL_SBMODE
+    NORMAL_SBMODEmask = $08;
+    NORMAL_SBMODE_1BIT = $00;
+    NORMAL_SBMODE_2BIT = $08;
+    // USART_ABW
+    ABWmask = $C0;
+    ABW_WDW0 = $00;
+    ABW_WDW1 = $40;
+    ABW_WDW2 = $80;
+    ABW_WDW3 = $C0;
+    // Autobaud majority voter bypass
+    ABMBPbm = $80;
+    // Debug Run
+    DBGRUNbm = $01;
+    // IrDA Event Input Enable
+    IREIbm = $01;
+    // Buffer Overflow
+    BUFOVFbm = $40;
+    // Receiver Data Register
+    DATA8bm = $01;
+    // Frame Error
+    FERRbm = $04;
+    // Parity Error
+    PERRbm = $02;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // RX Data
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Receiver Pulse Lenght
+    RXPL0bm = $01;
+    RXPL1bm = $02;
+    RXPL2bm = $04;
+    RXPL3bm = $08;
+    RXPL4bm = $10;
+    RXPL5bm = $20;
+    RXPL6bm = $40;
+    // Break Detected Flag
+    BDFbm = $02;
+    // Data Register Empty Flag
+    DREIFbm = $20;
+    // Inconsistent Sync Field Interrupt Flag
+    ISFIFbm = $08;
+    // Receive Start Interrupt
+    RXSIFbm = $10;
+    // Transmit Interrupt Flag
+    TXCIFbm = $40;
+    // Wait For Break
+    WFBbm = $01;
+    // Transmit pulse length
+    TXPL0bm = $01;
+    TXPL1bm = $02;
+    TXPL2bm = $04;
+    TXPL3bm = $08;
+    TXPL4bm = $10;
+    TXPL5bm = $20;
+    TXPL6bm = $40;
+    TXPL7bm = $80;
+  end;
+
+  TUSERROW = object //User Row
+    USERROW0: byte;  //User Row Byte 0
+    USERROW1: byte;  //User Row Byte 1
+    USERROW2: byte;  //User Row Byte 2
+    USERROW3: byte;  //User Row Byte 3
+    USERROW4: byte;  //User Row Byte 4
+    USERROW5: byte;  //User Row Byte 5
+    USERROW6: byte;  //User Row Byte 6
+    USERROW7: byte;  //User Row Byte 7
+    USERROW8: byte;  //User Row Byte 8
+    USERROW9: byte;  //User Row Byte 9
+    USERROW10: byte;  //User Row Byte 10
+    USERROW11: byte;  //User Row Byte 11
+    USERROW12: byte;  //User Row Byte 12
+    USERROW13: byte;  //User Row Byte 13
+    USERROW14: byte;  //User Row Byte 14
+    USERROW15: byte;  //User Row Byte 15
+    USERROW16: byte;  //User Row Byte 16
+    USERROW17: byte;  //User Row Byte 17
+    USERROW18: byte;  //User Row Byte 18
+    USERROW19: byte;  //User Row Byte 19
+    USERROW20: byte;  //User Row Byte 20
+    USERROW21: byte;  //User Row Byte 21
+    USERROW22: byte;  //User Row Byte 22
+    USERROW23: byte;  //User Row Byte 23
+    USERROW24: byte;  //User Row Byte 24
+    USERROW25: byte;  //User Row Byte 25
+    USERROW26: byte;  //User Row Byte 26
+    USERROW27: byte;  //User Row Byte 27
+    USERROW28: byte;  //User Row Byte 28
+    USERROW29: byte;  //User Row Byte 29
+    USERROW30: byte;  //User Row Byte 30
+    USERROW31: byte;  //User Row Byte 31
+    USERROW32: byte;  //User Row Byte 32
+    USERROW33: byte;  //User Row Byte 33
+    USERROW34: byte;  //User Row Byte 34
+    USERROW35: byte;  //User Row Byte 35
+    USERROW36: byte;  //User Row Byte 36
+    USERROW37: byte;  //User Row Byte 37
+    USERROW38: byte;  //User Row Byte 38
+    USERROW39: byte;  //User Row Byte 39
+    USERROW40: byte;  //User Row Byte 40
+    USERROW41: byte;  //User Row Byte 41
+    USERROW42: byte;  //User Row Byte 42
+    USERROW43: byte;  //User Row Byte 43
+    USERROW44: byte;  //User Row Byte 44
+    USERROW45: byte;  //User Row Byte 45
+    USERROW46: byte;  //User Row Byte 46
+    USERROW47: byte;  //User Row Byte 47
+    USERROW48: byte;  //User Row Byte 48
+    USERROW49: byte;  //User Row Byte 49
+    USERROW50: byte;  //User Row Byte 50
+    USERROW51: byte;  //User Row Byte 51
+    USERROW52: byte;  //User Row Byte 52
+    USERROW53: byte;  //User Row Byte 53
+    USERROW54: byte;  //User Row Byte 54
+    USERROW55: byte;  //User Row Byte 55
+    USERROW56: byte;  //User Row Byte 56
+    USERROW57: byte;  //User Row Byte 57
+    USERROW58: byte;  //User Row Byte 58
+    USERROW59: byte;  //User Row Byte 59
+    USERROW60: byte;  //User Row Byte 60
+    USERROW61: byte;  //User Row Byte 61
+    USERROW62: byte;  //User Row Byte 62
+    USERROW63: byte;  //User Row Byte 63
+  end;
+
+  TVPORT = object //Virtual Ports
+    DIR: byte;  //Data Direction
+    OUT_: byte;  //Output Value
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+  end;
+
+  TVREF = object //Voltage reference
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+  const
+    // VREF_AC0REFSEL
+    AC0REFSELmask = $07;
+    AC0REFSEL_1V024 = $00;
+    AC0REFSEL_2V048 = $01;
+    AC0REFSEL_2V5 = $02;
+    AC0REFSEL_4V096 = $03;
+    AC0REFSEL_AVDD = $07;
+    // AC0 DACREF reference enable
+    AC0REFENbm = $01;
+    // ADC0 reference enable
+    ADC0REFENbm = $02;
+    // NVM reference enable
+    NVMREFENbm = $04;
+  end;
+
+  TWDT = object //Watch-Dog Timer
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+  const
+    // WDT_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // WDT_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+    // Lock enable
+    LOCKbm = $80;
+    // Syncronization busy
+    SYNCBUSYbm = $01;
+  end;
+
+
+const
+ Pin0idx = 0;  Pin0bm = 1;
+ Pin1idx = 1;  Pin1bm = 2;
+ Pin2idx = 2;  Pin2bm = 4;
+ Pin3idx = 3;  Pin3bm = 8;
+ Pin4idx = 4;  Pin4bm = 16;
+ Pin5idx = 5;  Pin5bm = 32;
+ Pin6idx = 6;  Pin6bm = 64;
+ Pin7idx = 7;  Pin7bm = 128;
+
+var
+  VPORTA: TVPORT absolute $0000;
+  VPORTB: TVPORT absolute $0004;
+  VPORTC: TVPORT absolute $0008;
+  GPIO: TGPIO absolute $001C;
+  CPU: TCPU absolute $0030;
+  RSTCTRL: TRSTCTRL absolute $0040;
+  SLPCTRL: TSLPCTRL absolute $0050;
+  CLKCTRL: TCLKCTRL absolute $0060;
+  BOD: TBOD absolute $0080;
+  VREF: TVREF absolute $00A0;
+  NVMBIST: TNVMBIST absolute $00C0;
+  WDT: TWDT absolute $0100;
+  CPUINT: TCPUINT absolute $0110;
+  CRCSCAN: TCRCSCAN absolute $0120;
+  RTC: TRTC absolute $0140;
+  EVSYS: TEVSYS absolute $0180;
+  CCL: TCCL absolute $01C0;
+  PORTA: TPORT absolute $0400;
+  PORTB: TPORT absolute $0420;
+  PORTC: TPORT absolute $0440;
+  PORTMUX: TPORTMUX absolute $05E0;
+  ADC0: TADC absolute $0600;
+  AC0: TAC absolute $0680;
+  USART0: TUSART absolute $0800;
+  USART1: TUSART absolute $0820;
+  TWI0: TTWI absolute $08A0;
+  SPI0: TSPI absolute $08C0;
+  TCA0: TTCA absolute $0A00;
+  TCB0: TTCB absolute $0A80;
+  TCB1: TTCB absolute $0A90;
+  SYSCFG: TSYSCFG absolute $0F00;
+  NVMCTRL: TNVMCTRL absolute $1000;
+  SIGROW: TSIGROW absolute $1100;
+  FUSE: TFUSE absolute $1280;
+  LOCKBIT: TLOCKBIT absolute $128A;
+  USERROW: TUSERROW absolute $1300;
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure CRCSCAN_NMI_ISR; external name 'CRCSCAN_NMI_ISR'; // Interrupt 1 
+procedure BOD_VLM_ISR; external name 'BOD_VLM_ISR'; // Interrupt 2 
+procedure RTC_CNT_ISR; external name 'RTC_CNT_ISR'; // Interrupt 3 
+procedure RTC_PIT_ISR; external name 'RTC_PIT_ISR'; // Interrupt 4 
+procedure CCL_CCL_ISR; external name 'CCL_CCL_ISR'; // Interrupt 5 
+procedure PORTA_PORT_ISR; external name 'PORTA_PORT_ISR'; // Interrupt 6 
+procedure PORTB_PORT_ISR; external name 'PORTB_PORT_ISR'; // Interrupt 7 
+procedure TCA0_LUNF_ISR; external name 'TCA0_LUNF_ISR'; // Interrupt 8 
+//procedure TCA0_OVF_ISR; external name 'TCA0_OVF_ISR'; // Interrupt 8 
+procedure TCA0_HUNF_ISR; external name 'TCA0_HUNF_ISR'; // Interrupt 9 
+procedure TCA0_LCMP0_ISR; external name 'TCA0_LCMP0_ISR'; // Interrupt 10 
+//procedure TCA0_CMP0_ISR; external name 'TCA0_CMP0_ISR'; // Interrupt 10 
+procedure TCA0_CMP1_ISR; external name 'TCA0_CMP1_ISR'; // Interrupt 11 
+//procedure TCA0_LCMP1_ISR; external name 'TCA0_LCMP1_ISR'; // Interrupt 11 
+procedure TCA0_CMP2_ISR; external name 'TCA0_CMP2_ISR'; // Interrupt 12 
+//procedure TCA0_LCMP2_ISR; external name 'TCA0_LCMP2_ISR'; // Interrupt 12 
+procedure TCB0_INT_ISR; external name 'TCB0_INT_ISR'; // Interrupt 13 
+procedure TWI0_TWIS_ISR; external name 'TWI0_TWIS_ISR'; // Interrupt 14 
+procedure TWI0_TWIM_ISR; external name 'TWI0_TWIM_ISR'; // Interrupt 15 
+procedure SPI0_INT_ISR; external name 'SPI0_INT_ISR'; // Interrupt 16 
+procedure USART0_RXC_ISR; external name 'USART0_RXC_ISR'; // Interrupt 17 
+procedure USART0_DRE_ISR; external name 'USART0_DRE_ISR'; // Interrupt 18 
+procedure USART0_TXC_ISR; external name 'USART0_TXC_ISR'; // Interrupt 19 
+procedure AC0_AC_ISR; external name 'AC0_AC_ISR'; // Interrupt 20 
+procedure ADC0_ERROR_ISR; external name 'ADC0_ERROR_ISR'; // Interrupt 21 
+procedure ADC0_RESRDY_ISR; external name 'ADC0_RESRDY_ISR'; // Interrupt 22 
+procedure ADC0_SAMPRDY_ISR; external name 'ADC0_SAMPRDY_ISR'; // Interrupt 23 
+procedure PORTC_PORT_ISR; external name 'PORTC_PORT_ISR'; // Interrupt 24 
+procedure TCB1_INT_ISR; external name 'TCB1_INT_ISR'; // Interrupt 25 
+procedure USART1_RXC_ISR; external name 'USART1_RXC_ISR'; // Interrupt 26 
+procedure USART1_DRE_ISR; external name 'USART1_DRE_ISR'; // Interrupt 27 
+procedure USART1_TXC_ISR; external name 'USART1_TXC_ISR'; // Interrupt 28 
+procedure NVMCTRL_EE_ISR; external name 'NVMCTRL_EE_ISR'; // Interrupt 29 
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp CRCSCAN_NMI_ISR
+  jmp BOD_VLM_ISR
+  jmp RTC_CNT_ISR
+  jmp RTC_PIT_ISR
+  jmp CCL_CCL_ISR
+  jmp PORTA_PORT_ISR
+  jmp PORTB_PORT_ISR
+  jmp TCA0_LUNF_ISR
+//  jmp TCA0_OVF_ISR
+  jmp TCA0_HUNF_ISR
+  jmp TCA0_LCMP0_ISR
+//  jmp TCA0_CMP0_ISR
+  jmp TCA0_CMP1_ISR
+//  jmp TCA0_LCMP1_ISR
+  jmp TCA0_CMP2_ISR
+//  jmp TCA0_LCMP2_ISR
+  jmp TCB0_INT_ISR
+  jmp TWI0_TWIS_ISR
+  jmp TWI0_TWIM_ISR
+  jmp SPI0_INT_ISR
+  jmp USART0_RXC_ISR
+  jmp USART0_DRE_ISR
+  jmp USART0_TXC_ISR
+  jmp AC0_AC_ISR
+  jmp ADC0_ERROR_ISR
+  jmp ADC0_RESRDY_ISR
+  jmp ADC0_SAMPRDY_ISR
+  jmp PORTC_PORT_ISR
+  jmp TCB1_INT_ISR
+  jmp USART1_RXC_ISR
+  jmp USART1_DRE_ISR
+  jmp USART1_TXC_ISR
+  jmp NVMCTRL_EE_ISR
+
+  {$i start.inc}
+
+  .weak CRCSCAN_NMI_ISR
+  .weak BOD_VLM_ISR
+  .weak RTC_CNT_ISR
+  .weak RTC_PIT_ISR
+  .weak CCL_CCL_ISR
+  .weak PORTA_PORT_ISR
+  .weak PORTB_PORT_ISR
+  .weak TCA0_LUNF_ISR
+//  .weak TCA0_OVF_ISR
+  .weak TCA0_HUNF_ISR
+  .weak TCA0_LCMP0_ISR
+//  .weak TCA0_CMP0_ISR
+  .weak TCA0_CMP1_ISR
+//  .weak TCA0_LCMP1_ISR
+  .weak TCA0_CMP2_ISR
+//  .weak TCA0_LCMP2_ISR
+  .weak TCB0_INT_ISR
+  .weak TWI0_TWIS_ISR
+  .weak TWI0_TWIM_ISR
+  .weak SPI0_INT_ISR
+  .weak USART0_RXC_ISR
+  .weak USART0_DRE_ISR
+  .weak USART0_TXC_ISR
+  .weak AC0_AC_ISR
+  .weak ADC0_ERROR_ISR
+  .weak ADC0_RESRDY_ISR
+  .weak ADC0_SAMPRDY_ISR
+  .weak PORTC_PORT_ISR
+  .weak TCB1_INT_ISR
+  .weak USART1_RXC_ISR
+  .weak USART1_DRE_ISR
+  .weak USART1_TXC_ISR
+  .weak NVMCTRL_EE_ISR
+
+  .set CRCSCAN_NMI_ISR, Default_IRQ_handler
+  .set BOD_VLM_ISR, Default_IRQ_handler
+  .set RTC_CNT_ISR, Default_IRQ_handler
+  .set RTC_PIT_ISR, Default_IRQ_handler
+  .set CCL_CCL_ISR, Default_IRQ_handler
+  .set PORTA_PORT_ISR, Default_IRQ_handler
+  .set PORTB_PORT_ISR, Default_IRQ_handler
+  .set TCA0_LUNF_ISR, Default_IRQ_handler
+//  .set TCA0_OVF_ISR, Default_IRQ_handler
+  .set TCA0_HUNF_ISR, Default_IRQ_handler
+  .set TCA0_LCMP0_ISR, Default_IRQ_handler
+//  .set TCA0_CMP0_ISR, Default_IRQ_handler
+  .set TCA0_CMP1_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP1_ISR, Default_IRQ_handler
+  .set TCA0_CMP2_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP2_ISR, Default_IRQ_handler
+  .set TCB0_INT_ISR, Default_IRQ_handler
+  .set TWI0_TWIS_ISR, Default_IRQ_handler
+  .set TWI0_TWIM_ISR, Default_IRQ_handler
+  .set SPI0_INT_ISR, Default_IRQ_handler
+  .set USART0_RXC_ISR, Default_IRQ_handler
+  .set USART0_DRE_ISR, Default_IRQ_handler
+  .set USART0_TXC_ISR, Default_IRQ_handler
+  .set AC0_AC_ISR, Default_IRQ_handler
+  .set ADC0_ERROR_ISR, Default_IRQ_handler
+  .set ADC0_RESRDY_ISR, Default_IRQ_handler
+  .set ADC0_SAMPRDY_ISR, Default_IRQ_handler
+  .set PORTC_PORT_ISR, Default_IRQ_handler
+  .set TCB1_INT_ISR, Default_IRQ_handler
+  .set USART1_RXC_ISR, Default_IRQ_handler
+  .set USART1_DRE_ISR, Default_IRQ_handler
+  .set USART1_TXC_ISR, Default_IRQ_handler
+  .set NVMCTRL_EE_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/attiny1626.pp

@@ -0,0 +1,2522 @@
+unit ATtiny1626;
+
+{$goto on}
+interface
+
+type
+  TAC = object //Analog Comparator
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    MUXCTRLA: byte;  //Mux Control A
+    Reserved3: byte;
+    DACREF: byte;  //Referance scale control
+    Reserved5: byte;
+    INTCTRL: byte;  //Interrupt Control
+    STATUS: byte;  //Status
+  const
+    // Enable
+    ENABLEbm = $01;
+    // AC_HYSMODE
+    HYSMODEmask = $06;
+    HYSMODE_OFF = $00;
+    HYSMODE_10mV = $02;
+    HYSMODE_25mV = $04;
+    HYSMODE_50mV = $06;
+    // AC_INTMODE
+    INTMODEmask = $30;
+    INTMODE_BOTHEDGE = $00;
+    INTMODE_NEGEDGE = $20;
+    INTMODE_POSEDGE = $30;
+    // AC_LPMODE
+    LPMODEmask = $08;
+    LPMODE_DIS = $00;
+    LPMODE_EN = $08;
+    // Output Buffer Enable
+    OUTENbm = $40;
+    // Run in Standby Mode
+    RUNSTDBYbm = $80;
+    // DAC voltage reference
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Analog Comparator 0 Interrupt Enable
+    CMPbm = $01;
+    // Invert AC Output
+    INVERTbm = $80;
+    // AC_MUXNEG
+    MUXNEGmask = $03;
+    MUXNEG_PIN0 = $00;
+    MUXNEG_PIN1 = $01;
+    MUXNEG_PIN2 = $02;
+    MUXNEG_DACREF = $03;
+    // AC_MUXPOS
+    MUXPOSmask = $18;
+    MUXPOS_PIN0 = $00;
+    MUXPOS_PIN1 = $08;
+    MUXPOS_PIN2 = $10;
+    MUXPOS_PIN3 = $18;
+    // Analog Comparator State
+    STATEbm = $10;
+  end;
+
+  TADC = object //Analog to Digital Converter
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status register
+    DBGCTRL: byte;  //Debug Control
+    CTRLE: byte;  //Control E
+    CTRLF: byte;  //Control F
+    COMMAND: byte;  //Command register
+    PGACTRL: byte;  //PGA Control
+    MUXPOS: byte;  //Positive mux input
+    MUXNEG: byte;  //Negative mux input
+    Reserved14: byte;
+    Reserved15: byte;
+    RESULT: dword;  //Result
+    SAMPLE: word;  //Sample
+    Reserved22: byte;
+    Reserved23: byte;
+    TEMP0: byte;  //Temporary Data 0
+    TEMP1: byte;  //Temporary Data 1
+    TEMP2: byte;  //Temporary Data 2
+    Reserved27: byte;
+    WINLT: word;  //Window Low Threshold
+    WINHT: word;  //Window High Threshold
+  const
+    // Differential mode
+    DIFFbm = $80;
+    // ADC_MODE
+    MODEmask = $70;
+    MODE_SINGLE_8BIT = $00;
+    MODE_SINGLE_12BIT = $10;
+    MODE_SERIES = $20;
+    MODE_SERIES_TRUNCATION = $30;
+    MODE_BURST = $40;
+    MODE_BURST_TRUNCATION = $50;
+    // ADC_START
+    STARTmask = $07;
+    START_STOP = $00;
+    START_IMMEDIATE = $01;
+    START_MUXPOS_WRITE = $02;
+    START_MUXNEG_WRITE = $03;
+    START_EVENT_TRIGGER = $04;
+    // ADC Enable
+    ENABLEbm = $01;
+    // ADC Low latency mode
+    LOWLATbm = $20;
+    // Run standby mode
+    RUNSTDBYbm = $80;
+    // ADC_PRESC
+    PRESCmask = $0F;
+    PRESC_DIV2 = $00;
+    PRESC_DIV4 = $01;
+    PRESC_DIV6 = $02;
+    PRESC_DIV8 = $03;
+    PRESC_DIV10 = $04;
+    PRESC_DIV12 = $05;
+    PRESC_DIV14 = $06;
+    PRESC_DIV16 = $07;
+    PRESC_DIV20 = $08;
+    PRESC_DIV24 = $09;
+    PRESC_DIV28 = $0A;
+    PRESC_DIV32 = $0B;
+    PRESC_DIV40 = $0C;
+    PRESC_DIV48 = $0D;
+    PRESC_DIV56 = $0E;
+    PRESC_DIV64 = $0F;
+    // ADC_REFSEL
+    REFSELmask = $07;
+    REFSEL_VDD = $00;
+    REFSEL_VREFA = $02;
+    REFSEL_1024MV = $04;
+    REFSEL_2048MV = $05;
+    REFSEL_2500MV = $06;
+    REFSEL_4096MV = $07;
+    // Reference Selection
+    TIMEBASE0bm = $08;
+    TIMEBASE1bm = $10;
+    TIMEBASE2bm = $20;
+    TIMEBASE3bm = $40;
+    TIMEBASE4bm = $80;
+    // ADC_WINCM
+    WINCMmask = $07;
+    WINCM_NONE = $00;
+    WINCM_BELOW = $01;
+    WINCM_ABOVE = $02;
+    WINCM_INSIDE = $03;
+    WINCM_OUTSIDE = $04;
+    // ADC_WINSRC
+    WINSRCmask = $08;
+    WINSRC_RESULT = $00;
+    WINSRC_SAMPLE = $08;
+    // Sampling time
+    SAMPDUR0bm = $01;
+    SAMPDUR1bm = $02;
+    SAMPDUR2bm = $04;
+    SAMPDUR3bm = $08;
+    SAMPDUR4bm = $10;
+    SAMPDUR5bm = $20;
+    SAMPDUR6bm = $40;
+    SAMPDUR7bm = $80;
+    // Free running mode
+    FREERUNbm = $20;
+    // Left adjust
+    LEFTADJbm = $10;
+    // ADC_SAMPNUM
+    SAMPNUMmask = $0F;
+    SAMPNUM_NONE = $00;
+    SAMPNUM_ACC2 = $01;
+    SAMPNUM_ACC4 = $02;
+    SAMPNUM_ACC8 = $03;
+    SAMPNUM_ACC16 = $04;
+    SAMPNUM_ACC32 = $05;
+    SAMPNUM_ACC64 = $06;
+    SAMPNUM_ACC128 = $07;
+    SAMPNUM_ACC256 = $08;
+    SAMPNUM_ACC512 = $09;
+    SAMPNUM_ACC1024 = $0A;
+    // Debug run
+    DBGRUNbm = $01;
+    // Result Overwritten Interrupt Enable
+    RESOVRbm = $08;
+    // Result Ready Interrupt Enable
+    RESRDYbm = $01;
+    // Sample Overwritten Interrupt Enable
+    SAMPOVRbm = $10;
+    // Sample Ready Interrupt Enable
+    SAMPRDYbm = $02;
+    // Trigger Overrun Interrupt Enable
+    TRIGOVRbm = $20;
+    // Window Comparator Interrupt Enable
+    WCMPbm = $04;
+    // ADC_MUXNEG
+    MUXNEGmask = $3F;
+    MUXNEG_AIN1 = $01;
+    MUXNEG_AIN2 = $02;
+    MUXNEG_AIN3 = $03;
+    MUXNEG_AIN4 = $04;
+    MUXNEG_AIN5 = $05;
+    MUXNEG_AIN6 = $06;
+    MUXNEG_AIN7 = $07;
+    MUXNEG_GND = $30;
+    MUXNEG_VDDDIV10 = $31;
+    MUXNEG_DAC = $33;
+    // ADC_VIA
+    VIAmask = $C0;
+    VIA_ADC = $00;
+    VIA_PGA = $40;
+    // ADC_MUXPOS
+    MUXPOSmask = $3F;
+    MUXPOS_AIN1 = $01;
+    MUXPOS_AIN2 = $02;
+    MUXPOS_AIN3 = $03;
+    MUXPOS_AIN4 = $04;
+    MUXPOS_AIN5 = $05;
+    MUXPOS_AIN6 = $06;
+    MUXPOS_AIN7 = $07;
+    MUXPOS_AIN8 = $08;
+    MUXPOS_AIN9 = $09;
+    MUXPOS_AIN10 = $0A;
+    MUXPOS_AIN11 = $0B;
+    MUXPOS_AIN12 = $0C;
+    MUXPOS_AIN13 = $0D;
+    MUXPOS_AIN14 = $0E;
+    MUXPOS_AIN15 = $0F;
+    MUXPOS_GND = $30;
+    MUXPOS_VDDDIV10 = $31;
+    MUXPOS_TEMPSENSE = $32;
+    MUXPOS_DAC = $33;
+    // ADC_ADCPGASAMPDUR
+    ADCPGASAMPDURmask = $06;
+    ADCPGASAMPDUR_6CLK = $00;
+    ADCPGASAMPDUR_15CLK = $02;
+    ADCPGASAMPDUR_20CLK = $04;
+    ADCPGASAMPDUR_32CLK = $06;
+    // ADC_GAIN
+    GAINmask = $E0;
+    GAIN_1X = $00;
+    GAIN_2X = $20;
+    GAIN_4X = $40;
+    GAIN_8X = $60;
+    GAIN_16X = $80;
+    // ADC_PGABIASSEL
+    PGABIASSELmask = $18;
+    PGABIASSEL_1X = $00;
+    PGABIASSEL_3_4X = $08;
+    PGABIASSEL_1_2X = $10;
+    PGABIASSEL_1_4X = $18;
+    // PGA Enable
+    PGAENbm = $01;
+    // ADC Busy
+    ADCBUSYbm = $01;
+    // Temporary
+    TEMP0bm = $01;
+    TEMP1bm = $02;
+    TEMP2bm = $04;
+    TEMP3bm = $08;
+    TEMP4bm = $10;
+    TEMP5bm = $20;
+    TEMP6bm = $40;
+    TEMP7bm = $80;
+  end;
+
+  TBOD = object //Bod interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    VLMCTRLA: byte;  //Voltage level monitor Control
+    INTCTRL: byte;  //Voltage level monitor interrupt Control
+    INTFLAGS: byte;  //Voltage level monitor interrupt Flags
+    STATUS: byte;  //Voltage level monitor status
+  const
+    // BOD_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // BOD_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // BOD_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // BOD_LVL
+    LVLmask = $07;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $02;
+    LVL_BODLEVEL7 = $07;
+    // BOD_VLMCFG
+    VLMCFGmask = $06;
+    VLMCFG_BELOW = $00;
+    VLMCFG_ABOVE = $02;
+    VLMCFG_CROSS = $04;
+    // voltage level monitor interrrupt enable
+    VLMIEbm = $01;
+    // Voltage level monitor interrupt flag
+    VLMIFbm = $01;
+    // Voltage level monitor status
+    VLMSbm = $01;
+    // BOD_VLMLVL
+    VLMLVLmask = $03;
+    VLMLVL_5ABOVE = $00;
+    VLMLVL_15ABOVE = $01;
+    VLMLVL_25ABOVE = $02;
+  end;
+
+  TCCL = object //Configurable Custom Logic
+    CTRLA: byte;  //Control Register A
+    SEQCTRL0: byte;  //Sequential Control 0
+    SEQCTRL1: byte;  //Sequential Control 1
+    Reserved3: byte;
+    Reserved4: byte;
+    INTCTRL0: byte;  //Interrupt Control 0
+    Reserved6: byte;
+    INTFLAGS: byte;  //Interrupt Flags
+    LUT0CTRLA: byte;  //LUT Control 0 A
+    LUT0CTRLB: byte;  //LUT Control 0 B
+    LUT0CTRLC: byte;  //LUT Control 0 C
+    TRUTH0: byte;  //Truth 0
+    LUT1CTRLA: byte;  //LUT Control 1 A
+    LUT1CTRLB: byte;  //LUT Control 1 B
+    LUT1CTRLC: byte;  //LUT Control 1 C
+    TRUTH1: byte;  //Truth 1
+    LUT2CTRLA: byte;  //LUT Control 2 A
+    LUT2CTRLB: byte;  //LUT Control 2 B
+    LUT2CTRLC: byte;  //LUT Control 2 C
+    TRUTH2: byte;  //Truth 2
+    LUT3CTRLA: byte;  //LUT Control 3 A
+    LUT3CTRLB: byte;  //LUT Control 3 B
+    LUT3CTRLC: byte;  //LUT Control 3 C
+    TRUTH3: byte;  //Truth 3
+  const
+    // Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $40;
+    // CCL_INTMODE0
+    INTMODE0mask = $03;
+    INTMODE0_INTDISABLE = $00;
+    INTMODE0_RISING = $01;
+    INTMODE0_FALLING = $02;
+    INTMODE0_BOTH = $03;
+    // CCL_INTMODE1
+    INTMODE1mask = $0C;
+    INTMODE1_INTDISABLE = $00;
+    INTMODE1_RISING = $04;
+    INTMODE1_FALLING = $08;
+    INTMODE1_BOTH = $0C;
+    // CCL_INTMODE2
+    INTMODE2mask = $30;
+    INTMODE2_INTDISABLE = $00;
+    INTMODE2_RISING = $10;
+    INTMODE2_FALLING = $20;
+    INTMODE2_BOTH = $30;
+    // CCL_INTMODE3
+    INTMODE3mask = $C0;
+    INTMODE3_INTDISABLE = $00;
+    INTMODE3_RISING = $40;
+    INTMODE3_FALLING = $80;
+    INTMODE3_BOTH = $C0;
+    // Interrupt Flags
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    // CCL_CLKSRC
+    CLKSRCmask = $0E;
+    CLKSRC_CLKPER = $00;
+    CLKSRC_IN2 = $02;
+    CLKSRC_OSC20M = $08;
+    CLKSRC_OSCULP32K = $0A;
+    CLKSRC_OSCULP1K = $0C;
+    // CCL_EDGEDET
+    EDGEDETmask = $80;
+    EDGEDET_DIS = $00;
+    EDGEDET_EN = $80;
+    // CCL_FILTSEL
+    FILTSELmask = $30;
+    FILTSEL_DISABLE = $00;
+    FILTSEL_SYNCH = $10;
+    FILTSEL_FILTER = $20;
+    // Output Enable
+    OUTENbm = $40;
+    // CCL_INSEL0
+    INSEL0mask = $0F;
+    INSEL0_MASK = $00;
+    INSEL0_FEEDBACK = $01;
+    INSEL0_LINK = $02;
+    INSEL0_EVENTA = $03;
+    INSEL0_EVENTB = $04;
+    INSEL0_IO = $05;
+    INSEL0_AC0 = $06;
+    INSEL0_USART0 = $08;
+    INSEL0_SPI0 = $09;
+    INSEL0_TCA0 = $0A;
+    INSEL0_TCB0 = $0C;
+    // CCL_INSEL1
+    INSEL1mask = $F0;
+    INSEL1_MASK = $00;
+    INSEL1_FEEDBACK = $10;
+    INSEL1_LINK = $20;
+    INSEL1_EVENTA = $30;
+    INSEL1_EVENTB = $40;
+    INSEL1_IO = $50;
+    INSEL1_AC0 = $60;
+    INSEL1_USART1 = $80;
+    INSEL1_SPI0 = $90;
+    INSEL1_TCA0 = $A0;
+    INSEL1_TCB1 = $C0;
+    // CCL_INSEL2
+    INSEL2mask = $0F;
+    INSEL2_MASK = $00;
+    INSEL2_FEEDBACK = $01;
+    INSEL2_LINK = $02;
+    INSEL2_EVENTA = $03;
+    INSEL2_EVENTB = $04;
+    INSEL2_IO = $05;
+    INSEL2_AC0 = $06;
+    INSEL2_SPI0 = $09;
+    INSEL2_TCA0 = $0A;
+    // CCL_SEQSEL0
+    SEQSEL0mask = $07;
+    SEQSEL0_DISABLE = $00;
+    SEQSEL0_DFF = $01;
+    SEQSEL0_JK = $02;
+    SEQSEL0_LATCH = $03;
+    SEQSEL0_RS = $04;
+    // CCL_SEQSEL1
+    SEQSEL1mask = $07;
+    SEQSEL1_DISABLE = $00;
+    SEQSEL1_DFF = $01;
+    SEQSEL1_JK = $02;
+    SEQSEL1_LATCH = $03;
+    SEQSEL1_RS = $04;
+  end;
+
+  TCLKCTRL = object //Clock controller
+    MCLKCTRLA: byte;  //MCLK Control A
+    MCLKCTRLB: byte;  //MCLK Control B
+    MCLKLOCK: byte;  //MCLK Lock
+    MCLKSTATUS: byte;  //MCLK Status
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    OSC20MCTRLA: byte;  //OSC20M Control A
+    OSC20MCALIBA: byte;  //OSC20M Calibration A
+    OSC20MCALIBB: byte;  //OSC20M Calibration B
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSC32KCTRLA: byte;  //OSC32K Control A
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    XOSC32KCTRLA: byte;  //XOSC32K Control A
+  const
+    // System clock out
+    CLKOUTbm = $80;
+    // CLKCTRL_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_OSC20M = $00;
+    CLKSEL_OSCULP32K = $01;
+    CLKSEL_XOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // CLKCTRL_PDIV
+    PDIVmask = $1E;
+    PDIV_2X = $00;
+    PDIV_4X = $02;
+    PDIV_8X = $04;
+    PDIV_16X = $06;
+    PDIV_32X = $08;
+    PDIV_64X = $0A;
+    PDIV_6X = $10;
+    PDIV_10X = $12;
+    PDIV_12X = $14;
+    PDIV_24X = $16;
+    PDIV_48X = $18;
+    // Prescaler enable
+    PENbm = $01;
+    // lock ebable
+    LOCKENbm = $01;
+    // External Clock status
+    EXTSbm = $80;
+    // 20MHz oscillator status
+    OSC20MSbm = $10;
+    // 32KHz oscillator status
+    OSC32KSbm = $20;
+    // System Oscillator changing
+    SOSCbm = $01;
+    // 32.768 kHz Crystal Oscillator status
+    XOSC32KSbm = $40;
+    // Calibration
+    CAL20M0bm = $01;
+    CAL20M1bm = $02;
+    CAL20M2bm = $04;
+    CAL20M3bm = $08;
+    CAL20M4bm = $10;
+    CAL20M5bm = $20;
+    CAL20M6bm = $40;
+    // Lock
+    LOCKbm = $80;
+    // Oscillator temperature coefficient
+    TEMPCAL20M0bm = $01;
+    TEMPCAL20M1bm = $02;
+    TEMPCAL20M2bm = $04;
+    TEMPCAL20M3bm = $08;
+    // Run standby
+    RUNSTDBYbm = $02;
+    // CLKCTRL_CSUT
+    CSUTmask = $30;
+    CSUT_1K = $00;
+    CSUT_16K = $10;
+    CSUT_32K = $20;
+    CSUT_64K = $30;
+    // Enable
+    ENABLEbm = $01;
+    // Select
+    SELbm = $04;
+  end;
+
+  TCPU = object //CPU
+    Reserved0: byte;
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    CCP: byte;  //Configuration Change Protection
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    RAMPZ: byte;  //Extended Z-pointer Register
+    Reserved12: byte;
+    SPL: byte;  //Stack Pointer Low
+    SPH: byte;  //Stack Pointer High
+    SREG: byte;  //Status Register
+  const
+    // CPU_CCP
+    CCPmask = $FF;
+    CCP_SPM = $9D;
+    CCP_IOREG = $D8;
+    // Carry Flag
+    Cbm = $01;
+    // Half Carry Flag
+    Hbm = $20;
+    // Global Interrupt Enable Flag
+    Ibm = $80;
+    // Negative Flag
+    Nbm = $04;
+    // N Exclusive Or V Flag
+    Sbm = $10;
+    // Transfer Bit
+    Tbm = $40;
+    // Two's Complement Overflow Flag
+    Vbm = $08;
+    // Zero Flag
+    Zbm = $02;
+  end;
+
+  TCPUINT = object //Interrupt Controller
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    LVL0PRI: byte;  //Interrupt Level 0 Priority
+    LVL1VEC: byte;  //Interrupt Level 1 Priority Vector
+  const
+    // Compact Vector Table
+    CVTbm = $20;
+    // Interrupt Vector Select
+    IVSELbm = $40;
+    // Round-robin Scheduling Enable
+    LVL0RRbm = $01;
+    // Interrupt Level Priority
+    LVL0PRI0bm = $01;
+    LVL0PRI1bm = $02;
+    LVL0PRI2bm = $04;
+    LVL0PRI3bm = $08;
+    LVL0PRI4bm = $10;
+    LVL0PRI5bm = $20;
+    LVL0PRI6bm = $40;
+    LVL0PRI7bm = $80;
+    // Interrupt Vector with High Priority
+    LVL1VEC0bm = $01;
+    LVL1VEC1bm = $02;
+    LVL1VEC2bm = $04;
+    LVL1VEC3bm = $08;
+    LVL1VEC4bm = $10;
+    LVL1VEC5bm = $20;
+    LVL1VEC6bm = $40;
+    LVL1VEC7bm = $80;
+    // Level 0 Interrupt Executing
+    LVL0EXbm = $01;
+    // Level 1 Interrupt Executing
+    LVL1EXbm = $02;
+    // Non-maskable Interrupt Executing
+    NMIEXbm = $80;
+  end;
+
+  TCRCSCAN = object //CRCSCAN
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+  const
+    // Enable CRC scan
+    ENABLEbm = $01;
+    // Enable NMI Trigger
+    NMIENbm = $02;
+    // Reset CRC scan
+    RESETbm = $80;
+    // CRCSCAN_SRC
+    SRCmask = $03;
+    SRC_FLASH = $00;
+    SRC_APPLICATION = $01;
+    SRC_BOOT = $02;
+    // CRC Busy
+    BUSYbm = $01;
+    // CRC Ok
+    OKbm = $02;
+  end;
+
+  TEVSYS = object //Event System
+    SWEVENTA: byte;  //Software Event A
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    CHANNEL0: byte;  //Multiplexer Channel 0
+    CHANNEL1: byte;  //Multiplexer Channel 1
+    CHANNEL2: byte;  //Multiplexer Channel 2
+    CHANNEL3: byte;  //Multiplexer Channel 3
+    CHANNEL4: byte;  //Multiplexer Channel 4
+    CHANNEL5: byte;  //Multiplexer Channel 5
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    USERCCLLUT0A: byte;  //User CCL LUT0 Event A
+    USERCCLLUT0B: byte;  //User CCL LUT0 Event B
+    USERCCLLUT1A: byte;  //User CCL LUT1 Event A
+    USERCCLLUT1B: byte;  //User CCL LUT1 Event B
+    USERCCLLUT2A: byte;  //User CCL LUT2 Event A
+    USERCCLLUT2B: byte;  //User CCL LUT2 Event B
+    USERCCLLUT3A: byte;  //User CCL LUT3 Event A
+    USERCCLLUT3B: byte;  //User CCL LUT3 Event B
+    USERADC0START: byte;  //User ADC0
+    USEREVSYSEVOUTA: byte;  //User EVOUT Port A
+    USEREVSYSEVOUTB: byte;  //User EVOUT Port B
+    USEREVSYSEVOUTC: byte;  //User EVOUT Port C
+    USERUSART0IRDA: byte;  //User USART0
+    USERUSART1IRDA: byte;  //User USART1
+    USERTCA0CNTA: byte;  //User TCA0 count event
+    USERTCA0CNTB: byte;  //User TCA0 Restart event
+    USERTCB0CAPT: byte;  //User TCB0 Event in A
+    USERTCB0COUNT: byte;  //User TCB0 Event in B
+    USERTCB1CAPT: byte;  //User TCB1 Event in A
+    USERTCB1COUNT: byte;  //User TCB1 Event in B
+  const
+    // EVSYS_CHANNEL0
+    CHANNEL0mask = $FF;
+    CHANNEL0_OFF = $00;
+    CHANNEL0_UPDI = $01;
+    CHANNEL0_RTC_OVF = $06;
+    CHANNEL0_RTC_CMP = $07;
+    CHANNEL0_RTC_PIT_DIV8192 = $08;
+    CHANNEL0_RTC_PIT_DIV4096 = $09;
+    CHANNEL0_RTC_PIT_DIV2048 = $0A;
+    CHANNEL0_RTC_PIT_DIV1024 = $0B;
+    CHANNEL0_CCL_LUT0 = $10;
+    CHANNEL0_CCL_LUT1 = $11;
+    CHANNEL0_CCL_LUT2 = $12;
+    CHANNEL0_CCL_LUT3 = $13;
+    CHANNEL0_AC0_OUT = $20;
+    CHANNEL0_ADC0_RES = $24;
+    CHANNEL0_ADC0_SAMP = $25;
+    CHANNEL0_ADC0_WCMP = $26;
+    CHANNEL0_PORTA_PIN0 = $40;
+    CHANNEL0_PORTA_PIN1 = $41;
+    CHANNEL0_PORTA_PIN2 = $42;
+    CHANNEL0_PORTA_PIN3 = $43;
+    CHANNEL0_PORTA_PIN4 = $44;
+    CHANNEL0_PORTA_PIN5 = $45;
+    CHANNEL0_PORTA_PIN6 = $46;
+    CHANNEL0_PORTA_PIN7 = $47;
+    CHANNEL0_PORTB_PIN0 = $48;
+    CHANNEL0_PORTB_PIN1 = $49;
+    CHANNEL0_PORTB_PIN2 = $4A;
+    CHANNEL0_PORTB_PIN3 = $4B;
+    CHANNEL0_PORTB_PIN4 = $4C;
+    CHANNEL0_PORTB_PIN5 = $4D;
+    CHANNEL0_PORTB_PIN6 = $4E;
+    CHANNEL0_PORTB_PIN7 = $4F;
+    CHANNEL0_USART0_XCK = $60;
+    CHANNEL0_USART1_XCK = $61;
+    CHANNEL0_SPI0_SCK = $68;
+    CHANNEL0_TCA0_OVF_LUNF = $80;
+    CHANNEL0_TCA0_HUNF = $81;
+    CHANNEL0_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL0_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL0_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL0_TCB0_CAPT = $A0;
+    CHANNEL0_TCB0_OVF = $A1;
+    CHANNEL0_TCB1_CAPT = $A2;
+    CHANNEL0_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL1
+    CHANNEL1mask = $FF;
+    CHANNEL1_OFF = $00;
+    CHANNEL1_UPDI = $01;
+    CHANNEL1_RTC_OVF = $06;
+    CHANNEL1_RTC_CMP = $07;
+    CHANNEL1_RTC_PIT_DIV512 = $08;
+    CHANNEL1_RTC_PIT_DIV256 = $09;
+    CHANNEL1_RTC_PIT_DIV128 = $0A;
+    CHANNEL1_RTC_PIT_DIV64 = $0B;
+    CHANNEL1_CCL_LUT0 = $10;
+    CHANNEL1_CCL_LUT1 = $11;
+    CHANNEL1_CCL_LUT2 = $12;
+    CHANNEL1_CCL_LUT3 = $13;
+    CHANNEL1_AC0_OUT = $20;
+    CHANNEL1_ADC0_RES = $24;
+    CHANNEL1_ADC0_SAMP = $25;
+    CHANNEL1_ADC0_WCMP = $26;
+    CHANNEL1_PORTA_PIN0 = $40;
+    CHANNEL1_PORTA_PIN1 = $41;
+    CHANNEL1_PORTA_PIN2 = $42;
+    CHANNEL1_PORTA_PIN3 = $43;
+    CHANNEL1_PORTA_PIN4 = $44;
+    CHANNEL1_PORTA_PIN5 = $45;
+    CHANNEL1_PORTA_PIN6 = $46;
+    CHANNEL1_PORTA_PIN7 = $47;
+    CHANNEL1_PORTB_PIN0 = $48;
+    CHANNEL1_PORTB_PIN1 = $49;
+    CHANNEL1_PORTB_PIN2 = $4A;
+    CHANNEL1_PORTB_PIN3 = $4B;
+    CHANNEL1_PORTB_PIN4 = $4C;
+    CHANNEL1_PORTB_PIN5 = $4D;
+    CHANNEL1_PORTB_PIN6 = $4E;
+    CHANNEL1_PORTB_PIN7 = $4F;
+    CHANNEL1_USART0_XCK = $60;
+    CHANNEL1_USART1_XCK = $61;
+    CHANNEL1_SPI0_SCK = $68;
+    CHANNEL1_TCA0_OVF_LUNF = $80;
+    CHANNEL1_TCA0_HUNF = $81;
+    CHANNEL1_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL1_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL1_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL1_TCB0_CAPT = $A0;
+    CHANNEL1_TCB0_OVF = $A1;
+    CHANNEL1_TCB1_CAPT = $A2;
+    CHANNEL1_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL2
+    CHANNEL2mask = $FF;
+    CHANNEL2_OFF = $00;
+    CHANNEL2_UPDI = $01;
+    CHANNEL2_RTC_OVF = $06;
+    CHANNEL2_RTC_CMP = $07;
+    CHANNEL2_RTC_PIT_DIV8192 = $08;
+    CHANNEL2_RTC_PIT_DIV4096 = $09;
+    CHANNEL2_RTC_PIT_DIV2048 = $0A;
+    CHANNEL2_RTC_PIT_DIV1024 = $0B;
+    CHANNEL2_CCL_LUT0 = $10;
+    CHANNEL2_CCL_LUT1 = $11;
+    CHANNEL2_CCL_LUT2 = $12;
+    CHANNEL2_CCL_LUT3 = $13;
+    CHANNEL2_AC0_OUT = $20;
+    CHANNEL2_ADC0_RES = $24;
+    CHANNEL2_ADC0_SAMP = $25;
+    CHANNEL2_ADC0_WCMP = $26;
+    CHANNEL2_PORTC_PIN0 = $40;
+    CHANNEL2_PORTC_PIN1 = $41;
+    CHANNEL2_PORTC_PIN2 = $42;
+    CHANNEL2_PORTC_PIN3 = $43;
+    CHANNEL2_PORTC_PIN4 = $44;
+    CHANNEL2_PORTC_PIN5 = $45;
+    CHANNEL2_PORTC_PIN6 = $46;
+    CHANNEL2_PORTC_PIN7 = $47;
+    CHANNEL2_PORTA_PIN0 = $48;
+    CHANNEL2_PORTA_PIN1 = $49;
+    CHANNEL2_PORTA_PIN2 = $4A;
+    CHANNEL2_PORTA_PIN3 = $4B;
+    CHANNEL2_PORTA_PIN4 = $4C;
+    CHANNEL2_PORTA_PIN5 = $4D;
+    CHANNEL2_PORTA_PIN6 = $4E;
+    CHANNEL2_PORTA_PIN7 = $4F;
+    CHANNEL2_USART0_XCK = $60;
+    CHANNEL2_USART1_XCK = $61;
+    CHANNEL2_SPI0_SCK = $68;
+    CHANNEL2_TCA0_OVF_LUNF = $80;
+    CHANNEL2_TCA0_HUNF = $81;
+    CHANNEL2_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL2_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL2_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL2_TCB0_CAPT = $A0;
+    CHANNEL2_TCB0_OVF = $A1;
+    CHANNEL2_TCB1_CAPT = $A2;
+    CHANNEL2_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL3
+    CHANNEL3mask = $FF;
+    CHANNEL3_OFF = $00;
+    CHANNEL3_UPDI = $01;
+    CHANNEL3_RTC_OVF = $06;
+    CHANNEL3_RTC_CMP = $07;
+    CHANNEL3_RTC_PIT_DIV512 = $08;
+    CHANNEL3_RTC_PIT_DIV256 = $09;
+    CHANNEL3_RTC_PIT_DIV128 = $0A;
+    CHANNEL3_RTC_PIT_DIV64 = $0B;
+    CHANNEL3_CCL_LUT0 = $10;
+    CHANNEL3_CCL_LUT1 = $11;
+    CHANNEL3_CCL_LUT2 = $12;
+    CHANNEL3_CCL_LUT3 = $13;
+    CHANNEL3_AC0_OUT = $20;
+    CHANNEL3_ADC0_RES = $24;
+    CHANNEL3_ADC0_SAMP = $25;
+    CHANNEL3_ADC0_WCMP = $26;
+    CHANNEL3_PORTC_PIN0 = $40;
+    CHANNEL3_PORTC_PIN1 = $41;
+    CHANNEL3_PORTC_PIN2 = $42;
+    CHANNEL3_PORTC_PIN3 = $43;
+    CHANNEL3_PORTC_PIN4 = $44;
+    CHANNEL3_PORTC_PIN5 = $45;
+    CHANNEL3_PORTC_PIN6 = $46;
+    CHANNEL3_PORTC_PIN7 = $47;
+    CHANNEL3_PORTA_PIN0 = $48;
+    CHANNEL3_PORTA_PIN1 = $49;
+    CHANNEL3_PORTA_PIN2 = $4A;
+    CHANNEL3_PORTA_PIN3 = $4B;
+    CHANNEL3_PORTA_PIN4 = $4C;
+    CHANNEL3_PORTA_PIN5 = $4D;
+    CHANNEL3_PORTA_PIN6 = $4E;
+    CHANNEL3_PORTA_PIN7 = $4F;
+    CHANNEL3_USART0_XCK = $60;
+    CHANNEL3_USART1_XCK = $61;
+    CHANNEL3_SPI0_SCK = $68;
+    CHANNEL3_TCA0_OVF_LUNF = $80;
+    CHANNEL3_TCA0_HUNF = $81;
+    CHANNEL3_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL3_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL3_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL3_TCB0_CAPT = $A0;
+    CHANNEL3_TCB0_OVF = $A1;
+    CHANNEL3_TCB1_CAPT = $A2;
+    CHANNEL3_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL4
+    CHANNEL4mask = $FF;
+    CHANNEL4_OFF = $00;
+    CHANNEL4_UPDI = $01;
+    CHANNEL4_RTC_OVF = $06;
+    CHANNEL4_RTC_CMP = $07;
+    CHANNEL4_RTC_PIT_DIV8192 = $08;
+    CHANNEL4_RTC_PIT_DIV4096 = $09;
+    CHANNEL4_RTC_PIT_DIV2048 = $0A;
+    CHANNEL4_RTC_PIT_DIV1024 = $0B;
+    CHANNEL4_CCL_LUT0 = $10;
+    CHANNEL4_CCL_LUT1 = $11;
+    CHANNEL4_CCL_LUT2 = $12;
+    CHANNEL4_CCL_LUT3 = $13;
+    CHANNEL4_AC0_OUT = $20;
+    CHANNEL4_ADC0_RES = $24;
+    CHANNEL4_ADC0_SAMP = $25;
+    CHANNEL4_ADC0_WCMP = $26;
+    CHANNEL4_PORTB_PIN0 = $40;
+    CHANNEL4_PORTB_PIN1 = $41;
+    CHANNEL4_PORTB_PIN2 = $42;
+    CHANNEL4_PORTB_PIN3 = $43;
+    CHANNEL4_PORTB_PIN4 = $44;
+    CHANNEL4_PORTB_PIN5 = $45;
+    CHANNEL4_PORTB_PIN6 = $46;
+    CHANNEL4_PORTB_PIN7 = $47;
+    CHANNEL4_PORTC_PIN0 = $48;
+    CHANNEL4_PORTC_PIN1 = $49;
+    CHANNEL4_PORTC_PIN2 = $4A;
+    CHANNEL4_PORTC_PIN3 = $4B;
+    CHANNEL4_PORTC_PIN4 = $4C;
+    CHANNEL4_PORTC_PIN5 = $4D;
+    CHANNEL4_PORTC_PIN6 = $4E;
+    CHANNEL4_PORTC_PIN7 = $4F;
+    CHANNEL4_USART0_XCK = $60;
+    CHANNEL4_USART1_XCK = $61;
+    CHANNEL4_SPI0_SCK = $68;
+    CHANNEL4_TCA0_OVF_LUNF = $80;
+    CHANNEL4_TCA0_HUNF = $81;
+    CHANNEL4_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL4_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL4_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL4_TCB0_CAPT = $A0;
+    CHANNEL4_TCB0_OVF = $A1;
+    CHANNEL4_TCB1_CAPT = $A2;
+    CHANNEL4_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL5
+    CHANNEL5mask = $FF;
+    CHANNEL5_OFF = $00;
+    CHANNEL5_UPDI = $01;
+    CHANNEL5_RTC_OVF = $06;
+    CHANNEL5_RTC_CMP = $07;
+    CHANNEL5_RTC_PIT_DIV512 = $08;
+    CHANNEL5_RTC_PIT_DIV256 = $09;
+    CHANNEL5_RTC_PIT_DIV128 = $0A;
+    CHANNEL5_RTC_PIT_DIV64 = $0B;
+    CHANNEL5_CCL_LUT0 = $10;
+    CHANNEL5_CCL_LUT1 = $11;
+    CHANNEL5_CCL_LUT2 = $12;
+    CHANNEL5_CCL_LUT3 = $13;
+    CHANNEL5_AC0_OUT = $20;
+    CHANNEL5_ADC0_RES = $24;
+    CHANNEL5_ADC0_SAMP = $25;
+    CHANNEL5_ADC0_WCMP = $26;
+    CHANNEL5_PORTB_PIN0 = $40;
+    CHANNEL5_PORTB_PIN1 = $41;
+    CHANNEL5_PORTB_PIN2 = $42;
+    CHANNEL5_PORTB_PIN3 = $43;
+    CHANNEL5_PORTB_PIN4 = $44;
+    CHANNEL5_PORTB_PIN5 = $45;
+    CHANNEL5_PORTB_PIN6 = $46;
+    CHANNEL5_PORTB_PIN7 = $47;
+    CHANNEL5_PORTC_PIN0 = $48;
+    CHANNEL5_PORTC_PIN1 = $49;
+    CHANNEL5_PORTC_PIN2 = $4A;
+    CHANNEL5_PORTC_PIN3 = $4B;
+    CHANNEL5_PORTC_PIN4 = $4C;
+    CHANNEL5_PORTC_PIN5 = $4D;
+    CHANNEL5_PORTC_PIN6 = $4E;
+    CHANNEL5_PORTC_PIN7 = $4F;
+    CHANNEL5_USART0_XCK = $60;
+    CHANNEL5_USART1_XCK = $61;
+    CHANNEL5_SPI0_SCK = $68;
+    CHANNEL5_TCA0_OVF_LUNF = $80;
+    CHANNEL5_TCA0_HUNF = $81;
+    CHANNEL5_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL5_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL5_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL5_TCB0_CAPT = $A0;
+    CHANNEL5_TCB0_OVF = $A1;
+    CHANNEL5_TCB1_CAPT = $A2;
+    CHANNEL5_TCB1_OVF = $A3;
+    // EVSYS_SWEVENTA
+    SWEVENTAmask = $FF;
+    SWEVENTA_CH0 = $01;
+    SWEVENTA_CH1 = $02;
+    SWEVENTA_CH2 = $04;
+    SWEVENTA_CH3 = $08;
+    SWEVENTA_CH4 = $10;
+    SWEVENTA_CH5 = $20;
+    // EVSYS_USER
+    USERmask = $FF;
+    USER_OFF = $00;
+    USER_CHANNEL0 = $01;
+    USER_CHANNEL1 = $02;
+    USER_CHANNEL2 = $03;
+    USER_CHANNEL3 = $04;
+    USER_CHANNEL4 = $05;
+    USER_CHANNEL5 = $06;
+  end;
+
+  TFUSE = object //Fuses
+    WDTCFG: byte;  //Watchdog Configuration
+    BODCFG: byte;  //BOD Configuration
+    OSCCFG: byte;  //Oscillator Configuration
+    Reserved3: byte;
+    Reserved4: byte;
+    SYSCFG0: byte;  //System Configuration 0
+    SYSCFG1: byte;  //System Configuration 1
+    APPEND: byte;  //Application Code Section End
+    BOOTEND: byte;  //Boot Section End
+  const
+    // FUSE_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // FUSE_LVL
+    LVLmask = $E0;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $40;
+    LVL_BODLEVEL7 = $E0;
+    // FUSE_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // FUSE_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // FUSE_FREQSEL
+    FREQSELmask = $03;
+    FREQSEL_16MHZ = $01;
+    FREQSEL_20MHZ = $02;
+    // Oscillator Lock
+    OSCLOCKbm = $80;
+    // FUSE_CRCSRC
+    CRCSRCmask = $C0;
+    CRCSRC_FLASH = $00;
+    CRCSRC_BOOT = $40;
+    CRCSRC_BOOTAPP = $80;
+    CRCSRC_NOCRC = $C0;
+    // EEPROM Save
+    EESAVEbm = $01;
+    // FUSE_RSTPINCFG
+    RSTPINCFGmask = $0C;
+    RSTPINCFG_GPIO = $00;
+    RSTPINCFG_UPDI = $04;
+    RSTPINCFG_RST = $08;
+    RSTPINCFG_PDIRST = $0C;
+    // FUSE_SUT
+    SUTmask = $07;
+    SUT_0MS = $00;
+    SUT_1MS = $01;
+    SUT_2MS = $02;
+    SUT_4MS = $03;
+    SUT_8MS = $04;
+    SUT_16MS = $05;
+    SUT_32MS = $06;
+    SUT_64MS = $07;
+    // FUSE_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // FUSE_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+  end;
+
+  TGPIO = object //General Purpose IO
+    GPIOR0: byte;  //General Purpose IO Register 0
+    GPIOR1: byte;  //General Purpose IO Register 1
+    GPIOR2: byte;  //General Purpose IO Register 2
+    GPIOR3: byte;  //General Purpose IO Register 3
+  end;
+
+  TLOCKBIT = object //Lockbit
+    LOCKBIT: byte;  //Lock Bits
+  const
+    // LOCKBIT_LB
+    LBmask = $FF;
+    LB_RWLOCK = $3A;
+    LB_NOLOCK = $C5;
+  end;
+
+  TNVMBIST = object //BIST in the NVMCTRL module
+    CTRLA: byte;  //Control A
+    ADDRPAT: byte;  //Address pattern
+    DATAPAT: byte;  //Data pattern
+    STATUS: byte;  //Status
+    CNT: word;
+    END_: dword;
+  const
+    // NVMBIST_AMODE
+    AMODEmask = $70;
+    AMODE_NORMAL = $00;
+    AMODE_COMPLEMENT = $40;
+    // NVMBIST_XMODE
+    XMODEmask = $03;
+    XMODE_STATIC = $00;
+    XMODE_CARRY = $01;
+    XMODE_INC = $02;
+    XMODE_DEC = $03;
+    // NVMBIST_YMODE
+    YMODEmask = $0C;
+    YMODE_STATIC = $00;
+    YMODE_CARRY = $04;
+    YMODE_INC = $08;
+    YMODE_DEC = $0C;
+    // Faults counter
+    CNT0bm = $01;
+    CNT1bm = $02;
+    CNT2bm = $04;
+    CNT3bm = $08;
+    CNT4bm = $10;
+    CNT5bm = $20;
+    CNT6bm = $40;
+    CNT7bm = $80;
+    // NVMBIST_CMD
+    CMDmask = $07;
+    CMD_NOCMD = $00;
+    CMD_START = $01;
+    CMD_RESTART = $02;
+    CMD_BREAK = $03;
+    // Stop at fault
+    SAFbm = $08;
+    // NVMBIST_PATTERN
+    PATTERNmask = $03;
+    PATTERN_ZEROES = $00;
+    PATTERN_CHECK = $01;
+    PATTERN_INVCHECK = $02;
+    PATTERN_ONES = $03;
+    // 
+    END0bm = $01;
+    END1bm = $02;
+    END2bm = $04;
+    END3bm = $08;
+    END4bm = $10;
+    END5bm = $20;
+    END6bm = $40;
+    END7bm = $80;
+    // NVMBIST_STATE
+    STATEmask = $0F;
+    STATE_IDLE = $00;
+    STATE_BREAK = $01;
+    STATE_FAILED0 = $04;
+    STATE_FAILED1 = $05;
+    STATE_FAILED2 = $06;
+    STATE_SUCCESS = $07;
+    STATE_START0 = $08;
+    STATE_START1 = $09;
+    STATE_RESTART0 = $0A;
+    STATE_RESTART1 = $0B;
+    STATE_RUNNING = $0C;
+    STATE_FINISH0 = $0E;
+    STATE_FINISH1 = $0F;
+  end;
+
+  TNVMCTRL = object //Non-volatile Memory Controller
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved5: byte;
+    DATA: word;  //Data
+    ADDR: word;  //Address
+  const
+    // NVMCTRL_CMD
+    CMDmask = $07;
+    CMD_NONE = $00;
+    CMD_PAGEWRITE = $01;
+    CMD_PAGEERASE = $02;
+    CMD_PAGEERASEWRITE = $03;
+    CMD_PAGEBUFCLR = $04;
+    CMD_CHIPERASE = $05;
+    CMD_EEERASE = $06;
+    CMD_FUSEWRITE = $07;
+    // Application code write protect
+    APCWPbm = $01;
+    // Boot Lock
+    BOOTLOCKbm = $02;
+    // EEPROM Ready
+    EEREADYbm = $01;
+    // EEPROM busy
+    EEBUSYbm = $02;
+    // Flash busy
+    FBUSYbm = $01;
+    // Write error
+    WRERRORbm = $04;
+  end;
+
+  TPORT = object //I/O Ports
+    DIR: byte;  //Data Direction
+    DIRSET: byte;  //Data Direction Set
+    DIRCLR: byte;  //Data Direction Clear
+    DIRTGL: byte;  //Data Direction Toggle
+    OUT_: byte;  //Output Value
+    OUTSET: byte;  //Output Value Set
+    OUTCLR: byte;  //Output Value Clear
+    OUTTGL: byte;  //Output Value Toggle
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+    PORTCTRL: byte;  //Port Control
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    PIN0CTRL: byte;  //Pin 0 Control
+    PIN1CTRL: byte;  //Pin 1 Control
+    PIN2CTRL: byte;  //Pin 2 Control
+    PIN3CTRL: byte;  //Pin 3 Control
+    PIN4CTRL: byte;  //Pin 4 Control
+    PIN5CTRL: byte;  //Pin 5 Control
+    PIN6CTRL: byte;  //Pin 6 Control
+    PIN7CTRL: byte;  //Pin 7 Control
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+    // Inverted I/O Enable
+    INVENbm = $80;
+    // PORT_ISC
+    ISCmask = $07;
+    ISC_INTDISABLE = $00;
+    ISC_BOTHEDGES = $01;
+    ISC_RISING = $02;
+    ISC_FALLING = $03;
+    ISC_INPUT_DISABLE = $04;
+    ISC_LEVEL = $05;
+    // Pullup enable
+    PULLUPENbm = $08;
+    // Slew Rate Limit Enable
+    SRLbm = $01;
+  end;
+
+  TPORTMUX = object //Port Multiplexer
+    EVSYSROUTEA: byte;  //Port Multiplexer EVSYS
+    CCLROUTEA: byte;  //Port Multiplexer CCL
+    USARTROUTEA: byte;  //Port Multiplexer USART register A
+    SPIROUTEA: byte;  //Port Multiplexer TWI and SPI
+    TCAROUTEA: byte;  //Port Multiplexer TCA
+    TCBROUTEA: byte;  //Port Multiplexer TCB
+  const
+    // CCL LUT0
+    LUT0bm = $01;
+    // CCL LUT1
+    LUT1bm = $02;
+    // CCL LUT2
+    LUT2bm = $04;
+    // CCL LUT3
+    LUT3bm = $08;
+    // Event Output 0
+    EVOUT0bm = $01;
+    // Event Output 1
+    EVOUT1bm = $02;
+    // Event Output 2
+    EVOUT2bm = $04;
+    // Event Output 3
+    EVOUT3bm = $08;
+    // Event Output 4
+    EVOUT4bm = $10;
+    // Event Output 5
+    EVOUT5bm = $20;
+    // PORTMUX_SPI0
+    SPI0mask = $03;
+    SPI0_DEFAULT = $00;
+    SPI0_ALT1 = $01;
+    SPI0_ALT2 = $02;
+    SPI0_NONE = $03;
+    // PORTMUX_TWI0
+    TWI0mask = $30;
+    TWI0_DEFAULT = $00;
+    TWI0_ALT1 = $10;
+    TWI0_ALT2 = $20;
+    TWI0_NONE = $30;
+    // PORTMUX_TCA0
+    TCA0mask = $07;
+    TCA0_PORTA = $00;
+    TCA0_PORTB = $01;
+    TCA0_PORTC = $02;
+    TCA0_PORTD = $03;
+    TCA0_PORTE = $04;
+    TCA0_PORTF = $05;
+    // Port Multiplexer TCB0
+    TCB0bm = $01;
+    // Port Multiplexer TCB1
+    TCB1bm = $02;
+    // Port Multiplexer TCB2
+    TCB2bm = $04;
+    // Port Multiplexer TCB3
+    TCB3bm = $08;
+    // PORTMUX_USART0
+    USART0mask = $03;
+    USART0_DEFAULT = $00;
+    USART0_ALT1 = $01;
+    USART0_NONE = $03;
+    // PORTMUX_USART1
+    USART1mask = $0C;
+    USART1_DEFAULT = $00;
+    USART1_ALT1 = $04;
+    USART1_NONE = $0C;
+  end;
+
+  TRSTCTRL = object //Reset controller
+    RSTFR: byte;  //Reset Flags
+    SWRR: byte;  //Software Reset
+  const
+    // Brown out detector Reset flag
+    BORFbm = $02;
+    // External Reset flag
+    EXTRFbm = $04;
+    // Power on Reset flag
+    PORFbm = $01;
+    // Software Reset flag
+    SWRFbm = $10;
+    // UPDI Reset flag
+    UPDIRFbm = $20;
+    // Watch dog Reset flag
+    WDRFbm = $08;
+    // Software reset enable
+    SWREbm = $01;
+  end;
+
+  TRTC = object //Real-Time Counter
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    TEMP: byte;  //Temporary
+    DBGCTRL: byte;  //Debug control
+    CALIB: byte;  //Calibration
+    CLKSEL: byte;  //RTC Clock
+    CNT: word;  //Counter
+    PER: word;  //Period
+    CMP: word;  //Compare
+    Reserved14: byte;
+    Reserved15: byte;
+    PITCTRLA: byte;  //PIT Control A
+    PITSTATUS: byte;  //PIT Status
+    PITINTCTRL: byte;  //PIT Interrupt Control
+    PITINTFLAGS: byte;  //PIT Interrupt Flags
+    Reserved20: byte;
+    PITDBGCTRL: byte;  //PIT Debug control
+  const
+    // Error Correction Value
+    ERROR0bm = $01;
+    ERROR1bm = $02;
+    ERROR2bm = $04;
+    ERROR3bm = $08;
+    ERROR4bm = $10;
+    ERROR5bm = $20;
+    ERROR6bm = $40;
+    // Error Correction Sign Bit
+    SIGNbm = $80;
+    // RTC_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_INT32K = $00;
+    CLKSEL_INT1K = $01;
+    CLKSEL_TOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // Correction enable
+    CORRENbm = $04;
+    // RTC_PRESCALER
+    PRESCALERmask = $78;
+    PRESCALER_DIV1 = $00;
+    PRESCALER_DIV2 = $08;
+    PRESCALER_DIV4 = $10;
+    PRESCALER_DIV8 = $18;
+    PRESCALER_DIV16 = $20;
+    PRESCALER_DIV32 = $28;
+    PRESCALER_DIV64 = $30;
+    PRESCALER_DIV128 = $38;
+    PRESCALER_DIV256 = $40;
+    PRESCALER_DIV512 = $48;
+    PRESCALER_DIV1024 = $50;
+    PRESCALER_DIV2048 = $58;
+    PRESCALER_DIV4096 = $60;
+    PRESCALER_DIV8192 = $68;
+    PRESCALER_DIV16384 = $70;
+    PRESCALER_DIV32768 = $78;
+    // Enable
+    RTCENbm = $01;
+    // Run In Standby
+    RUNSTDBYbm = $80;
+    // Run in debug
+    DBGRUNbm = $01;
+    // Compare Match Interrupt enable
+    CMPbm = $02;
+    // Overflow Interrupt enable
+    OVFbm = $01;
+    // RTC_PERIOD
+    PERIODmask = $78;
+    PERIOD_OFF = $00;
+    PERIOD_CYC4 = $08;
+    PERIOD_CYC8 = $10;
+    PERIOD_CYC16 = $18;
+    PERIOD_CYC32 = $20;
+    PERIOD_CYC64 = $28;
+    PERIOD_CYC128 = $30;
+    PERIOD_CYC256 = $38;
+    PERIOD_CYC512 = $40;
+    PERIOD_CYC1024 = $48;
+    PERIOD_CYC2048 = $50;
+    PERIOD_CYC4096 = $58;
+    PERIOD_CYC8192 = $60;
+    PERIOD_CYC16384 = $68;
+    PERIOD_CYC32768 = $70;
+    // Enable
+    PITENbm = $01;
+    // Periodic Interrupt
+    PIbm = $01;
+    // CTRLA Synchronization Busy Flag
+    CTRLBUSYbm = $01;
+    // Comparator Synchronization Busy Flag
+    CMPBUSYbm = $08;
+    // Count Synchronization Busy Flag
+    CNTBUSYbm = $02;
+    // CTRLA Synchronization Busy Flag
+    CTRLABUSYbm = $01;
+    // Period Synchronization Busy Flag
+    PERBUSYbm = $04;
+  end;
+
+  TSIGROW = object //Signature row
+    DEVICEID0: byte;  //Device ID Byte 0
+    DEVICEID1: byte;  //Device ID Byte 1
+    DEVICEID2: byte;  //Device ID Byte 2
+    SERNUM0: byte;  //Serial Number Byte 0
+    SERNUM1: byte;  //Serial Number Byte 1
+    SERNUM2: byte;  //Serial Number Byte 2
+    SERNUM3: byte;  //Serial Number Byte 3
+    SERNUM4: byte;  //Serial Number Byte 4
+    SERNUM5: byte;  //Serial Number Byte 5
+    SERNUM6: byte;  //Serial Number Byte 6
+    SERNUM7: byte;  //Serial Number Byte 7
+    SERNUM8: byte;  //Serial Number Byte 8
+    SERNUM9: byte;  //Serial Number Byte 9
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    OSCCAL32K: byte;  //Oscillator Calibration for 32kHz ULP
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSCCAL16M0: byte;  //Oscillator Calibration 16 MHz Byte 0
+    OSCCAL16M1: byte;  //Oscillator Calibration 16 MHz Byte 1
+    OSCCAL20M0: byte;  //Oscillator Calibration 20 MHz Byte 0
+    OSCCAL20M1: byte;  //Oscillator Calibration 20 MHz Byte 1
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    TEMPSENSE0: byte;  //Temperature Sensor Calibration Byte 0
+    TEMPSENSE1: byte;  //Temperature Sensor Calibration Byte 1
+    OSC16ERR3V: byte;  //OSC16 error at 3V
+    OSC16ERR5V: byte;  //OSC16 error at 5V
+    OSC20ERR3V: byte;  //OSC20 error at 3V
+    OSC20ERR5V: byte;  //OSC20 error at 5V
+    Reserved38: byte;
+    Reserved39: byte;
+    Reserved40: byte;
+    Reserved41: byte;
+    Reserved42: byte;
+    Reserved43: byte;
+    Reserved44: byte;
+    Reserved45: byte;
+    Reserved46: byte;
+    CHECKSUM1: byte;  //CRC Checksum Byte 1
+  end;
+
+  TSLPCTRL = object //Sleep Controller
+    CTRLA: byte;  //Control
+  const
+    // Sleep enable
+    SENbm = $01;
+    // SLPCTRL_SMODE
+    SMODEmask = $06;
+    SMODE_IDLE = $00;
+    SMODE_STDBY = $02;
+    SMODE_PDOWN = $04;
+  end;
+
+  TSPI = object //Serial Peripheral Interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    DATA: byte;  //Data
+  const
+    // Enable Double Speed
+    CLK2Xbm = $10;
+    // Data Order Setting
+    DORDbm = $40;
+    // Enable Module
+    ENABLEbm = $01;
+    // Master Operation Enable
+    MASTERbm = $20;
+    // SPI_PRESC
+    PRESCmask = $06;
+    PRESC_DIV4 = $00;
+    PRESC_DIV16 = $02;
+    PRESC_DIV64 = $04;
+    PRESC_DIV128 = $06;
+    // Buffer Mode Enable
+    BUFENbm = $80;
+    // Buffer Mode Wait for Receive
+    BUFWRbm = $40;
+    // SPI_MODE
+    MODEmask = $03;
+    MODE_0 = $00;
+    MODE_1 = $01;
+    MODE_2 = $02;
+    MODE_3 = $03;
+    // Slave Select Disable
+    SSDbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Interrupt Enable
+    IEbm = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Slave Select Trigger Interrupt Enable
+    SSIEbm = $10;
+    // Transfer Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Buffer Overflow
+    BUFOVFbm = $01;
+    // Data Register Empty Interrupt Flag
+    DREIFbm = $20;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // Slave Select Trigger Interrupt Flag
+    SSIFbm = $10;
+    // Transfer Complete Interrupt Flag
+    TXCIFbm = $40;
+    // Interrupt Flag
+    IFbm = $80;
+    // Write Collision
+    WRCOLbm = $40;
+  end;
+
+  TSYSCFG = object //System Configuration Registers
+    Reserved0: byte;
+    REVID: byte;  //Revision ID
+    EXTBRK: byte;  //External Break
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OCDM: byte;  //OCD Message Register
+    OCDMS: byte;  //OCD Message Status
+  const
+    // External break enable
+    ENEXTBRKbm = $01;
+    // OCD Message Read
+    OCDMRbm = $01;
+  end;
+
+  TTCA_SINGLE = object //16-bit Timer/Counter Type A - Single Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    CTRLFCLR: byte;  //Control F Clear
+    CTRLFSET: byte;  //Control F Set
+    Reserved8: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    TEMP: byte;  //Temporary data for 16-bit Access
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    CNT: word;  //Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    PER: word;  //Period
+    CMP0: word;  //Compare 0
+    CMP1: word;  //Compare 1
+    CMP2: word;  //Compare 2
+    Reserved46: byte;
+    Reserved47: byte;
+    Reserved48: byte;
+    Reserved49: byte;
+    Reserved50: byte;
+    Reserved51: byte;
+    Reserved52: byte;
+    Reserved53: byte;
+    PERBUF: word;  //Period Buffer
+    CMP0BUF: word;  //Compare 0 Buffer
+    CMP1BUF: word;  //Compare 1 Buffer
+    CMP2BUF: word;  //Compare 2 Buffer
+  const
+    // TCA_SINGLE_CLKSEL
+    SINGLE_CLKSELmask = $0E;
+    SINGLE_CLKSEL_DIV1 = $00;
+    SINGLE_CLKSEL_DIV2 = $02;
+    SINGLE_CLKSEL_DIV4 = $04;
+    SINGLE_CLKSEL_DIV8 = $06;
+    SINGLE_CLKSEL_DIV16 = $08;
+    SINGLE_CLKSEL_DIV64 = $0A;
+    SINGLE_CLKSEL_DIV256 = $0C;
+    SINGLE_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // Auto Lock Update
+    ALUPDbm = $08;
+    // Compare 0 Enable
+    CMP0ENbm = $10;
+    // Compare 1 Enable
+    CMP1ENbm = $20;
+    // Compare 2 Enable
+    CMP2ENbm = $40;
+    // TCA_SINGLE_WGMODE
+    SINGLE_WGMODEmask = $07;
+    SINGLE_WGMODE_NORMAL = $00;
+    SINGLE_WGMODE_FRQ = $01;
+    SINGLE_WGMODE_SINGLESLOPE = $03;
+    SINGLE_WGMODE_DSTOP = $05;
+    SINGLE_WGMODE_DSBOTH = $06;
+    SINGLE_WGMODE_DSBOTTOM = $07;
+    // Compare 0 Waveform Output Value
+    CMP0OVbm = $01;
+    // Compare 1 Waveform Output Value
+    CMP1OVbm = $02;
+    // Compare 2 Waveform Output Value
+    CMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SINGLE_CMD
+    SINGLE_CMDmask = $0C;
+    SINGLE_CMD_NONE = $00;
+    SINGLE_CMD_UPDATE = $04;
+    SINGLE_CMD_RESTART = $08;
+    SINGLE_CMD_RESET = $0C;
+    // Direction
+    DIRbm = $01;
+    // Lock Update
+    LUPDbm = $02;
+    // Compare 0 Buffer Valid
+    CMP0BVbm = $02;
+    // Compare 1 Buffer Valid
+    CMP1BVbm = $04;
+    // Compare 2 Buffer Valid
+    CMP2BVbm = $08;
+    // Period Buffer Valid
+    PERBVbm = $01;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Count on Event Input A
+    CNTAEIbm = $01;
+    // Count on Event Input B
+    CNTBEIbm = $10;
+    // TCA_SINGLE_EVACTA
+    SINGLE_EVACTAmask = $0E;
+    SINGLE_EVACTA_CNT_POSEDGE = $00;
+    SINGLE_EVACTA_CNT_ANYEDGE = $02;
+    SINGLE_EVACTA_CNT_HIGHLVL = $04;
+    SINGLE_EVACTA_UPDOWN = $06;
+    // TCA_SINGLE_EVACTB
+    SINGLE_EVACTBmask = $E0;
+    SINGLE_EVACTB_UPDOWN = $60;
+    SINGLE_EVACTB_RESTART_POSEDGE = $80;
+    SINGLE_EVACTB_RESTART_ANYEDGE = $A0;
+    SINGLE_EVACTB_RESTART_HIGHLVL = $C0;
+    // Compare 0 Interrupt
+    CMP0bm = $10;
+    // Compare 1 Interrupt
+    CMP1bm = $20;
+    // Compare 2 Interrupt
+    CMP2bm = $40;
+    // Overflow Interrupt
+    OVFbm = $01;
+  end;
+
+  TTCA_SPLIT = object //16-bit Timer/Counter Type A - Split Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    LCNT: byte;  //Low Count
+    HCNT: byte;  //High Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    LPER: byte;  //Low Period
+    HPER: byte;  //High Period
+    LCMP0: byte;  //Low Compare
+    HCMP0: byte;  //High Compare
+    LCMP1: byte;  //Low Compare
+    HCMP1: byte;  //High Compare
+    LCMP2: byte;  //Low Compare
+    HCMP2: byte;  //High Compare
+  const
+    // TCA_SPLIT_CLKSEL
+    SPLIT_CLKSELmask = $0E;
+    SPLIT_CLKSEL_DIV1 = $00;
+    SPLIT_CLKSEL_DIV2 = $02;
+    SPLIT_CLKSEL_DIV4 = $04;
+    SPLIT_CLKSEL_DIV8 = $06;
+    SPLIT_CLKSEL_DIV16 = $08;
+    SPLIT_CLKSEL_DIV64 = $0A;
+    SPLIT_CLKSEL_DIV256 = $0C;
+    SPLIT_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // High Compare 0 Enable
+    HCMP0ENbm = $10;
+    // High Compare 1 Enable
+    HCMP1ENbm = $20;
+    // High Compare 2 Enable
+    HCMP2ENbm = $40;
+    // Low Compare 0 Enable
+    LCMP0ENbm = $01;
+    // Low Compare 1 Enable
+    LCMP1ENbm = $02;
+    // Low Compare 2 Enable
+    LCMP2ENbm = $04;
+    // High Compare 0 Output Value
+    HCMP0OVbm = $10;
+    // High Compare 1 Output Value
+    HCMP1OVbm = $20;
+    // High Compare 2 Output Value
+    HCMP2OVbm = $40;
+    // Low Compare 0 Output Value
+    LCMP0OVbm = $01;
+    // Low Compare 1 Output Value
+    LCMP1OVbm = $02;
+    // Low Compare 2 Output Value
+    LCMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SPLIT_CMD
+    SPLIT_CMDmask = $0C;
+    SPLIT_CMD_NONE = $00;
+    SPLIT_CMD_UPDATE = $04;
+    SPLIT_CMD_RESTART = $08;
+    SPLIT_CMD_RESET = $0C;
+    // TCA_SPLIT_CMDEN
+    SPLIT_CMDENmask = $03;
+    SPLIT_CMDEN_NONE = $00;
+    SPLIT_CMDEN_BOTH = $03;
+    // Debug Run
+    DBGRUNbm = $01;
+    // High Underflow Interrupt Enable
+    HUNFbm = $02;
+    // Low Compare 0 Interrupt Enable
+    LCMP0bm = $10;
+    // Low Compare 1 Interrupt Enable
+    LCMP1bm = $20;
+    // Low Compare 2 Interrupt Enable
+    LCMP2bm = $40;
+    // Low Underflow Interrupt Enable
+    LUNFbm = $01;
+  end;
+
+  TTCA = record //16-bit Timer/Counter Type A
+    case byte of
+      0: (SINGLE: TTCA_SINGLE);
+      1: (SPLIT: TTCA_SPLIT);
+  end;
+
+  TTCB = object //16-bit Timer Type B
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control Register B
+    Reserved2: byte;
+    Reserved3: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status
+    DBGCTRL: byte;  //Debug Control
+    TEMP: byte;  //Temporary Value
+    CNT: word;  //Count
+    CCMP: word;  //Compare or Capture
+  const
+    // Cascade two timers
+    CASCADEbm = $20;
+    // TCB_CLKSEL
+    CLKSELmask = $0E;
+    CLKSEL_DIV1 = $00;
+    CLKSEL_DIV2 = $02;
+    CLKSEL_TCA0 = $04;
+    CLKSEL_EVENT = $0E;
+    // Enable
+    ENABLEbm = $01;
+    // Run Standby
+    RUNSTDBYbm = $40;
+    // Synchronize Update
+    SYNCUPDbm = $10;
+    // Asynchronous Enable
+    ASYNCbm = $40;
+    // Pin Output Enable
+    CCMPENbm = $10;
+    // Pin Initial State
+    CCMPINITbm = $20;
+    // TCB_CNTMODE
+    CNTMODEmask = $07;
+    CNTMODE_INT = $00;
+    CNTMODE_TIMEOUT = $01;
+    CNTMODE_CAPT = $02;
+    CNTMODE_FRQ = $03;
+    CNTMODE_PW = $04;
+    CNTMODE_FRQPW = $05;
+    CNTMODE_SINGLE = $06;
+    CNTMODE_PWM8 = $07;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Event Input Enable
+    CAPTEIbm = $01;
+    // Event Edge
+    EDGEbm = $10;
+    // Input Capture Noise Cancellation Filter
+    FILTERbm = $40;
+    // Capture or Timeout
+    CAPTbm = $01;
+    // Overflow
+    OVFbm = $02;
+    // Run
+    RUNbm = $01;
+  end;
+
+  TTWI = object //Two-Wire Interface
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    DBGCTRL: byte;  //Debug Control Register
+    MCTRLA: byte;  //Master Control A
+    MCTRLB: byte;  //Master Control B
+    MSTATUS: byte;  //Master Status
+    MBAUD: byte;  //Master Baud Rate Control
+    MADDR: byte;  //Master Address
+    MDATA: byte;  //Master Data
+    SCTRLA: byte;  //Slave Control A
+    SCTRLB: byte;  //Slave Control B
+    SSTATUS: byte;  //Slave Status
+    SADDR: byte;  //Slave Address
+    SDATA: byte;  //Slave Data
+    SADDRMASK: byte;  //Slave Address Mask
+  const
+    // FM Plus Enable
+    FMPENbm = $02;
+    // TWI_DEFAULT_SDAHOLD
+    DEFAULT_SDAHOLDmask = $0C;
+    DEFAULT_SDAHOLD_OFF = $00;
+    DEFAULT_SDAHOLD_50NS = $04;
+    DEFAULT_SDAHOLD_300NS = $08;
+    DEFAULT_SDAHOLD_500NS = $0C;
+    // TWI_DEFAULT_SDASETUP
+    DEFAULT_SDASETUPmask = $10;
+    DEFAULT_SDASETUP_4CYC = $00;
+    DEFAULT_SDASETUP_8CYC = $10;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Enable TWI Master
+    ENABLEbm = $01;
+    // Quick Command Enable
+    QCENbm = $10;
+    // Read Interrupt Enable
+    RIENbm = $80;
+    // Smart Mode Enable
+    SMENbm = $02;
+    // TWI_TIMEOUT
+    TIMEOUTmask = $0C;
+    TIMEOUT_DISABLED = $00;
+    TIMEOUT_50US = $04;
+    TIMEOUT_100US = $08;
+    TIMEOUT_200US = $0C;
+    // Write Interrupt Enable
+    WIENbm = $40;
+    // TWI_ACKACT
+    ACKACTmask = $04;
+    ACKACT_ACK = $00;
+    ACKACT_NACK = $04;
+    // Flush
+    FLUSHbm = $08;
+    // TWI_MCMD
+    MCMDmask = $03;
+    MCMD_NOACT = $00;
+    MCMD_REPSTART = $01;
+    MCMD_RECVTRANS = $02;
+    MCMD_STOP = $03;
+    // Arbitration Lost
+    ARBLOSTbm = $08;
+    // Bus Error
+    BUSERRbm = $04;
+    // TWI_BUSSTATE
+    BUSSTATEmask = $03;
+    BUSSTATE_UNKNOWN = $00;
+    BUSSTATE_IDLE = $01;
+    BUSSTATE_OWNER = $02;
+    BUSSTATE_BUSY = $03;
+    // Clock Hold
+    CLKHOLDbm = $20;
+    // Read Interrupt Flag
+    RIFbm = $80;
+    // Received Acknowledge
+    RXACKbm = $10;
+    // Write Interrupt Flag
+    WIFbm = $40;
+    // Address Enable
+    ADDRENbm = $01;
+    // Address Mask
+    ADDRMASK0bm = $02;
+    ADDRMASK1bm = $04;
+    ADDRMASK2bm = $08;
+    ADDRMASK3bm = $10;
+    ADDRMASK4bm = $20;
+    ADDRMASK5bm = $40;
+    ADDRMASK6bm = $80;
+    // Address/Stop Interrupt Enable
+    APIENbm = $40;
+    // Data Interrupt Enable
+    DIENbm = $80;
+    // Stop Interrupt Enable
+    PIENbm = $20;
+    // Permissive Mode Enable
+    PMENbm = $04;
+    // TWI_SCMD
+    SCMDmask = $03;
+    SCMD_NOACT = $00;
+    SCMD_COMPTRANS = $02;
+    SCMD_RESPONSE = $03;
+    // TWI_AP
+    APmask = $01;
+    AP_STOP = $00;
+    AP_ADR = $01;
+    // Address/Stop Interrupt Flag
+    APIFbm = $40;
+    // Collision
+    COLLbm = $08;
+    // Data Interrupt Flag
+    DIFbm = $80;
+    // Read/Write Direction
+    DIRbm = $02;
+  end;
+
+  TUSART = object //Universal Synchronous and Asynchronous Receiver and Transmitter
+    RXDATAL: byte;  //Receive Data Low Byte
+    RXDATAH: byte;  //Receive Data High Byte
+    TXDATAL: byte;  //Transmit Data Low Byte
+    TXDATAH: byte;  //Transmit Data High Byte
+    STATUS: byte;  //Status
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    BAUD: word;  //Baud Rate
+    CTRLD: byte;  //Control D
+    DBGCTRL: byte;  //Debug Control
+    EVCTRL: byte;  //Event Control
+    TXPLCTRL: byte;  //IRCOM Transmitter Pulse Length Control
+    RXPLCTRL: byte;  //IRCOM Receiver Pulse Length Control
+  const
+    // Auto-baud Error Interrupt Enable
+    ABEIEbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Loop-back Mode Enable
+    LBMEbm = $08;
+    // USART_RS485
+    RS485mask = $01;
+    RS485_DISABLE = $00;
+    RS485_ENABLE = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Receiver Start Frame Interrupt Enable
+    RXSIEbm = $10;
+    // Transmit Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Multi-processor Communication Mode
+    MPCMbm = $01;
+    // Open Drain Mode Enable
+    ODMEbm = $08;
+    // Reciever enable
+    RXENbm = $80;
+    // USART_RXMODE
+    RXMODEmask = $06;
+    RXMODE_NORMAL = $00;
+    RXMODE_CLK2X = $02;
+    RXMODE_GENAUTO = $04;
+    RXMODE_LINAUTO = $06;
+    // Start Frame Detection Enable
+    SFDENbm = $10;
+    // Transmitter Enable
+    TXENbm = $40;
+    // USART_MSPI_CMODE
+    MSPI_CMODEmask = $C0;
+    MSPI_CMODE_ASYNCHRONOUS = $00;
+    MSPI_CMODE_SYNCHRONOUS = $40;
+    MSPI_CMODE_IRCOM = $80;
+    MSPI_CMODE_MSPI = $C0;
+    // SPI Master Mode, Clock Phase
+    UCPHAbm = $02;
+    // SPI Master Mode, Data Order
+    UDORDbm = $04;
+    // USART_NORMAL_CHSIZE
+    NORMAL_CHSIZEmask = $07;
+    NORMAL_CHSIZE_5BIT = $00;
+    NORMAL_CHSIZE_6BIT = $01;
+    NORMAL_CHSIZE_7BIT = $02;
+    NORMAL_CHSIZE_8BIT = $03;
+    NORMAL_CHSIZE_9BITL = $06;
+    NORMAL_CHSIZE_9BITH = $07;
+    // USART_NORMAL_CMODE
+    NORMAL_CMODEmask = $C0;
+    NORMAL_CMODE_ASYNCHRONOUS = $00;
+    NORMAL_CMODE_SYNCHRONOUS = $40;
+    NORMAL_CMODE_IRCOM = $80;
+    NORMAL_CMODE_MSPI = $C0;
+    // USART_NORMAL_PMODE
+    NORMAL_PMODEmask = $30;
+    NORMAL_PMODE_DISABLED = $00;
+    NORMAL_PMODE_EVEN = $20;
+    NORMAL_PMODE_ODD = $30;
+    // USART_NORMAL_SBMODE
+    NORMAL_SBMODEmask = $08;
+    NORMAL_SBMODE_1BIT = $00;
+    NORMAL_SBMODE_2BIT = $08;
+    // USART_ABW
+    ABWmask = $C0;
+    ABW_WDW0 = $00;
+    ABW_WDW1 = $40;
+    ABW_WDW2 = $80;
+    ABW_WDW3 = $C0;
+    // Autobaud majority voter bypass
+    ABMBPbm = $80;
+    // Debug Run
+    DBGRUNbm = $01;
+    // IrDA Event Input Enable
+    IREIbm = $01;
+    // Buffer Overflow
+    BUFOVFbm = $40;
+    // Receiver Data Register
+    DATA8bm = $01;
+    // Frame Error
+    FERRbm = $04;
+    // Parity Error
+    PERRbm = $02;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // RX Data
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Receiver Pulse Lenght
+    RXPL0bm = $01;
+    RXPL1bm = $02;
+    RXPL2bm = $04;
+    RXPL3bm = $08;
+    RXPL4bm = $10;
+    RXPL5bm = $20;
+    RXPL6bm = $40;
+    // Break Detected Flag
+    BDFbm = $02;
+    // Data Register Empty Flag
+    DREIFbm = $20;
+    // Inconsistent Sync Field Interrupt Flag
+    ISFIFbm = $08;
+    // Receive Start Interrupt
+    RXSIFbm = $10;
+    // Transmit Interrupt Flag
+    TXCIFbm = $40;
+    // Wait For Break
+    WFBbm = $01;
+    // Transmit pulse length
+    TXPL0bm = $01;
+    TXPL1bm = $02;
+    TXPL2bm = $04;
+    TXPL3bm = $08;
+    TXPL4bm = $10;
+    TXPL5bm = $20;
+    TXPL6bm = $40;
+    TXPL7bm = $80;
+  end;
+
+  TUSERROW = object //User Row
+    USERROW0: byte;  //User Row Byte 0
+    USERROW1: byte;  //User Row Byte 1
+    USERROW2: byte;  //User Row Byte 2
+    USERROW3: byte;  //User Row Byte 3
+    USERROW4: byte;  //User Row Byte 4
+    USERROW5: byte;  //User Row Byte 5
+    USERROW6: byte;  //User Row Byte 6
+    USERROW7: byte;  //User Row Byte 7
+    USERROW8: byte;  //User Row Byte 8
+    USERROW9: byte;  //User Row Byte 9
+    USERROW10: byte;  //User Row Byte 10
+    USERROW11: byte;  //User Row Byte 11
+    USERROW12: byte;  //User Row Byte 12
+    USERROW13: byte;  //User Row Byte 13
+    USERROW14: byte;  //User Row Byte 14
+    USERROW15: byte;  //User Row Byte 15
+    USERROW16: byte;  //User Row Byte 16
+    USERROW17: byte;  //User Row Byte 17
+    USERROW18: byte;  //User Row Byte 18
+    USERROW19: byte;  //User Row Byte 19
+    USERROW20: byte;  //User Row Byte 20
+    USERROW21: byte;  //User Row Byte 21
+    USERROW22: byte;  //User Row Byte 22
+    USERROW23: byte;  //User Row Byte 23
+    USERROW24: byte;  //User Row Byte 24
+    USERROW25: byte;  //User Row Byte 25
+    USERROW26: byte;  //User Row Byte 26
+    USERROW27: byte;  //User Row Byte 27
+    USERROW28: byte;  //User Row Byte 28
+    USERROW29: byte;  //User Row Byte 29
+    USERROW30: byte;  //User Row Byte 30
+    USERROW31: byte;  //User Row Byte 31
+    USERROW32: byte;  //User Row Byte 32
+    USERROW33: byte;  //User Row Byte 33
+    USERROW34: byte;  //User Row Byte 34
+    USERROW35: byte;  //User Row Byte 35
+    USERROW36: byte;  //User Row Byte 36
+    USERROW37: byte;  //User Row Byte 37
+    USERROW38: byte;  //User Row Byte 38
+    USERROW39: byte;  //User Row Byte 39
+    USERROW40: byte;  //User Row Byte 40
+    USERROW41: byte;  //User Row Byte 41
+    USERROW42: byte;  //User Row Byte 42
+    USERROW43: byte;  //User Row Byte 43
+    USERROW44: byte;  //User Row Byte 44
+    USERROW45: byte;  //User Row Byte 45
+    USERROW46: byte;  //User Row Byte 46
+    USERROW47: byte;  //User Row Byte 47
+    USERROW48: byte;  //User Row Byte 48
+    USERROW49: byte;  //User Row Byte 49
+    USERROW50: byte;  //User Row Byte 50
+    USERROW51: byte;  //User Row Byte 51
+    USERROW52: byte;  //User Row Byte 52
+    USERROW53: byte;  //User Row Byte 53
+    USERROW54: byte;  //User Row Byte 54
+    USERROW55: byte;  //User Row Byte 55
+    USERROW56: byte;  //User Row Byte 56
+    USERROW57: byte;  //User Row Byte 57
+    USERROW58: byte;  //User Row Byte 58
+    USERROW59: byte;  //User Row Byte 59
+    USERROW60: byte;  //User Row Byte 60
+    USERROW61: byte;  //User Row Byte 61
+    USERROW62: byte;  //User Row Byte 62
+    USERROW63: byte;  //User Row Byte 63
+  end;
+
+  TVPORT = object //Virtual Ports
+    DIR: byte;  //Data Direction
+    OUT_: byte;  //Output Value
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+  end;
+
+  TVREF = object //Voltage reference
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+  const
+    // VREF_AC0REFSEL
+    AC0REFSELmask = $07;
+    AC0REFSEL_1V024 = $00;
+    AC0REFSEL_2V048 = $01;
+    AC0REFSEL_2V5 = $02;
+    AC0REFSEL_4V096 = $03;
+    AC0REFSEL_AVDD = $07;
+    // AC0 DACREF reference enable
+    AC0REFENbm = $01;
+    // ADC0 reference enable
+    ADC0REFENbm = $02;
+    // NVM reference enable
+    NVMREFENbm = $04;
+  end;
+
+  TWDT = object //Watch-Dog Timer
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+  const
+    // WDT_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // WDT_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+    // Lock enable
+    LOCKbm = $80;
+    // Syncronization busy
+    SYNCBUSYbm = $01;
+  end;
+
+
+const
+ Pin0idx = 0;  Pin0bm = 1;
+ Pin1idx = 1;  Pin1bm = 2;
+ Pin2idx = 2;  Pin2bm = 4;
+ Pin3idx = 3;  Pin3bm = 8;
+ Pin4idx = 4;  Pin4bm = 16;
+ Pin5idx = 5;  Pin5bm = 32;
+ Pin6idx = 6;  Pin6bm = 64;
+ Pin7idx = 7;  Pin7bm = 128;
+
+var
+  VPORTA: TVPORT absolute $0000;
+  VPORTB: TVPORT absolute $0004;
+  VPORTC: TVPORT absolute $0008;
+  GPIO: TGPIO absolute $001C;
+  CPU: TCPU absolute $0030;
+  RSTCTRL: TRSTCTRL absolute $0040;
+  SLPCTRL: TSLPCTRL absolute $0050;
+  CLKCTRL: TCLKCTRL absolute $0060;
+  BOD: TBOD absolute $0080;
+  VREF: TVREF absolute $00A0;
+  NVMBIST: TNVMBIST absolute $00C0;
+  WDT: TWDT absolute $0100;
+  CPUINT: TCPUINT absolute $0110;
+  CRCSCAN: TCRCSCAN absolute $0120;
+  RTC: TRTC absolute $0140;
+  EVSYS: TEVSYS absolute $0180;
+  CCL: TCCL absolute $01C0;
+  PORTA: TPORT absolute $0400;
+  PORTB: TPORT absolute $0420;
+  PORTC: TPORT absolute $0440;
+  PORTMUX: TPORTMUX absolute $05E0;
+  ADC0: TADC absolute $0600;
+  AC0: TAC absolute $0680;
+  USART0: TUSART absolute $0800;
+  USART1: TUSART absolute $0820;
+  TWI0: TTWI absolute $08A0;
+  SPI0: TSPI absolute $08C0;
+  TCA0: TTCA absolute $0A00;
+  TCB0: TTCB absolute $0A80;
+  TCB1: TTCB absolute $0A90;
+  SYSCFG: TSYSCFG absolute $0F00;
+  NVMCTRL: TNVMCTRL absolute $1000;
+  SIGROW: TSIGROW absolute $1100;
+  FUSE: TFUSE absolute $1280;
+  LOCKBIT: TLOCKBIT absolute $128A;
+  USERROW: TUSERROW absolute $1300;
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure CRCSCAN_NMI_ISR; external name 'CRCSCAN_NMI_ISR'; // Interrupt 1 
+procedure BOD_VLM_ISR; external name 'BOD_VLM_ISR'; // Interrupt 2 
+procedure RTC_CNT_ISR; external name 'RTC_CNT_ISR'; // Interrupt 3 
+procedure RTC_PIT_ISR; external name 'RTC_PIT_ISR'; // Interrupt 4 
+procedure CCL_CCL_ISR; external name 'CCL_CCL_ISR'; // Interrupt 5 
+procedure PORTA_PORT_ISR; external name 'PORTA_PORT_ISR'; // Interrupt 6 
+procedure PORTB_PORT_ISR; external name 'PORTB_PORT_ISR'; // Interrupt 7 
+procedure TCA0_LUNF_ISR; external name 'TCA0_LUNF_ISR'; // Interrupt 8 
+//procedure TCA0_OVF_ISR; external name 'TCA0_OVF_ISR'; // Interrupt 8 
+procedure TCA0_HUNF_ISR; external name 'TCA0_HUNF_ISR'; // Interrupt 9 
+procedure TCA0_CMP0_ISR; external name 'TCA0_CMP0_ISR'; // Interrupt 10 
+//procedure TCA0_LCMP0_ISR; external name 'TCA0_LCMP0_ISR'; // Interrupt 10 
+procedure TCA0_CMP1_ISR; external name 'TCA0_CMP1_ISR'; // Interrupt 11 
+//procedure TCA0_LCMP1_ISR; external name 'TCA0_LCMP1_ISR'; // Interrupt 11 
+procedure TCA0_CMP2_ISR; external name 'TCA0_CMP2_ISR'; // Interrupt 12 
+//procedure TCA0_LCMP2_ISR; external name 'TCA0_LCMP2_ISR'; // Interrupt 12 
+procedure TCB0_INT_ISR; external name 'TCB0_INT_ISR'; // Interrupt 13 
+procedure TWI0_TWIS_ISR; external name 'TWI0_TWIS_ISR'; // Interrupt 14 
+procedure TWI0_TWIM_ISR; external name 'TWI0_TWIM_ISR'; // Interrupt 15 
+procedure SPI0_INT_ISR; external name 'SPI0_INT_ISR'; // Interrupt 16 
+procedure USART0_RXC_ISR; external name 'USART0_RXC_ISR'; // Interrupt 17 
+procedure USART0_DRE_ISR; external name 'USART0_DRE_ISR'; // Interrupt 18 
+procedure USART0_TXC_ISR; external name 'USART0_TXC_ISR'; // Interrupt 19 
+procedure AC0_AC_ISR; external name 'AC0_AC_ISR'; // Interrupt 20 
+procedure ADC0_ERROR_ISR; external name 'ADC0_ERROR_ISR'; // Interrupt 21 
+procedure ADC0_RESRDY_ISR; external name 'ADC0_RESRDY_ISR'; // Interrupt 22 
+procedure ADC0_SAMPRDY_ISR; external name 'ADC0_SAMPRDY_ISR'; // Interrupt 23 
+procedure PORTC_PORT_ISR; external name 'PORTC_PORT_ISR'; // Interrupt 24 
+procedure TCB1_INT_ISR; external name 'TCB1_INT_ISR'; // Interrupt 25 
+procedure USART1_RXC_ISR; external name 'USART1_RXC_ISR'; // Interrupt 26 
+procedure USART1_DRE_ISR; external name 'USART1_DRE_ISR'; // Interrupt 27 
+procedure USART1_TXC_ISR; external name 'USART1_TXC_ISR'; // Interrupt 28 
+procedure NVMCTRL_EE_ISR; external name 'NVMCTRL_EE_ISR'; // Interrupt 29 
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp CRCSCAN_NMI_ISR
+  jmp BOD_VLM_ISR
+  jmp RTC_CNT_ISR
+  jmp RTC_PIT_ISR
+  jmp CCL_CCL_ISR
+  jmp PORTA_PORT_ISR
+  jmp PORTB_PORT_ISR
+  jmp TCA0_LUNF_ISR
+//  jmp TCA0_OVF_ISR
+  jmp TCA0_HUNF_ISR
+  jmp TCA0_CMP0_ISR
+//  jmp TCA0_LCMP0_ISR
+  jmp TCA0_CMP1_ISR
+//  jmp TCA0_LCMP1_ISR
+  jmp TCA0_CMP2_ISR
+//  jmp TCA0_LCMP2_ISR
+  jmp TCB0_INT_ISR
+  jmp TWI0_TWIS_ISR
+  jmp TWI0_TWIM_ISR
+  jmp SPI0_INT_ISR
+  jmp USART0_RXC_ISR
+  jmp USART0_DRE_ISR
+  jmp USART0_TXC_ISR
+  jmp AC0_AC_ISR
+  jmp ADC0_ERROR_ISR
+  jmp ADC0_RESRDY_ISR
+  jmp ADC0_SAMPRDY_ISR
+  jmp PORTC_PORT_ISR
+  jmp TCB1_INT_ISR
+  jmp USART1_RXC_ISR
+  jmp USART1_DRE_ISR
+  jmp USART1_TXC_ISR
+  jmp NVMCTRL_EE_ISR
+
+  {$i start.inc}
+
+  .weak CRCSCAN_NMI_ISR
+  .weak BOD_VLM_ISR
+  .weak RTC_CNT_ISR
+  .weak RTC_PIT_ISR
+  .weak CCL_CCL_ISR
+  .weak PORTA_PORT_ISR
+  .weak PORTB_PORT_ISR
+  .weak TCA0_LUNF_ISR
+//  .weak TCA0_OVF_ISR
+  .weak TCA0_HUNF_ISR
+  .weak TCA0_CMP0_ISR
+//  .weak TCA0_LCMP0_ISR
+  .weak TCA0_CMP1_ISR
+//  .weak TCA0_LCMP1_ISR
+  .weak TCA0_CMP2_ISR
+//  .weak TCA0_LCMP2_ISR
+  .weak TCB0_INT_ISR
+  .weak TWI0_TWIS_ISR
+  .weak TWI0_TWIM_ISR
+  .weak SPI0_INT_ISR
+  .weak USART0_RXC_ISR
+  .weak USART0_DRE_ISR
+  .weak USART0_TXC_ISR
+  .weak AC0_AC_ISR
+  .weak ADC0_ERROR_ISR
+  .weak ADC0_RESRDY_ISR
+  .weak ADC0_SAMPRDY_ISR
+  .weak PORTC_PORT_ISR
+  .weak TCB1_INT_ISR
+  .weak USART1_RXC_ISR
+  .weak USART1_DRE_ISR
+  .weak USART1_TXC_ISR
+  .weak NVMCTRL_EE_ISR
+
+  .set CRCSCAN_NMI_ISR, Default_IRQ_handler
+  .set BOD_VLM_ISR, Default_IRQ_handler
+  .set RTC_CNT_ISR, Default_IRQ_handler
+  .set RTC_PIT_ISR, Default_IRQ_handler
+  .set CCL_CCL_ISR, Default_IRQ_handler
+  .set PORTA_PORT_ISR, Default_IRQ_handler
+  .set PORTB_PORT_ISR, Default_IRQ_handler
+  .set TCA0_LUNF_ISR, Default_IRQ_handler
+//  .set TCA0_OVF_ISR, Default_IRQ_handler
+  .set TCA0_HUNF_ISR, Default_IRQ_handler
+  .set TCA0_CMP0_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP0_ISR, Default_IRQ_handler
+  .set TCA0_CMP1_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP1_ISR, Default_IRQ_handler
+  .set TCA0_CMP2_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP2_ISR, Default_IRQ_handler
+  .set TCB0_INT_ISR, Default_IRQ_handler
+  .set TWI0_TWIS_ISR, Default_IRQ_handler
+  .set TWI0_TWIM_ISR, Default_IRQ_handler
+  .set SPI0_INT_ISR, Default_IRQ_handler
+  .set USART0_RXC_ISR, Default_IRQ_handler
+  .set USART0_DRE_ISR, Default_IRQ_handler
+  .set USART0_TXC_ISR, Default_IRQ_handler
+  .set AC0_AC_ISR, Default_IRQ_handler
+  .set ADC0_ERROR_ISR, Default_IRQ_handler
+  .set ADC0_RESRDY_ISR, Default_IRQ_handler
+  .set ADC0_SAMPRDY_ISR, Default_IRQ_handler
+  .set PORTC_PORT_ISR, Default_IRQ_handler
+  .set TCB1_INT_ISR, Default_IRQ_handler
+  .set USART1_RXC_ISR, Default_IRQ_handler
+  .set USART1_DRE_ISR, Default_IRQ_handler
+  .set USART1_TXC_ISR, Default_IRQ_handler
+  .set NVMCTRL_EE_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/attiny1627.pp

@@ -0,0 +1,2522 @@
+unit ATtiny1627;
+
+{$goto on}
+interface
+
+type
+  TAC = object //Analog Comparator
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    MUXCTRLA: byte;  //Mux Control A
+    Reserved3: byte;
+    DACREF: byte;  //Referance scale control
+    Reserved5: byte;
+    INTCTRL: byte;  //Interrupt Control
+    STATUS: byte;  //Status
+  const
+    // Enable
+    ENABLEbm = $01;
+    // AC_HYSMODE
+    HYSMODEmask = $06;
+    HYSMODE_OFF = $00;
+    HYSMODE_10mV = $02;
+    HYSMODE_25mV = $04;
+    HYSMODE_50mV = $06;
+    // AC_INTMODE
+    INTMODEmask = $30;
+    INTMODE_BOTHEDGE = $00;
+    INTMODE_NEGEDGE = $20;
+    INTMODE_POSEDGE = $30;
+    // AC_LPMODE
+    LPMODEmask = $08;
+    LPMODE_DIS = $00;
+    LPMODE_EN = $08;
+    // Output Buffer Enable
+    OUTENbm = $40;
+    // Run in Standby Mode
+    RUNSTDBYbm = $80;
+    // DAC voltage reference
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Analog Comparator 0 Interrupt Enable
+    CMPbm = $01;
+    // Invert AC Output
+    INVERTbm = $80;
+    // AC_MUXNEG
+    MUXNEGmask = $03;
+    MUXNEG_PIN0 = $00;
+    MUXNEG_PIN1 = $01;
+    MUXNEG_PIN2 = $02;
+    MUXNEG_DACREF = $03;
+    // AC_MUXPOS
+    MUXPOSmask = $18;
+    MUXPOS_PIN0 = $00;
+    MUXPOS_PIN1 = $08;
+    MUXPOS_PIN2 = $10;
+    MUXPOS_PIN3 = $18;
+    // Analog Comparator State
+    STATEbm = $10;
+  end;
+
+  TADC = object //Analog to Digital Converter
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status register
+    DBGCTRL: byte;  //Debug Control
+    CTRLE: byte;  //Control E
+    CTRLF: byte;  //Control F
+    COMMAND: byte;  //Command register
+    PGACTRL: byte;  //PGA Control
+    MUXPOS: byte;  //Positive mux input
+    MUXNEG: byte;  //Negative mux input
+    Reserved14: byte;
+    Reserved15: byte;
+    RESULT: dword;  //Result
+    SAMPLE: word;  //Sample
+    Reserved22: byte;
+    Reserved23: byte;
+    TEMP0: byte;  //Temporary Data 0
+    TEMP1: byte;  //Temporary Data 1
+    TEMP2: byte;  //Temporary Data 2
+    Reserved27: byte;
+    WINLT: word;  //Window Low Threshold
+    WINHT: word;  //Window High Threshold
+  const
+    // Differential mode
+    DIFFbm = $80;
+    // ADC_MODE
+    MODEmask = $70;
+    MODE_SINGLE_8BIT = $00;
+    MODE_SINGLE_12BIT = $10;
+    MODE_SERIES = $20;
+    MODE_SERIES_TRUNCATION = $30;
+    MODE_BURST = $40;
+    MODE_BURST_TRUNCATION = $50;
+    // ADC_START
+    STARTmask = $07;
+    START_STOP = $00;
+    START_IMMEDIATE = $01;
+    START_MUXPOS_WRITE = $02;
+    START_MUXNEG_WRITE = $03;
+    START_EVENT_TRIGGER = $04;
+    // ADC Enable
+    ENABLEbm = $01;
+    // ADC Low latency mode
+    LOWLATbm = $20;
+    // Run standby mode
+    RUNSTDBYbm = $80;
+    // ADC_PRESC
+    PRESCmask = $0F;
+    PRESC_DIV2 = $00;
+    PRESC_DIV4 = $01;
+    PRESC_DIV6 = $02;
+    PRESC_DIV8 = $03;
+    PRESC_DIV10 = $04;
+    PRESC_DIV12 = $05;
+    PRESC_DIV14 = $06;
+    PRESC_DIV16 = $07;
+    PRESC_DIV20 = $08;
+    PRESC_DIV24 = $09;
+    PRESC_DIV28 = $0A;
+    PRESC_DIV32 = $0B;
+    PRESC_DIV40 = $0C;
+    PRESC_DIV48 = $0D;
+    PRESC_DIV56 = $0E;
+    PRESC_DIV64 = $0F;
+    // ADC_REFSEL
+    REFSELmask = $07;
+    REFSEL_VDD = $00;
+    REFSEL_VREFA = $02;
+    REFSEL_1024MV = $04;
+    REFSEL_2048MV = $05;
+    REFSEL_2500MV = $06;
+    REFSEL_4096MV = $07;
+    // Reference Selection
+    TIMEBASE0bm = $08;
+    TIMEBASE1bm = $10;
+    TIMEBASE2bm = $20;
+    TIMEBASE3bm = $40;
+    TIMEBASE4bm = $80;
+    // ADC_WINCM
+    WINCMmask = $07;
+    WINCM_NONE = $00;
+    WINCM_BELOW = $01;
+    WINCM_ABOVE = $02;
+    WINCM_INSIDE = $03;
+    WINCM_OUTSIDE = $04;
+    // ADC_WINSRC
+    WINSRCmask = $08;
+    WINSRC_RESULT = $00;
+    WINSRC_SAMPLE = $08;
+    // Sampling time
+    SAMPDUR0bm = $01;
+    SAMPDUR1bm = $02;
+    SAMPDUR2bm = $04;
+    SAMPDUR3bm = $08;
+    SAMPDUR4bm = $10;
+    SAMPDUR5bm = $20;
+    SAMPDUR6bm = $40;
+    SAMPDUR7bm = $80;
+    // Free running mode
+    FREERUNbm = $20;
+    // Left adjust
+    LEFTADJbm = $10;
+    // ADC_SAMPNUM
+    SAMPNUMmask = $0F;
+    SAMPNUM_NONE = $00;
+    SAMPNUM_ACC2 = $01;
+    SAMPNUM_ACC4 = $02;
+    SAMPNUM_ACC8 = $03;
+    SAMPNUM_ACC16 = $04;
+    SAMPNUM_ACC32 = $05;
+    SAMPNUM_ACC64 = $06;
+    SAMPNUM_ACC128 = $07;
+    SAMPNUM_ACC256 = $08;
+    SAMPNUM_ACC512 = $09;
+    SAMPNUM_ACC1024 = $0A;
+    // Debug run
+    DBGRUNbm = $01;
+    // Result Overwritten Interrupt Enable
+    RESOVRbm = $08;
+    // Result Ready Interrupt Enable
+    RESRDYbm = $01;
+    // Sample Overwritten Interrupt Enable
+    SAMPOVRbm = $10;
+    // Sample Ready Interrupt Enable
+    SAMPRDYbm = $02;
+    // Trigger Overrun Interrupt Enable
+    TRIGOVRbm = $20;
+    // Window Comparator Interrupt Enable
+    WCMPbm = $04;
+    // ADC_MUXNEG
+    MUXNEGmask = $3F;
+    MUXNEG_AIN1 = $01;
+    MUXNEG_AIN2 = $02;
+    MUXNEG_AIN3 = $03;
+    MUXNEG_AIN4 = $04;
+    MUXNEG_AIN5 = $05;
+    MUXNEG_AIN6 = $06;
+    MUXNEG_AIN7 = $07;
+    MUXNEG_GND = $30;
+    MUXNEG_VDDDIV10 = $31;
+    MUXNEG_DAC = $33;
+    // ADC_VIA
+    VIAmask = $C0;
+    VIA_ADC = $00;
+    VIA_PGA = $40;
+    // ADC_MUXPOS
+    MUXPOSmask = $3F;
+    MUXPOS_AIN1 = $01;
+    MUXPOS_AIN2 = $02;
+    MUXPOS_AIN3 = $03;
+    MUXPOS_AIN4 = $04;
+    MUXPOS_AIN5 = $05;
+    MUXPOS_AIN6 = $06;
+    MUXPOS_AIN7 = $07;
+    MUXPOS_AIN8 = $08;
+    MUXPOS_AIN9 = $09;
+    MUXPOS_AIN10 = $0A;
+    MUXPOS_AIN11 = $0B;
+    MUXPOS_AIN12 = $0C;
+    MUXPOS_AIN13 = $0D;
+    MUXPOS_AIN14 = $0E;
+    MUXPOS_AIN15 = $0F;
+    MUXPOS_GND = $30;
+    MUXPOS_VDDDIV10 = $31;
+    MUXPOS_TEMPSENSE = $32;
+    MUXPOS_DAC = $33;
+    // ADC_ADCPGASAMPDUR
+    ADCPGASAMPDURmask = $06;
+    ADCPGASAMPDUR_6CLK = $00;
+    ADCPGASAMPDUR_15CLK = $02;
+    ADCPGASAMPDUR_20CLK = $04;
+    ADCPGASAMPDUR_32CLK = $06;
+    // ADC_GAIN
+    GAINmask = $E0;
+    GAIN_1X = $00;
+    GAIN_2X = $20;
+    GAIN_4X = $40;
+    GAIN_8X = $60;
+    GAIN_16X = $80;
+    // ADC_PGABIASSEL
+    PGABIASSELmask = $18;
+    PGABIASSEL_1X = $00;
+    PGABIASSEL_3_4X = $08;
+    PGABIASSEL_1_2X = $10;
+    PGABIASSEL_1_4X = $18;
+    // PGA Enable
+    PGAENbm = $01;
+    // ADC Busy
+    ADCBUSYbm = $01;
+    // Temporary
+    TEMP0bm = $01;
+    TEMP1bm = $02;
+    TEMP2bm = $04;
+    TEMP3bm = $08;
+    TEMP4bm = $10;
+    TEMP5bm = $20;
+    TEMP6bm = $40;
+    TEMP7bm = $80;
+  end;
+
+  TBOD = object //Bod interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    VLMCTRLA: byte;  //Voltage level monitor Control
+    INTCTRL: byte;  //Voltage level monitor interrupt Control
+    INTFLAGS: byte;  //Voltage level monitor interrupt Flags
+    STATUS: byte;  //Voltage level monitor status
+  const
+    // BOD_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // BOD_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // BOD_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // BOD_LVL
+    LVLmask = $07;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $02;
+    LVL_BODLEVEL7 = $07;
+    // BOD_VLMCFG
+    VLMCFGmask = $06;
+    VLMCFG_BELOW = $00;
+    VLMCFG_ABOVE = $02;
+    VLMCFG_CROSS = $04;
+    // voltage level monitor interrrupt enable
+    VLMIEbm = $01;
+    // Voltage level monitor interrupt flag
+    VLMIFbm = $01;
+    // Voltage level monitor status
+    VLMSbm = $01;
+    // BOD_VLMLVL
+    VLMLVLmask = $03;
+    VLMLVL_5ABOVE = $00;
+    VLMLVL_15ABOVE = $01;
+    VLMLVL_25ABOVE = $02;
+  end;
+
+  TCCL = object //Configurable Custom Logic
+    CTRLA: byte;  //Control Register A
+    SEQCTRL0: byte;  //Sequential Control 0
+    SEQCTRL1: byte;  //Sequential Control 1
+    Reserved3: byte;
+    Reserved4: byte;
+    INTCTRL0: byte;  //Interrupt Control 0
+    Reserved6: byte;
+    INTFLAGS: byte;  //Interrupt Flags
+    LUT0CTRLA: byte;  //LUT Control 0 A
+    LUT0CTRLB: byte;  //LUT Control 0 B
+    LUT0CTRLC: byte;  //LUT Control 0 C
+    TRUTH0: byte;  //Truth 0
+    LUT1CTRLA: byte;  //LUT Control 1 A
+    LUT1CTRLB: byte;  //LUT Control 1 B
+    LUT1CTRLC: byte;  //LUT Control 1 C
+    TRUTH1: byte;  //Truth 1
+    LUT2CTRLA: byte;  //LUT Control 2 A
+    LUT2CTRLB: byte;  //LUT Control 2 B
+    LUT2CTRLC: byte;  //LUT Control 2 C
+    TRUTH2: byte;  //Truth 2
+    LUT3CTRLA: byte;  //LUT Control 3 A
+    LUT3CTRLB: byte;  //LUT Control 3 B
+    LUT3CTRLC: byte;  //LUT Control 3 C
+    TRUTH3: byte;  //Truth 3
+  const
+    // Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $40;
+    // CCL_INTMODE0
+    INTMODE0mask = $03;
+    INTMODE0_INTDISABLE = $00;
+    INTMODE0_RISING = $01;
+    INTMODE0_FALLING = $02;
+    INTMODE0_BOTH = $03;
+    // CCL_INTMODE1
+    INTMODE1mask = $0C;
+    INTMODE1_INTDISABLE = $00;
+    INTMODE1_RISING = $04;
+    INTMODE1_FALLING = $08;
+    INTMODE1_BOTH = $0C;
+    // CCL_INTMODE2
+    INTMODE2mask = $30;
+    INTMODE2_INTDISABLE = $00;
+    INTMODE2_RISING = $10;
+    INTMODE2_FALLING = $20;
+    INTMODE2_BOTH = $30;
+    // CCL_INTMODE3
+    INTMODE3mask = $C0;
+    INTMODE3_INTDISABLE = $00;
+    INTMODE3_RISING = $40;
+    INTMODE3_FALLING = $80;
+    INTMODE3_BOTH = $C0;
+    // Interrupt Flags
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    // CCL_CLKSRC
+    CLKSRCmask = $0E;
+    CLKSRC_CLKPER = $00;
+    CLKSRC_IN2 = $02;
+    CLKSRC_OSC20M = $08;
+    CLKSRC_OSCULP32K = $0A;
+    CLKSRC_OSCULP1K = $0C;
+    // CCL_EDGEDET
+    EDGEDETmask = $80;
+    EDGEDET_DIS = $00;
+    EDGEDET_EN = $80;
+    // CCL_FILTSEL
+    FILTSELmask = $30;
+    FILTSEL_DISABLE = $00;
+    FILTSEL_SYNCH = $10;
+    FILTSEL_FILTER = $20;
+    // Output Enable
+    OUTENbm = $40;
+    // CCL_INSEL0
+    INSEL0mask = $0F;
+    INSEL0_MASK = $00;
+    INSEL0_FEEDBACK = $01;
+    INSEL0_LINK = $02;
+    INSEL0_EVENTA = $03;
+    INSEL0_EVENTB = $04;
+    INSEL0_IO = $05;
+    INSEL0_AC0 = $06;
+    INSEL0_USART0 = $08;
+    INSEL0_SPI0 = $09;
+    INSEL0_TCA0 = $0A;
+    INSEL0_TCB0 = $0C;
+    // CCL_INSEL1
+    INSEL1mask = $F0;
+    INSEL1_MASK = $00;
+    INSEL1_FEEDBACK = $10;
+    INSEL1_LINK = $20;
+    INSEL1_EVENTA = $30;
+    INSEL1_EVENTB = $40;
+    INSEL1_IO = $50;
+    INSEL1_AC0 = $60;
+    INSEL1_USART1 = $80;
+    INSEL1_SPI0 = $90;
+    INSEL1_TCA0 = $A0;
+    INSEL1_TCB1 = $C0;
+    // CCL_INSEL2
+    INSEL2mask = $0F;
+    INSEL2_MASK = $00;
+    INSEL2_FEEDBACK = $01;
+    INSEL2_LINK = $02;
+    INSEL2_EVENTA = $03;
+    INSEL2_EVENTB = $04;
+    INSEL2_IO = $05;
+    INSEL2_AC0 = $06;
+    INSEL2_SPI0 = $09;
+    INSEL2_TCA0 = $0A;
+    // CCL_SEQSEL0
+    SEQSEL0mask = $07;
+    SEQSEL0_DISABLE = $00;
+    SEQSEL0_DFF = $01;
+    SEQSEL0_JK = $02;
+    SEQSEL0_LATCH = $03;
+    SEQSEL0_RS = $04;
+    // CCL_SEQSEL1
+    SEQSEL1mask = $07;
+    SEQSEL1_DISABLE = $00;
+    SEQSEL1_DFF = $01;
+    SEQSEL1_JK = $02;
+    SEQSEL1_LATCH = $03;
+    SEQSEL1_RS = $04;
+  end;
+
+  TCLKCTRL = object //Clock controller
+    MCLKCTRLA: byte;  //MCLK Control A
+    MCLKCTRLB: byte;  //MCLK Control B
+    MCLKLOCK: byte;  //MCLK Lock
+    MCLKSTATUS: byte;  //MCLK Status
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    OSC20MCTRLA: byte;  //OSC20M Control A
+    OSC20MCALIBA: byte;  //OSC20M Calibration A
+    OSC20MCALIBB: byte;  //OSC20M Calibration B
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSC32KCTRLA: byte;  //OSC32K Control A
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    XOSC32KCTRLA: byte;  //XOSC32K Control A
+  const
+    // System clock out
+    CLKOUTbm = $80;
+    // CLKCTRL_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_OSC20M = $00;
+    CLKSEL_OSCULP32K = $01;
+    CLKSEL_XOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // CLKCTRL_PDIV
+    PDIVmask = $1E;
+    PDIV_2X = $00;
+    PDIV_4X = $02;
+    PDIV_8X = $04;
+    PDIV_16X = $06;
+    PDIV_32X = $08;
+    PDIV_64X = $0A;
+    PDIV_6X = $10;
+    PDIV_10X = $12;
+    PDIV_12X = $14;
+    PDIV_24X = $16;
+    PDIV_48X = $18;
+    // Prescaler enable
+    PENbm = $01;
+    // lock ebable
+    LOCKENbm = $01;
+    // External Clock status
+    EXTSbm = $80;
+    // 20MHz oscillator status
+    OSC20MSbm = $10;
+    // 32KHz oscillator status
+    OSC32KSbm = $20;
+    // System Oscillator changing
+    SOSCbm = $01;
+    // 32.768 kHz Crystal Oscillator status
+    XOSC32KSbm = $40;
+    // Calibration
+    CAL20M0bm = $01;
+    CAL20M1bm = $02;
+    CAL20M2bm = $04;
+    CAL20M3bm = $08;
+    CAL20M4bm = $10;
+    CAL20M5bm = $20;
+    CAL20M6bm = $40;
+    // Lock
+    LOCKbm = $80;
+    // Oscillator temperature coefficient
+    TEMPCAL20M0bm = $01;
+    TEMPCAL20M1bm = $02;
+    TEMPCAL20M2bm = $04;
+    TEMPCAL20M3bm = $08;
+    // Run standby
+    RUNSTDBYbm = $02;
+    // CLKCTRL_CSUT
+    CSUTmask = $30;
+    CSUT_1K = $00;
+    CSUT_16K = $10;
+    CSUT_32K = $20;
+    CSUT_64K = $30;
+    // Enable
+    ENABLEbm = $01;
+    // Select
+    SELbm = $04;
+  end;
+
+  TCPU = object //CPU
+    Reserved0: byte;
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    CCP: byte;  //Configuration Change Protection
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    RAMPZ: byte;  //Extended Z-pointer Register
+    Reserved12: byte;
+    SPL: byte;  //Stack Pointer Low
+    SPH: byte;  //Stack Pointer High
+    SREG: byte;  //Status Register
+  const
+    // CPU_CCP
+    CCPmask = $FF;
+    CCP_SPM = $9D;
+    CCP_IOREG = $D8;
+    // Carry Flag
+    Cbm = $01;
+    // Half Carry Flag
+    Hbm = $20;
+    // Global Interrupt Enable Flag
+    Ibm = $80;
+    // Negative Flag
+    Nbm = $04;
+    // N Exclusive Or V Flag
+    Sbm = $10;
+    // Transfer Bit
+    Tbm = $40;
+    // Two's Complement Overflow Flag
+    Vbm = $08;
+    // Zero Flag
+    Zbm = $02;
+  end;
+
+  TCPUINT = object //Interrupt Controller
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    LVL0PRI: byte;  //Interrupt Level 0 Priority
+    LVL1VEC: byte;  //Interrupt Level 1 Priority Vector
+  const
+    // Compact Vector Table
+    CVTbm = $20;
+    // Interrupt Vector Select
+    IVSELbm = $40;
+    // Round-robin Scheduling Enable
+    LVL0RRbm = $01;
+    // Interrupt Level Priority
+    LVL0PRI0bm = $01;
+    LVL0PRI1bm = $02;
+    LVL0PRI2bm = $04;
+    LVL0PRI3bm = $08;
+    LVL0PRI4bm = $10;
+    LVL0PRI5bm = $20;
+    LVL0PRI6bm = $40;
+    LVL0PRI7bm = $80;
+    // Interrupt Vector with High Priority
+    LVL1VEC0bm = $01;
+    LVL1VEC1bm = $02;
+    LVL1VEC2bm = $04;
+    LVL1VEC3bm = $08;
+    LVL1VEC4bm = $10;
+    LVL1VEC5bm = $20;
+    LVL1VEC6bm = $40;
+    LVL1VEC7bm = $80;
+    // Level 0 Interrupt Executing
+    LVL0EXbm = $01;
+    // Level 1 Interrupt Executing
+    LVL1EXbm = $02;
+    // Non-maskable Interrupt Executing
+    NMIEXbm = $80;
+  end;
+
+  TCRCSCAN = object //CRCSCAN
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+  const
+    // Enable CRC scan
+    ENABLEbm = $01;
+    // Enable NMI Trigger
+    NMIENbm = $02;
+    // Reset CRC scan
+    RESETbm = $80;
+    // CRCSCAN_SRC
+    SRCmask = $03;
+    SRC_FLASH = $00;
+    SRC_APPLICATION = $01;
+    SRC_BOOT = $02;
+    // CRC Busy
+    BUSYbm = $01;
+    // CRC Ok
+    OKbm = $02;
+  end;
+
+  TEVSYS = object //Event System
+    SWEVENTA: byte;  //Software Event A
+    Reserved1: byte;
+    Reserved2: byte;
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    CHANNEL0: byte;  //Multiplexer Channel 0
+    CHANNEL1: byte;  //Multiplexer Channel 1
+    CHANNEL2: byte;  //Multiplexer Channel 2
+    CHANNEL3: byte;  //Multiplexer Channel 3
+    CHANNEL4: byte;  //Multiplexer Channel 4
+    CHANNEL5: byte;  //Multiplexer Channel 5
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    USERCCLLUT0A: byte;  //User CCL LUT0 Event A
+    USERCCLLUT0B: byte;  //User CCL LUT0 Event B
+    USERCCLLUT1A: byte;  //User CCL LUT1 Event A
+    USERCCLLUT1B: byte;  //User CCL LUT1 Event B
+    USERCCLLUT2A: byte;  //User CCL LUT2 Event A
+    USERCCLLUT2B: byte;  //User CCL LUT2 Event B
+    USERCCLLUT3A: byte;  //User CCL LUT3 Event A
+    USERCCLLUT3B: byte;  //User CCL LUT3 Event B
+    USERADC0START: byte;  //User ADC0
+    USEREVSYSEVOUTA: byte;  //User EVOUT Port A
+    USEREVSYSEVOUTB: byte;  //User EVOUT Port B
+    USEREVSYSEVOUTC: byte;  //User EVOUT Port C
+    USERUSART0IRDA: byte;  //User USART0
+    USERUSART1IRDA: byte;  //User USART1
+    USERTCA0CNTA: byte;  //User TCA0 count event
+    USERTCA0CNTB: byte;  //User TCA0 Restart event
+    USERTCB0CAPT: byte;  //User TCB0 Event in A
+    USERTCB0COUNT: byte;  //User TCB0 Event in B
+    USERTCB1CAPT: byte;  //User TCB1 Event in A
+    USERTCB1COUNT: byte;  //User TCB1 Event in B
+  const
+    // EVSYS_CHANNEL0
+    CHANNEL0mask = $FF;
+    CHANNEL0_OFF = $00;
+    CHANNEL0_UPDI = $01;
+    CHANNEL0_RTC_OVF = $06;
+    CHANNEL0_RTC_CMP = $07;
+    CHANNEL0_RTC_PIT_DIV8192 = $08;
+    CHANNEL0_RTC_PIT_DIV4096 = $09;
+    CHANNEL0_RTC_PIT_DIV2048 = $0A;
+    CHANNEL0_RTC_PIT_DIV1024 = $0B;
+    CHANNEL0_CCL_LUT0 = $10;
+    CHANNEL0_CCL_LUT1 = $11;
+    CHANNEL0_CCL_LUT2 = $12;
+    CHANNEL0_CCL_LUT3 = $13;
+    CHANNEL0_AC0_OUT = $20;
+    CHANNEL0_ADC0_RES = $24;
+    CHANNEL0_ADC0_SAMP = $25;
+    CHANNEL0_ADC0_WCMP = $26;
+    CHANNEL0_PORTA_PIN0 = $40;
+    CHANNEL0_PORTA_PIN1 = $41;
+    CHANNEL0_PORTA_PIN2 = $42;
+    CHANNEL0_PORTA_PIN3 = $43;
+    CHANNEL0_PORTA_PIN4 = $44;
+    CHANNEL0_PORTA_PIN5 = $45;
+    CHANNEL0_PORTA_PIN6 = $46;
+    CHANNEL0_PORTA_PIN7 = $47;
+    CHANNEL0_PORTB_PIN0 = $48;
+    CHANNEL0_PORTB_PIN1 = $49;
+    CHANNEL0_PORTB_PIN2 = $4A;
+    CHANNEL0_PORTB_PIN3 = $4B;
+    CHANNEL0_PORTB_PIN4 = $4C;
+    CHANNEL0_PORTB_PIN5 = $4D;
+    CHANNEL0_PORTB_PIN6 = $4E;
+    CHANNEL0_PORTB_PIN7 = $4F;
+    CHANNEL0_USART0_XCK = $60;
+    CHANNEL0_USART1_XCK = $61;
+    CHANNEL0_SPI0_SCK = $68;
+    CHANNEL0_TCA0_OVF_LUNF = $80;
+    CHANNEL0_TCA0_HUNF = $81;
+    CHANNEL0_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL0_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL0_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL0_TCB0_CAPT = $A0;
+    CHANNEL0_TCB0_OVF = $A1;
+    CHANNEL0_TCB1_CAPT = $A2;
+    CHANNEL0_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL1
+    CHANNEL1mask = $FF;
+    CHANNEL1_OFF = $00;
+    CHANNEL1_UPDI = $01;
+    CHANNEL1_RTC_OVF = $06;
+    CHANNEL1_RTC_CMP = $07;
+    CHANNEL1_RTC_PIT_DIV512 = $08;
+    CHANNEL1_RTC_PIT_DIV256 = $09;
+    CHANNEL1_RTC_PIT_DIV128 = $0A;
+    CHANNEL1_RTC_PIT_DIV64 = $0B;
+    CHANNEL1_CCL_LUT0 = $10;
+    CHANNEL1_CCL_LUT1 = $11;
+    CHANNEL1_CCL_LUT2 = $12;
+    CHANNEL1_CCL_LUT3 = $13;
+    CHANNEL1_AC0_OUT = $20;
+    CHANNEL1_ADC0_RES = $24;
+    CHANNEL1_ADC0_SAMP = $25;
+    CHANNEL1_ADC0_WCMP = $26;
+    CHANNEL1_PORTA_PIN0 = $40;
+    CHANNEL1_PORTA_PIN1 = $41;
+    CHANNEL1_PORTA_PIN2 = $42;
+    CHANNEL1_PORTA_PIN3 = $43;
+    CHANNEL1_PORTA_PIN4 = $44;
+    CHANNEL1_PORTA_PIN5 = $45;
+    CHANNEL1_PORTA_PIN6 = $46;
+    CHANNEL1_PORTA_PIN7 = $47;
+    CHANNEL1_PORTB_PIN0 = $48;
+    CHANNEL1_PORTB_PIN1 = $49;
+    CHANNEL1_PORTB_PIN2 = $4A;
+    CHANNEL1_PORTB_PIN3 = $4B;
+    CHANNEL1_PORTB_PIN4 = $4C;
+    CHANNEL1_PORTB_PIN5 = $4D;
+    CHANNEL1_PORTB_PIN6 = $4E;
+    CHANNEL1_PORTB_PIN7 = $4F;
+    CHANNEL1_USART0_XCK = $60;
+    CHANNEL1_USART1_XCK = $61;
+    CHANNEL1_SPI0_SCK = $68;
+    CHANNEL1_TCA0_OVF_LUNF = $80;
+    CHANNEL1_TCA0_HUNF = $81;
+    CHANNEL1_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL1_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL1_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL1_TCB0_CAPT = $A0;
+    CHANNEL1_TCB0_OVF = $A1;
+    CHANNEL1_TCB1_CAPT = $A2;
+    CHANNEL1_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL2
+    CHANNEL2mask = $FF;
+    CHANNEL2_OFF = $00;
+    CHANNEL2_UPDI = $01;
+    CHANNEL2_RTC_OVF = $06;
+    CHANNEL2_RTC_CMP = $07;
+    CHANNEL2_RTC_PIT_DIV8192 = $08;
+    CHANNEL2_RTC_PIT_DIV4096 = $09;
+    CHANNEL2_RTC_PIT_DIV2048 = $0A;
+    CHANNEL2_RTC_PIT_DIV1024 = $0B;
+    CHANNEL2_CCL_LUT0 = $10;
+    CHANNEL2_CCL_LUT1 = $11;
+    CHANNEL2_CCL_LUT2 = $12;
+    CHANNEL2_CCL_LUT3 = $13;
+    CHANNEL2_AC0_OUT = $20;
+    CHANNEL2_ADC0_RES = $24;
+    CHANNEL2_ADC0_SAMP = $25;
+    CHANNEL2_ADC0_WCMP = $26;
+    CHANNEL2_PORTC_PIN0 = $40;
+    CHANNEL2_PORTC_PIN1 = $41;
+    CHANNEL2_PORTC_PIN2 = $42;
+    CHANNEL2_PORTC_PIN3 = $43;
+    CHANNEL2_PORTC_PIN4 = $44;
+    CHANNEL2_PORTC_PIN5 = $45;
+    CHANNEL2_PORTC_PIN6 = $46;
+    CHANNEL2_PORTC_PIN7 = $47;
+    CHANNEL2_PORTA_PIN0 = $48;
+    CHANNEL2_PORTA_PIN1 = $49;
+    CHANNEL2_PORTA_PIN2 = $4A;
+    CHANNEL2_PORTA_PIN3 = $4B;
+    CHANNEL2_PORTA_PIN4 = $4C;
+    CHANNEL2_PORTA_PIN5 = $4D;
+    CHANNEL2_PORTA_PIN6 = $4E;
+    CHANNEL2_PORTA_PIN7 = $4F;
+    CHANNEL2_USART0_XCK = $60;
+    CHANNEL2_USART1_XCK = $61;
+    CHANNEL2_SPI0_SCK = $68;
+    CHANNEL2_TCA0_OVF_LUNF = $80;
+    CHANNEL2_TCA0_HUNF = $81;
+    CHANNEL2_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL2_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL2_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL2_TCB0_CAPT = $A0;
+    CHANNEL2_TCB0_OVF = $A1;
+    CHANNEL2_TCB1_CAPT = $A2;
+    CHANNEL2_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL3
+    CHANNEL3mask = $FF;
+    CHANNEL3_OFF = $00;
+    CHANNEL3_UPDI = $01;
+    CHANNEL3_RTC_OVF = $06;
+    CHANNEL3_RTC_CMP = $07;
+    CHANNEL3_RTC_PIT_DIV512 = $08;
+    CHANNEL3_RTC_PIT_DIV256 = $09;
+    CHANNEL3_RTC_PIT_DIV128 = $0A;
+    CHANNEL3_RTC_PIT_DIV64 = $0B;
+    CHANNEL3_CCL_LUT0 = $10;
+    CHANNEL3_CCL_LUT1 = $11;
+    CHANNEL3_CCL_LUT2 = $12;
+    CHANNEL3_CCL_LUT3 = $13;
+    CHANNEL3_AC0_OUT = $20;
+    CHANNEL3_ADC0_RES = $24;
+    CHANNEL3_ADC0_SAMP = $25;
+    CHANNEL3_ADC0_WCMP = $26;
+    CHANNEL3_PORTC_PIN0 = $40;
+    CHANNEL3_PORTC_PIN1 = $41;
+    CHANNEL3_PORTC_PIN2 = $42;
+    CHANNEL3_PORTC_PIN3 = $43;
+    CHANNEL3_PORTC_PIN4 = $44;
+    CHANNEL3_PORTC_PIN5 = $45;
+    CHANNEL3_PORTC_PIN6 = $46;
+    CHANNEL3_PORTC_PIN7 = $47;
+    CHANNEL3_PORTA_PIN0 = $48;
+    CHANNEL3_PORTA_PIN1 = $49;
+    CHANNEL3_PORTA_PIN2 = $4A;
+    CHANNEL3_PORTA_PIN3 = $4B;
+    CHANNEL3_PORTA_PIN4 = $4C;
+    CHANNEL3_PORTA_PIN5 = $4D;
+    CHANNEL3_PORTA_PIN6 = $4E;
+    CHANNEL3_PORTA_PIN7 = $4F;
+    CHANNEL3_USART0_XCK = $60;
+    CHANNEL3_USART1_XCK = $61;
+    CHANNEL3_SPI0_SCK = $68;
+    CHANNEL3_TCA0_OVF_LUNF = $80;
+    CHANNEL3_TCA0_HUNF = $81;
+    CHANNEL3_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL3_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL3_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL3_TCB0_CAPT = $A0;
+    CHANNEL3_TCB0_OVF = $A1;
+    CHANNEL3_TCB1_CAPT = $A2;
+    CHANNEL3_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL4
+    CHANNEL4mask = $FF;
+    CHANNEL4_OFF = $00;
+    CHANNEL4_UPDI = $01;
+    CHANNEL4_RTC_OVF = $06;
+    CHANNEL4_RTC_CMP = $07;
+    CHANNEL4_RTC_PIT_DIV8192 = $08;
+    CHANNEL4_RTC_PIT_DIV4096 = $09;
+    CHANNEL4_RTC_PIT_DIV2048 = $0A;
+    CHANNEL4_RTC_PIT_DIV1024 = $0B;
+    CHANNEL4_CCL_LUT0 = $10;
+    CHANNEL4_CCL_LUT1 = $11;
+    CHANNEL4_CCL_LUT2 = $12;
+    CHANNEL4_CCL_LUT3 = $13;
+    CHANNEL4_AC0_OUT = $20;
+    CHANNEL4_ADC0_RES = $24;
+    CHANNEL4_ADC0_SAMP = $25;
+    CHANNEL4_ADC0_WCMP = $26;
+    CHANNEL4_PORTB_PIN0 = $40;
+    CHANNEL4_PORTB_PIN1 = $41;
+    CHANNEL4_PORTB_PIN2 = $42;
+    CHANNEL4_PORTB_PIN3 = $43;
+    CHANNEL4_PORTB_PIN4 = $44;
+    CHANNEL4_PORTB_PIN5 = $45;
+    CHANNEL4_PORTB_PIN6 = $46;
+    CHANNEL4_PORTB_PIN7 = $47;
+    CHANNEL4_PORTC_PIN0 = $48;
+    CHANNEL4_PORTC_PIN1 = $49;
+    CHANNEL4_PORTC_PIN2 = $4A;
+    CHANNEL4_PORTC_PIN3 = $4B;
+    CHANNEL4_PORTC_PIN4 = $4C;
+    CHANNEL4_PORTC_PIN5 = $4D;
+    CHANNEL4_PORTC_PIN6 = $4E;
+    CHANNEL4_PORTC_PIN7 = $4F;
+    CHANNEL4_USART0_XCK = $60;
+    CHANNEL4_USART1_XCK = $61;
+    CHANNEL4_SPI0_SCK = $68;
+    CHANNEL4_TCA0_OVF_LUNF = $80;
+    CHANNEL4_TCA0_HUNF = $81;
+    CHANNEL4_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL4_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL4_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL4_TCB0_CAPT = $A0;
+    CHANNEL4_TCB0_OVF = $A1;
+    CHANNEL4_TCB1_CAPT = $A2;
+    CHANNEL4_TCB1_OVF = $A3;
+    // EVSYS_CHANNEL5
+    CHANNEL5mask = $FF;
+    CHANNEL5_OFF = $00;
+    CHANNEL5_UPDI = $01;
+    CHANNEL5_RTC_OVF = $06;
+    CHANNEL5_RTC_CMP = $07;
+    CHANNEL5_RTC_PIT_DIV512 = $08;
+    CHANNEL5_RTC_PIT_DIV256 = $09;
+    CHANNEL5_RTC_PIT_DIV128 = $0A;
+    CHANNEL5_RTC_PIT_DIV64 = $0B;
+    CHANNEL5_CCL_LUT0 = $10;
+    CHANNEL5_CCL_LUT1 = $11;
+    CHANNEL5_CCL_LUT2 = $12;
+    CHANNEL5_CCL_LUT3 = $13;
+    CHANNEL5_AC0_OUT = $20;
+    CHANNEL5_ADC0_RES = $24;
+    CHANNEL5_ADC0_SAMP = $25;
+    CHANNEL5_ADC0_WCMP = $26;
+    CHANNEL5_PORTB_PIN0 = $40;
+    CHANNEL5_PORTB_PIN1 = $41;
+    CHANNEL5_PORTB_PIN2 = $42;
+    CHANNEL5_PORTB_PIN3 = $43;
+    CHANNEL5_PORTB_PIN4 = $44;
+    CHANNEL5_PORTB_PIN5 = $45;
+    CHANNEL5_PORTB_PIN6 = $46;
+    CHANNEL5_PORTB_PIN7 = $47;
+    CHANNEL5_PORTC_PIN0 = $48;
+    CHANNEL5_PORTC_PIN1 = $49;
+    CHANNEL5_PORTC_PIN2 = $4A;
+    CHANNEL5_PORTC_PIN3 = $4B;
+    CHANNEL5_PORTC_PIN4 = $4C;
+    CHANNEL5_PORTC_PIN5 = $4D;
+    CHANNEL5_PORTC_PIN6 = $4E;
+    CHANNEL5_PORTC_PIN7 = $4F;
+    CHANNEL5_USART0_XCK = $60;
+    CHANNEL5_USART1_XCK = $61;
+    CHANNEL5_SPI0_SCK = $68;
+    CHANNEL5_TCA0_OVF_LUNF = $80;
+    CHANNEL5_TCA0_HUNF = $81;
+    CHANNEL5_TCA0_CMP0_LCMP0 = $84;
+    CHANNEL5_TCA0_CMP1_LCMP1 = $85;
+    CHANNEL5_TCA0_CMP2_LCMP2 = $86;
+    CHANNEL5_TCB0_CAPT = $A0;
+    CHANNEL5_TCB0_OVF = $A1;
+    CHANNEL5_TCB1_CAPT = $A2;
+    CHANNEL5_TCB1_OVF = $A3;
+    // EVSYS_SWEVENTA
+    SWEVENTAmask = $FF;
+    SWEVENTA_CH0 = $01;
+    SWEVENTA_CH1 = $02;
+    SWEVENTA_CH2 = $04;
+    SWEVENTA_CH3 = $08;
+    SWEVENTA_CH4 = $10;
+    SWEVENTA_CH5 = $20;
+    // EVSYS_USER
+    USERmask = $FF;
+    USER_OFF = $00;
+    USER_CHANNEL0 = $01;
+    USER_CHANNEL1 = $02;
+    USER_CHANNEL2 = $03;
+    USER_CHANNEL3 = $04;
+    USER_CHANNEL4 = $05;
+    USER_CHANNEL5 = $06;
+  end;
+
+  TFUSE = object //Fuses
+    WDTCFG: byte;  //Watchdog Configuration
+    BODCFG: byte;  //BOD Configuration
+    OSCCFG: byte;  //Oscillator Configuration
+    Reserved3: byte;
+    Reserved4: byte;
+    SYSCFG0: byte;  //System Configuration 0
+    SYSCFG1: byte;  //System Configuration 1
+    APPEND: byte;  //Application Code Section End
+    BOOTEND: byte;  //Boot Section End
+  const
+    // FUSE_ACTIVE
+    ACTIVEmask = $0C;
+    ACTIVE_DIS = $00;
+    ACTIVE_ENABLED = $04;
+    ACTIVE_SAMPLED = $08;
+    ACTIVE_ENWAKE = $0C;
+    // FUSE_LVL
+    LVLmask = $E0;
+    LVL_BODLEVEL0 = $00;
+    LVL_BODLEVEL2 = $40;
+    LVL_BODLEVEL7 = $E0;
+    // FUSE_SAMPFREQ
+    SAMPFREQmask = $10;
+    SAMPFREQ_1KHZ = $00;
+    SAMPFREQ_125HZ = $10;
+    // FUSE_SLEEP
+    SLEEPmask = $03;
+    SLEEP_DIS = $00;
+    SLEEP_ENABLED = $01;
+    SLEEP_SAMPLED = $02;
+    // FUSE_FREQSEL
+    FREQSELmask = $03;
+    FREQSEL_16MHZ = $01;
+    FREQSEL_20MHZ = $02;
+    // Oscillator Lock
+    OSCLOCKbm = $80;
+    // FUSE_CRCSRC
+    CRCSRCmask = $C0;
+    CRCSRC_FLASH = $00;
+    CRCSRC_BOOT = $40;
+    CRCSRC_BOOTAPP = $80;
+    CRCSRC_NOCRC = $C0;
+    // EEPROM Save
+    EESAVEbm = $01;
+    // FUSE_RSTPINCFG
+    RSTPINCFGmask = $0C;
+    RSTPINCFG_GPIO = $00;
+    RSTPINCFG_UPDI = $04;
+    RSTPINCFG_RST = $08;
+    RSTPINCFG_PDIRST = $0C;
+    // FUSE_SUT
+    SUTmask = $07;
+    SUT_0MS = $00;
+    SUT_1MS = $01;
+    SUT_2MS = $02;
+    SUT_4MS = $03;
+    SUT_8MS = $04;
+    SUT_16MS = $05;
+    SUT_32MS = $06;
+    SUT_64MS = $07;
+    // FUSE_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // FUSE_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+  end;
+
+  TGPIO = object //General Purpose IO
+    GPIOR0: byte;  //General Purpose IO Register 0
+    GPIOR1: byte;  //General Purpose IO Register 1
+    GPIOR2: byte;  //General Purpose IO Register 2
+    GPIOR3: byte;  //General Purpose IO Register 3
+  end;
+
+  TLOCKBIT = object //Lockbit
+    LOCKBIT: byte;  //Lock Bits
+  const
+    // LOCKBIT_LB
+    LBmask = $FF;
+    LB_RWLOCK = $3A;
+    LB_NOLOCK = $C5;
+  end;
+
+  TNVMBIST = object //BIST in the NVMCTRL module
+    CTRLA: byte;  //Control A
+    ADDRPAT: byte;  //Address pattern
+    DATAPAT: byte;  //Data pattern
+    STATUS: byte;  //Status
+    CNT: word;
+    END_: dword;
+  const
+    // NVMBIST_AMODE
+    AMODEmask = $70;
+    AMODE_NORMAL = $00;
+    AMODE_COMPLEMENT = $40;
+    // NVMBIST_XMODE
+    XMODEmask = $03;
+    XMODE_STATIC = $00;
+    XMODE_CARRY = $01;
+    XMODE_INC = $02;
+    XMODE_DEC = $03;
+    // NVMBIST_YMODE
+    YMODEmask = $0C;
+    YMODE_STATIC = $00;
+    YMODE_CARRY = $04;
+    YMODE_INC = $08;
+    YMODE_DEC = $0C;
+    // Faults counter
+    CNT0bm = $01;
+    CNT1bm = $02;
+    CNT2bm = $04;
+    CNT3bm = $08;
+    CNT4bm = $10;
+    CNT5bm = $20;
+    CNT6bm = $40;
+    CNT7bm = $80;
+    // NVMBIST_CMD
+    CMDmask = $07;
+    CMD_NOCMD = $00;
+    CMD_START = $01;
+    CMD_RESTART = $02;
+    CMD_BREAK = $03;
+    // Stop at fault
+    SAFbm = $08;
+    // NVMBIST_PATTERN
+    PATTERNmask = $03;
+    PATTERN_ZEROES = $00;
+    PATTERN_CHECK = $01;
+    PATTERN_INVCHECK = $02;
+    PATTERN_ONES = $03;
+    // 
+    END0bm = $01;
+    END1bm = $02;
+    END2bm = $04;
+    END3bm = $08;
+    END4bm = $10;
+    END5bm = $20;
+    END6bm = $40;
+    END7bm = $80;
+    // NVMBIST_STATE
+    STATEmask = $0F;
+    STATE_IDLE = $00;
+    STATE_BREAK = $01;
+    STATE_FAILED0 = $04;
+    STATE_FAILED1 = $05;
+    STATE_FAILED2 = $06;
+    STATE_SUCCESS = $07;
+    STATE_START0 = $08;
+    STATE_START1 = $09;
+    STATE_RESTART0 = $0A;
+    STATE_RESTART1 = $0B;
+    STATE_RUNNING = $0C;
+    STATE_FINISH0 = $0E;
+    STATE_FINISH1 = $0F;
+  end;
+
+  TNVMCTRL = object //Non-volatile Memory Controller
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved5: byte;
+    DATA: word;  //Data
+    ADDR: word;  //Address
+  const
+    // NVMCTRL_CMD
+    CMDmask = $07;
+    CMD_NONE = $00;
+    CMD_PAGEWRITE = $01;
+    CMD_PAGEERASE = $02;
+    CMD_PAGEERASEWRITE = $03;
+    CMD_PAGEBUFCLR = $04;
+    CMD_CHIPERASE = $05;
+    CMD_EEERASE = $06;
+    CMD_FUSEWRITE = $07;
+    // Application code write protect
+    APCWPbm = $01;
+    // Boot Lock
+    BOOTLOCKbm = $02;
+    // EEPROM Ready
+    EEREADYbm = $01;
+    // EEPROM busy
+    EEBUSYbm = $02;
+    // Flash busy
+    FBUSYbm = $01;
+    // Write error
+    WRERRORbm = $04;
+  end;
+
+  TPORT = object //I/O Ports
+    DIR: byte;  //Data Direction
+    DIRSET: byte;  //Data Direction Set
+    DIRCLR: byte;  //Data Direction Clear
+    DIRTGL: byte;  //Data Direction Toggle
+    OUT_: byte;  //Output Value
+    OUTSET: byte;  //Output Value Set
+    OUTCLR: byte;  //Output Value Clear
+    OUTTGL: byte;  //Output Value Toggle
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+    PORTCTRL: byte;  //Port Control
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    PIN0CTRL: byte;  //Pin 0 Control
+    PIN1CTRL: byte;  //Pin 1 Control
+    PIN2CTRL: byte;  //Pin 2 Control
+    PIN3CTRL: byte;  //Pin 3 Control
+    PIN4CTRL: byte;  //Pin 4 Control
+    PIN5CTRL: byte;  //Pin 5 Control
+    PIN6CTRL: byte;  //Pin 6 Control
+    PIN7CTRL: byte;  //Pin 7 Control
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+    // Inverted I/O Enable
+    INVENbm = $80;
+    // PORT_ISC
+    ISCmask = $07;
+    ISC_INTDISABLE = $00;
+    ISC_BOTHEDGES = $01;
+    ISC_RISING = $02;
+    ISC_FALLING = $03;
+    ISC_INPUT_DISABLE = $04;
+    ISC_LEVEL = $05;
+    // Pullup enable
+    PULLUPENbm = $08;
+    // Slew Rate Limit Enable
+    SRLbm = $01;
+  end;
+
+  TPORTMUX = object //Port Multiplexer
+    EVSYSROUTEA: byte;  //Port Multiplexer EVSYS
+    CCLROUTEA: byte;  //Port Multiplexer CCL
+    USARTROUTEA: byte;  //Port Multiplexer USART register A
+    SPIROUTEA: byte;  //Port Multiplexer TWI and SPI
+    TCAROUTEA: byte;  //Port Multiplexer TCA
+    TCBROUTEA: byte;  //Port Multiplexer TCB
+  const
+    // CCL LUT0
+    LUT0bm = $01;
+    // CCL LUT1
+    LUT1bm = $02;
+    // CCL LUT2
+    LUT2bm = $04;
+    // CCL LUT3
+    LUT3bm = $08;
+    // Event Output 0
+    EVOUT0bm = $01;
+    // Event Output 1
+    EVOUT1bm = $02;
+    // Event Output 2
+    EVOUT2bm = $04;
+    // Event Output 3
+    EVOUT3bm = $08;
+    // Event Output 4
+    EVOUT4bm = $10;
+    // Event Output 5
+    EVOUT5bm = $20;
+    // PORTMUX_SPI0
+    SPI0mask = $03;
+    SPI0_DEFAULT = $00;
+    SPI0_ALT1 = $01;
+    SPI0_ALT2 = $02;
+    SPI0_NONE = $03;
+    // PORTMUX_TWI0
+    TWI0mask = $30;
+    TWI0_DEFAULT = $00;
+    TWI0_ALT1 = $10;
+    TWI0_ALT2 = $20;
+    TWI0_NONE = $30;
+    // PORTMUX_TCA0
+    TCA0mask = $07;
+    TCA0_PORTA = $00;
+    TCA0_PORTB = $01;
+    TCA0_PORTC = $02;
+    TCA0_PORTD = $03;
+    TCA0_PORTE = $04;
+    TCA0_PORTF = $05;
+    // Port Multiplexer TCB0
+    TCB0bm = $01;
+    // Port Multiplexer TCB1
+    TCB1bm = $02;
+    // Port Multiplexer TCB2
+    TCB2bm = $04;
+    // Port Multiplexer TCB3
+    TCB3bm = $08;
+    // PORTMUX_USART0
+    USART0mask = $03;
+    USART0_DEFAULT = $00;
+    USART0_ALT1 = $01;
+    USART0_NONE = $03;
+    // PORTMUX_USART1
+    USART1mask = $0C;
+    USART1_DEFAULT = $00;
+    USART1_ALT1 = $04;
+    USART1_NONE = $0C;
+  end;
+
+  TRSTCTRL = object //Reset controller
+    RSTFR: byte;  //Reset Flags
+    SWRR: byte;  //Software Reset
+  const
+    // Brown out detector Reset flag
+    BORFbm = $02;
+    // External Reset flag
+    EXTRFbm = $04;
+    // Power on Reset flag
+    PORFbm = $01;
+    // Software Reset flag
+    SWRFbm = $10;
+    // UPDI Reset flag
+    UPDIRFbm = $20;
+    // Watch dog Reset flag
+    WDRFbm = $08;
+    // Software reset enable
+    SWREbm = $01;
+  end;
+
+  TRTC = object //Real-Time Counter
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    TEMP: byte;  //Temporary
+    DBGCTRL: byte;  //Debug control
+    CALIB: byte;  //Calibration
+    CLKSEL: byte;  //RTC Clock
+    CNT: word;  //Counter
+    PER: word;  //Period
+    CMP: word;  //Compare
+    Reserved14: byte;
+    Reserved15: byte;
+    PITCTRLA: byte;  //PIT Control A
+    PITSTATUS: byte;  //PIT Status
+    PITINTCTRL: byte;  //PIT Interrupt Control
+    PITINTFLAGS: byte;  //PIT Interrupt Flags
+    Reserved20: byte;
+    PITDBGCTRL: byte;  //PIT Debug control
+  const
+    // Error Correction Value
+    ERROR0bm = $01;
+    ERROR1bm = $02;
+    ERROR2bm = $04;
+    ERROR3bm = $08;
+    ERROR4bm = $10;
+    ERROR5bm = $20;
+    ERROR6bm = $40;
+    // Error Correction Sign Bit
+    SIGNbm = $80;
+    // RTC_CLKSEL
+    CLKSELmask = $03;
+    CLKSEL_INT32K = $00;
+    CLKSEL_INT1K = $01;
+    CLKSEL_TOSC32K = $02;
+    CLKSEL_EXTCLK = $03;
+    // Correction enable
+    CORRENbm = $04;
+    // RTC_PRESCALER
+    PRESCALERmask = $78;
+    PRESCALER_DIV1 = $00;
+    PRESCALER_DIV2 = $08;
+    PRESCALER_DIV4 = $10;
+    PRESCALER_DIV8 = $18;
+    PRESCALER_DIV16 = $20;
+    PRESCALER_DIV32 = $28;
+    PRESCALER_DIV64 = $30;
+    PRESCALER_DIV128 = $38;
+    PRESCALER_DIV256 = $40;
+    PRESCALER_DIV512 = $48;
+    PRESCALER_DIV1024 = $50;
+    PRESCALER_DIV2048 = $58;
+    PRESCALER_DIV4096 = $60;
+    PRESCALER_DIV8192 = $68;
+    PRESCALER_DIV16384 = $70;
+    PRESCALER_DIV32768 = $78;
+    // Enable
+    RTCENbm = $01;
+    // Run In Standby
+    RUNSTDBYbm = $80;
+    // Run in debug
+    DBGRUNbm = $01;
+    // Compare Match Interrupt enable
+    CMPbm = $02;
+    // Overflow Interrupt enable
+    OVFbm = $01;
+    // RTC_PERIOD
+    PERIODmask = $78;
+    PERIOD_OFF = $00;
+    PERIOD_CYC4 = $08;
+    PERIOD_CYC8 = $10;
+    PERIOD_CYC16 = $18;
+    PERIOD_CYC32 = $20;
+    PERIOD_CYC64 = $28;
+    PERIOD_CYC128 = $30;
+    PERIOD_CYC256 = $38;
+    PERIOD_CYC512 = $40;
+    PERIOD_CYC1024 = $48;
+    PERIOD_CYC2048 = $50;
+    PERIOD_CYC4096 = $58;
+    PERIOD_CYC8192 = $60;
+    PERIOD_CYC16384 = $68;
+    PERIOD_CYC32768 = $70;
+    // Enable
+    PITENbm = $01;
+    // Periodic Interrupt
+    PIbm = $01;
+    // CTRLA Synchronization Busy Flag
+    CTRLBUSYbm = $01;
+    // Comparator Synchronization Busy Flag
+    CMPBUSYbm = $08;
+    // Count Synchronization Busy Flag
+    CNTBUSYbm = $02;
+    // CTRLA Synchronization Busy Flag
+    CTRLABUSYbm = $01;
+    // Period Synchronization Busy Flag
+    PERBUSYbm = $04;
+  end;
+
+  TSIGROW = object //Signature row
+    DEVICEID0: byte;  //Device ID Byte 0
+    DEVICEID1: byte;  //Device ID Byte 1
+    DEVICEID2: byte;  //Device ID Byte 2
+    SERNUM0: byte;  //Serial Number Byte 0
+    SERNUM1: byte;  //Serial Number Byte 1
+    SERNUM2: byte;  //Serial Number Byte 2
+    SERNUM3: byte;  //Serial Number Byte 3
+    SERNUM4: byte;  //Serial Number Byte 4
+    SERNUM5: byte;  //Serial Number Byte 5
+    SERNUM6: byte;  //Serial Number Byte 6
+    SERNUM7: byte;  //Serial Number Byte 7
+    SERNUM8: byte;  //Serial Number Byte 8
+    SERNUM9: byte;  //Serial Number Byte 9
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    OSCCAL32K: byte;  //Oscillator Calibration for 32kHz ULP
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OSCCAL16M0: byte;  //Oscillator Calibration 16 MHz Byte 0
+    OSCCAL16M1: byte;  //Oscillator Calibration 16 MHz Byte 1
+    OSCCAL20M0: byte;  //Oscillator Calibration 20 MHz Byte 0
+    OSCCAL20M1: byte;  //Oscillator Calibration 20 MHz Byte 1
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    TEMPSENSE0: byte;  //Temperature Sensor Calibration Byte 0
+    TEMPSENSE1: byte;  //Temperature Sensor Calibration Byte 1
+    OSC16ERR3V: byte;  //OSC16 error at 3V
+    OSC16ERR5V: byte;  //OSC16 error at 5V
+    OSC20ERR3V: byte;  //OSC20 error at 3V
+    OSC20ERR5V: byte;  //OSC20 error at 5V
+    Reserved38: byte;
+    Reserved39: byte;
+    Reserved40: byte;
+    Reserved41: byte;
+    Reserved42: byte;
+    Reserved43: byte;
+    Reserved44: byte;
+    Reserved45: byte;
+    Reserved46: byte;
+    CHECKSUM1: byte;  //CRC Checksum Byte 1
+  end;
+
+  TSLPCTRL = object //Sleep Controller
+    CTRLA: byte;  //Control
+  const
+    // Sleep enable
+    SENbm = $01;
+    // SLPCTRL_SMODE
+    SMODEmask = $06;
+    SMODE_IDLE = $00;
+    SMODE_STDBY = $02;
+    SMODE_PDOWN = $04;
+  end;
+
+  TSPI = object //Serial Peripheral Interface
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    DATA: byte;  //Data
+  const
+    // Enable Double Speed
+    CLK2Xbm = $10;
+    // Data Order Setting
+    DORDbm = $40;
+    // Enable Module
+    ENABLEbm = $01;
+    // Master Operation Enable
+    MASTERbm = $20;
+    // SPI_PRESC
+    PRESCmask = $06;
+    PRESC_DIV4 = $00;
+    PRESC_DIV16 = $02;
+    PRESC_DIV64 = $04;
+    PRESC_DIV128 = $06;
+    // Buffer Mode Enable
+    BUFENbm = $80;
+    // Buffer Mode Wait for Receive
+    BUFWRbm = $40;
+    // SPI_MODE
+    MODEmask = $03;
+    MODE_0 = $00;
+    MODE_1 = $01;
+    MODE_2 = $02;
+    MODE_3 = $03;
+    // Slave Select Disable
+    SSDbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Interrupt Enable
+    IEbm = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Slave Select Trigger Interrupt Enable
+    SSIEbm = $10;
+    // Transfer Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Buffer Overflow
+    BUFOVFbm = $01;
+    // Data Register Empty Interrupt Flag
+    DREIFbm = $20;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // Slave Select Trigger Interrupt Flag
+    SSIFbm = $10;
+    // Transfer Complete Interrupt Flag
+    TXCIFbm = $40;
+    // Interrupt Flag
+    IFbm = $80;
+    // Write Collision
+    WRCOLbm = $40;
+  end;
+
+  TSYSCFG = object //System Configuration Registers
+    Reserved0: byte;
+    REVID: byte;  //Revision ID
+    EXTBRK: byte;  //External Break
+    Reserved3: byte;
+    Reserved4: byte;
+    Reserved5: byte;
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    Reserved10: byte;
+    Reserved11: byte;
+    Reserved12: byte;
+    Reserved13: byte;
+    Reserved14: byte;
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    OCDM: byte;  //OCD Message Register
+    OCDMS: byte;  //OCD Message Status
+  const
+    // External break enable
+    ENEXTBRKbm = $01;
+    // OCD Message Read
+    OCDMRbm = $01;
+  end;
+
+  TTCA_SINGLE = object //16-bit Timer/Counter Type A - Single Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    CTRLFCLR: byte;  //Control F Clear
+    CTRLFSET: byte;  //Control F Set
+    Reserved8: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    TEMP: byte;  //Temporary data for 16-bit Access
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    CNT: word;  //Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    PER: word;  //Period
+    CMP0: word;  //Compare 0
+    CMP1: word;  //Compare 1
+    CMP2: word;  //Compare 2
+    Reserved46: byte;
+    Reserved47: byte;
+    Reserved48: byte;
+    Reserved49: byte;
+    Reserved50: byte;
+    Reserved51: byte;
+    Reserved52: byte;
+    Reserved53: byte;
+    PERBUF: word;  //Period Buffer
+    CMP0BUF: word;  //Compare 0 Buffer
+    CMP1BUF: word;  //Compare 1 Buffer
+    CMP2BUF: word;  //Compare 2 Buffer
+  const
+    // TCA_SINGLE_CLKSEL
+    SINGLE_CLKSELmask = $0E;
+    SINGLE_CLKSEL_DIV1 = $00;
+    SINGLE_CLKSEL_DIV2 = $02;
+    SINGLE_CLKSEL_DIV4 = $04;
+    SINGLE_CLKSEL_DIV8 = $06;
+    SINGLE_CLKSEL_DIV16 = $08;
+    SINGLE_CLKSEL_DIV64 = $0A;
+    SINGLE_CLKSEL_DIV256 = $0C;
+    SINGLE_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // Auto Lock Update
+    ALUPDbm = $08;
+    // Compare 0 Enable
+    CMP0ENbm = $10;
+    // Compare 1 Enable
+    CMP1ENbm = $20;
+    // Compare 2 Enable
+    CMP2ENbm = $40;
+    // TCA_SINGLE_WGMODE
+    SINGLE_WGMODEmask = $07;
+    SINGLE_WGMODE_NORMAL = $00;
+    SINGLE_WGMODE_FRQ = $01;
+    SINGLE_WGMODE_SINGLESLOPE = $03;
+    SINGLE_WGMODE_DSTOP = $05;
+    SINGLE_WGMODE_DSBOTH = $06;
+    SINGLE_WGMODE_DSBOTTOM = $07;
+    // Compare 0 Waveform Output Value
+    CMP0OVbm = $01;
+    // Compare 1 Waveform Output Value
+    CMP1OVbm = $02;
+    // Compare 2 Waveform Output Value
+    CMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SINGLE_CMD
+    SINGLE_CMDmask = $0C;
+    SINGLE_CMD_NONE = $00;
+    SINGLE_CMD_UPDATE = $04;
+    SINGLE_CMD_RESTART = $08;
+    SINGLE_CMD_RESET = $0C;
+    // Direction
+    DIRbm = $01;
+    // Lock Update
+    LUPDbm = $02;
+    // Compare 0 Buffer Valid
+    CMP0BVbm = $02;
+    // Compare 1 Buffer Valid
+    CMP1BVbm = $04;
+    // Compare 2 Buffer Valid
+    CMP2BVbm = $08;
+    // Period Buffer Valid
+    PERBVbm = $01;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Count on Event Input A
+    CNTAEIbm = $01;
+    // Count on Event Input B
+    CNTBEIbm = $10;
+    // TCA_SINGLE_EVACTA
+    SINGLE_EVACTAmask = $0E;
+    SINGLE_EVACTA_CNT_POSEDGE = $00;
+    SINGLE_EVACTA_CNT_ANYEDGE = $02;
+    SINGLE_EVACTA_CNT_HIGHLVL = $04;
+    SINGLE_EVACTA_UPDOWN = $06;
+    // TCA_SINGLE_EVACTB
+    SINGLE_EVACTBmask = $E0;
+    SINGLE_EVACTB_UPDOWN = $60;
+    SINGLE_EVACTB_RESTART_POSEDGE = $80;
+    SINGLE_EVACTB_RESTART_ANYEDGE = $A0;
+    SINGLE_EVACTB_RESTART_HIGHLVL = $C0;
+    // Compare 0 Interrupt
+    CMP0bm = $10;
+    // Compare 1 Interrupt
+    CMP1bm = $20;
+    // Compare 2 Interrupt
+    CMP2bm = $40;
+    // Overflow Interrupt
+    OVFbm = $01;
+  end;
+
+  TTCA_SPLIT = object //16-bit Timer/Counter Type A - Split Mode
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    CTRLD: byte;  //Control D
+    CTRLECLR: byte;  //Control E Clear
+    CTRLESET: byte;  //Control E Set
+    Reserved6: byte;
+    Reserved7: byte;
+    Reserved8: byte;
+    Reserved9: byte;
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    Reserved12: byte;
+    Reserved13: byte;
+    DBGCTRL: byte;  //Degbug Control
+    Reserved15: byte;
+    Reserved16: byte;
+    Reserved17: byte;
+    Reserved18: byte;
+    Reserved19: byte;
+    Reserved20: byte;
+    Reserved21: byte;
+    Reserved22: byte;
+    Reserved23: byte;
+    Reserved24: byte;
+    Reserved25: byte;
+    Reserved26: byte;
+    Reserved27: byte;
+    Reserved28: byte;
+    Reserved29: byte;
+    Reserved30: byte;
+    Reserved31: byte;
+    LCNT: byte;  //Low Count
+    HCNT: byte;  //High Count
+    Reserved34: byte;
+    Reserved35: byte;
+    Reserved36: byte;
+    Reserved37: byte;
+    LPER: byte;  //Low Period
+    HPER: byte;  //High Period
+    LCMP0: byte;  //Low Compare
+    HCMP0: byte;  //High Compare
+    LCMP1: byte;  //Low Compare
+    HCMP1: byte;  //High Compare
+    LCMP2: byte;  //Low Compare
+    HCMP2: byte;  //High Compare
+  const
+    // TCA_SPLIT_CLKSEL
+    SPLIT_CLKSELmask = $0E;
+    SPLIT_CLKSEL_DIV1 = $00;
+    SPLIT_CLKSEL_DIV2 = $02;
+    SPLIT_CLKSEL_DIV4 = $04;
+    SPLIT_CLKSEL_DIV8 = $06;
+    SPLIT_CLKSEL_DIV16 = $08;
+    SPLIT_CLKSEL_DIV64 = $0A;
+    SPLIT_CLKSEL_DIV256 = $0C;
+    SPLIT_CLKSEL_DIV1024 = $0E;
+    // Module Enable
+    ENABLEbm = $01;
+    // Run in Standby
+    RUNSTDBYbm = $80;
+    // High Compare 0 Enable
+    HCMP0ENbm = $10;
+    // High Compare 1 Enable
+    HCMP1ENbm = $20;
+    // High Compare 2 Enable
+    HCMP2ENbm = $40;
+    // Low Compare 0 Enable
+    LCMP0ENbm = $01;
+    // Low Compare 1 Enable
+    LCMP1ENbm = $02;
+    // Low Compare 2 Enable
+    LCMP2ENbm = $04;
+    // High Compare 0 Output Value
+    HCMP0OVbm = $10;
+    // High Compare 1 Output Value
+    HCMP1OVbm = $20;
+    // High Compare 2 Output Value
+    HCMP2OVbm = $40;
+    // Low Compare 0 Output Value
+    LCMP0OVbm = $01;
+    // Low Compare 1 Output Value
+    LCMP1OVbm = $02;
+    // Low Compare 2 Output Value
+    LCMP2OVbm = $04;
+    // Split Mode Enable
+    SPLITMbm = $01;
+    // TCA_SPLIT_CMD
+    SPLIT_CMDmask = $0C;
+    SPLIT_CMD_NONE = $00;
+    SPLIT_CMD_UPDATE = $04;
+    SPLIT_CMD_RESTART = $08;
+    SPLIT_CMD_RESET = $0C;
+    // TCA_SPLIT_CMDEN
+    SPLIT_CMDENmask = $03;
+    SPLIT_CMDEN_NONE = $00;
+    SPLIT_CMDEN_BOTH = $03;
+    // Debug Run
+    DBGRUNbm = $01;
+    // High Underflow Interrupt Enable
+    HUNFbm = $02;
+    // Low Compare 0 Interrupt Enable
+    LCMP0bm = $10;
+    // Low Compare 1 Interrupt Enable
+    LCMP1bm = $20;
+    // Low Compare 2 Interrupt Enable
+    LCMP2bm = $40;
+    // Low Underflow Interrupt Enable
+    LUNFbm = $01;
+  end;
+
+  TTCA = record //16-bit Timer/Counter Type A
+    case byte of
+      0: (SINGLE: TTCA_SINGLE);
+      1: (SPLIT: TTCA_SPLIT);
+  end;
+
+  TTCB = object //16-bit Timer Type B
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control Register B
+    Reserved2: byte;
+    Reserved3: byte;
+    EVCTRL: byte;  //Event Control
+    INTCTRL: byte;  //Interrupt Control
+    INTFLAGS: byte;  //Interrupt Flags
+    STATUS: byte;  //Status
+    DBGCTRL: byte;  //Debug Control
+    TEMP: byte;  //Temporary Value
+    CNT: word;  //Count
+    CCMP: word;  //Compare or Capture
+  const
+    // Cascade two timers
+    CASCADEbm = $20;
+    // TCB_CLKSEL
+    CLKSELmask = $0E;
+    CLKSEL_DIV1 = $00;
+    CLKSEL_DIV2 = $02;
+    CLKSEL_TCA0 = $04;
+    CLKSEL_EVENT = $0E;
+    // Enable
+    ENABLEbm = $01;
+    // Run Standby
+    RUNSTDBYbm = $40;
+    // Synchronize Update
+    SYNCUPDbm = $10;
+    // Asynchronous Enable
+    ASYNCbm = $40;
+    // Pin Output Enable
+    CCMPENbm = $10;
+    // Pin Initial State
+    CCMPINITbm = $20;
+    // TCB_CNTMODE
+    CNTMODEmask = $07;
+    CNTMODE_INT = $00;
+    CNTMODE_TIMEOUT = $01;
+    CNTMODE_CAPT = $02;
+    CNTMODE_FRQ = $03;
+    CNTMODE_PW = $04;
+    CNTMODE_FRQPW = $05;
+    CNTMODE_SINGLE = $06;
+    CNTMODE_PWM8 = $07;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Event Input Enable
+    CAPTEIbm = $01;
+    // Event Edge
+    EDGEbm = $10;
+    // Input Capture Noise Cancellation Filter
+    FILTERbm = $40;
+    // Capture or Timeout
+    CAPTbm = $01;
+    // Overflow
+    OVFbm = $02;
+    // Run
+    RUNbm = $01;
+  end;
+
+  TTWI = object //Two-Wire Interface
+    CTRLA: byte;  //Control A
+    Reserved1: byte;
+    DBGCTRL: byte;  //Debug Control Register
+    MCTRLA: byte;  //Master Control A
+    MCTRLB: byte;  //Master Control B
+    MSTATUS: byte;  //Master Status
+    MBAUD: byte;  //Master Baud Rate Control
+    MADDR: byte;  //Master Address
+    MDATA: byte;  //Master Data
+    SCTRLA: byte;  //Slave Control A
+    SCTRLB: byte;  //Slave Control B
+    SSTATUS: byte;  //Slave Status
+    SADDR: byte;  //Slave Address
+    SDATA: byte;  //Slave Data
+    SADDRMASK: byte;  //Slave Address Mask
+  const
+    // FM Plus Enable
+    FMPENbm = $02;
+    // TWI_DEFAULT_SDAHOLD
+    DEFAULT_SDAHOLDmask = $0C;
+    DEFAULT_SDAHOLD_OFF = $00;
+    DEFAULT_SDAHOLD_50NS = $04;
+    DEFAULT_SDAHOLD_300NS = $08;
+    DEFAULT_SDAHOLD_500NS = $0C;
+    // TWI_DEFAULT_SDASETUP
+    DEFAULT_SDASETUPmask = $10;
+    DEFAULT_SDASETUP_4CYC = $00;
+    DEFAULT_SDASETUP_8CYC = $10;
+    // Debug Run
+    DBGRUNbm = $01;
+    // Enable TWI Master
+    ENABLEbm = $01;
+    // Quick Command Enable
+    QCENbm = $10;
+    // Read Interrupt Enable
+    RIENbm = $80;
+    // Smart Mode Enable
+    SMENbm = $02;
+    // TWI_TIMEOUT
+    TIMEOUTmask = $0C;
+    TIMEOUT_DISABLED = $00;
+    TIMEOUT_50US = $04;
+    TIMEOUT_100US = $08;
+    TIMEOUT_200US = $0C;
+    // Write Interrupt Enable
+    WIENbm = $40;
+    // TWI_ACKACT
+    ACKACTmask = $04;
+    ACKACT_ACK = $00;
+    ACKACT_NACK = $04;
+    // Flush
+    FLUSHbm = $08;
+    // TWI_MCMD
+    MCMDmask = $03;
+    MCMD_NOACT = $00;
+    MCMD_REPSTART = $01;
+    MCMD_RECVTRANS = $02;
+    MCMD_STOP = $03;
+    // Arbitration Lost
+    ARBLOSTbm = $08;
+    // Bus Error
+    BUSERRbm = $04;
+    // TWI_BUSSTATE
+    BUSSTATEmask = $03;
+    BUSSTATE_UNKNOWN = $00;
+    BUSSTATE_IDLE = $01;
+    BUSSTATE_OWNER = $02;
+    BUSSTATE_BUSY = $03;
+    // Clock Hold
+    CLKHOLDbm = $20;
+    // Read Interrupt Flag
+    RIFbm = $80;
+    // Received Acknowledge
+    RXACKbm = $10;
+    // Write Interrupt Flag
+    WIFbm = $40;
+    // Address Enable
+    ADDRENbm = $01;
+    // Address Mask
+    ADDRMASK0bm = $02;
+    ADDRMASK1bm = $04;
+    ADDRMASK2bm = $08;
+    ADDRMASK3bm = $10;
+    ADDRMASK4bm = $20;
+    ADDRMASK5bm = $40;
+    ADDRMASK6bm = $80;
+    // Address/Stop Interrupt Enable
+    APIENbm = $40;
+    // Data Interrupt Enable
+    DIENbm = $80;
+    // Stop Interrupt Enable
+    PIENbm = $20;
+    // Permissive Mode Enable
+    PMENbm = $04;
+    // TWI_SCMD
+    SCMDmask = $03;
+    SCMD_NOACT = $00;
+    SCMD_COMPTRANS = $02;
+    SCMD_RESPONSE = $03;
+    // TWI_AP
+    APmask = $01;
+    AP_STOP = $00;
+    AP_ADR = $01;
+    // Address/Stop Interrupt Flag
+    APIFbm = $40;
+    // Collision
+    COLLbm = $08;
+    // Data Interrupt Flag
+    DIFbm = $80;
+    // Read/Write Direction
+    DIRbm = $02;
+  end;
+
+  TUSART = object //Universal Synchronous and Asynchronous Receiver and Transmitter
+    RXDATAL: byte;  //Receive Data Low Byte
+    RXDATAH: byte;  //Receive Data High Byte
+    TXDATAL: byte;  //Transmit Data Low Byte
+    TXDATAH: byte;  //Transmit Data High Byte
+    STATUS: byte;  //Status
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+    CTRLC: byte;  //Control C
+    BAUD: word;  //Baud Rate
+    CTRLD: byte;  //Control D
+    DBGCTRL: byte;  //Debug Control
+    EVCTRL: byte;  //Event Control
+    TXPLCTRL: byte;  //IRCOM Transmitter Pulse Length Control
+    RXPLCTRL: byte;  //IRCOM Receiver Pulse Length Control
+  const
+    // Auto-baud Error Interrupt Enable
+    ABEIEbm = $04;
+    // Data Register Empty Interrupt Enable
+    DREIEbm = $20;
+    // Loop-back Mode Enable
+    LBMEbm = $08;
+    // USART_RS485
+    RS485mask = $01;
+    RS485_DISABLE = $00;
+    RS485_ENABLE = $01;
+    // Receive Complete Interrupt Enable
+    RXCIEbm = $80;
+    // Receiver Start Frame Interrupt Enable
+    RXSIEbm = $10;
+    // Transmit Complete Interrupt Enable
+    TXCIEbm = $40;
+    // Multi-processor Communication Mode
+    MPCMbm = $01;
+    // Open Drain Mode Enable
+    ODMEbm = $08;
+    // Reciever enable
+    RXENbm = $80;
+    // USART_RXMODE
+    RXMODEmask = $06;
+    RXMODE_NORMAL = $00;
+    RXMODE_CLK2X = $02;
+    RXMODE_GENAUTO = $04;
+    RXMODE_LINAUTO = $06;
+    // Start Frame Detection Enable
+    SFDENbm = $10;
+    // Transmitter Enable
+    TXENbm = $40;
+    // USART_MSPI_CMODE
+    MSPI_CMODEmask = $C0;
+    MSPI_CMODE_ASYNCHRONOUS = $00;
+    MSPI_CMODE_SYNCHRONOUS = $40;
+    MSPI_CMODE_IRCOM = $80;
+    MSPI_CMODE_MSPI = $C0;
+    // SPI Master Mode, Clock Phase
+    UCPHAbm = $02;
+    // SPI Master Mode, Data Order
+    UDORDbm = $04;
+    // USART_NORMAL_CHSIZE
+    NORMAL_CHSIZEmask = $07;
+    NORMAL_CHSIZE_5BIT = $00;
+    NORMAL_CHSIZE_6BIT = $01;
+    NORMAL_CHSIZE_7BIT = $02;
+    NORMAL_CHSIZE_8BIT = $03;
+    NORMAL_CHSIZE_9BITL = $06;
+    NORMAL_CHSIZE_9BITH = $07;
+    // USART_NORMAL_CMODE
+    NORMAL_CMODEmask = $C0;
+    NORMAL_CMODE_ASYNCHRONOUS = $00;
+    NORMAL_CMODE_SYNCHRONOUS = $40;
+    NORMAL_CMODE_IRCOM = $80;
+    NORMAL_CMODE_MSPI = $C0;
+    // USART_NORMAL_PMODE
+    NORMAL_PMODEmask = $30;
+    NORMAL_PMODE_DISABLED = $00;
+    NORMAL_PMODE_EVEN = $20;
+    NORMAL_PMODE_ODD = $30;
+    // USART_NORMAL_SBMODE
+    NORMAL_SBMODEmask = $08;
+    NORMAL_SBMODE_1BIT = $00;
+    NORMAL_SBMODE_2BIT = $08;
+    // USART_ABW
+    ABWmask = $C0;
+    ABW_WDW0 = $00;
+    ABW_WDW1 = $40;
+    ABW_WDW2 = $80;
+    ABW_WDW3 = $C0;
+    // Autobaud majority voter bypass
+    ABMBPbm = $80;
+    // Debug Run
+    DBGRUNbm = $01;
+    // IrDA Event Input Enable
+    IREIbm = $01;
+    // Buffer Overflow
+    BUFOVFbm = $40;
+    // Receiver Data Register
+    DATA8bm = $01;
+    // Frame Error
+    FERRbm = $04;
+    // Parity Error
+    PERRbm = $02;
+    // Receive Complete Interrupt Flag
+    RXCIFbm = $80;
+    // RX Data
+    DATA0bm = $01;
+    DATA1bm = $02;
+    DATA2bm = $04;
+    DATA3bm = $08;
+    DATA4bm = $10;
+    DATA5bm = $20;
+    DATA6bm = $40;
+    DATA7bm = $80;
+    // Receiver Pulse Lenght
+    RXPL0bm = $01;
+    RXPL1bm = $02;
+    RXPL2bm = $04;
+    RXPL3bm = $08;
+    RXPL4bm = $10;
+    RXPL5bm = $20;
+    RXPL6bm = $40;
+    // Break Detected Flag
+    BDFbm = $02;
+    // Data Register Empty Flag
+    DREIFbm = $20;
+    // Inconsistent Sync Field Interrupt Flag
+    ISFIFbm = $08;
+    // Receive Start Interrupt
+    RXSIFbm = $10;
+    // Transmit Interrupt Flag
+    TXCIFbm = $40;
+    // Wait For Break
+    WFBbm = $01;
+    // Transmit pulse length
+    TXPL0bm = $01;
+    TXPL1bm = $02;
+    TXPL2bm = $04;
+    TXPL3bm = $08;
+    TXPL4bm = $10;
+    TXPL5bm = $20;
+    TXPL6bm = $40;
+    TXPL7bm = $80;
+  end;
+
+  TUSERROW = object //User Row
+    USERROW0: byte;  //User Row Byte 0
+    USERROW1: byte;  //User Row Byte 1
+    USERROW2: byte;  //User Row Byte 2
+    USERROW3: byte;  //User Row Byte 3
+    USERROW4: byte;  //User Row Byte 4
+    USERROW5: byte;  //User Row Byte 5
+    USERROW6: byte;  //User Row Byte 6
+    USERROW7: byte;  //User Row Byte 7
+    USERROW8: byte;  //User Row Byte 8
+    USERROW9: byte;  //User Row Byte 9
+    USERROW10: byte;  //User Row Byte 10
+    USERROW11: byte;  //User Row Byte 11
+    USERROW12: byte;  //User Row Byte 12
+    USERROW13: byte;  //User Row Byte 13
+    USERROW14: byte;  //User Row Byte 14
+    USERROW15: byte;  //User Row Byte 15
+    USERROW16: byte;  //User Row Byte 16
+    USERROW17: byte;  //User Row Byte 17
+    USERROW18: byte;  //User Row Byte 18
+    USERROW19: byte;  //User Row Byte 19
+    USERROW20: byte;  //User Row Byte 20
+    USERROW21: byte;  //User Row Byte 21
+    USERROW22: byte;  //User Row Byte 22
+    USERROW23: byte;  //User Row Byte 23
+    USERROW24: byte;  //User Row Byte 24
+    USERROW25: byte;  //User Row Byte 25
+    USERROW26: byte;  //User Row Byte 26
+    USERROW27: byte;  //User Row Byte 27
+    USERROW28: byte;  //User Row Byte 28
+    USERROW29: byte;  //User Row Byte 29
+    USERROW30: byte;  //User Row Byte 30
+    USERROW31: byte;  //User Row Byte 31
+    USERROW32: byte;  //User Row Byte 32
+    USERROW33: byte;  //User Row Byte 33
+    USERROW34: byte;  //User Row Byte 34
+    USERROW35: byte;  //User Row Byte 35
+    USERROW36: byte;  //User Row Byte 36
+    USERROW37: byte;  //User Row Byte 37
+    USERROW38: byte;  //User Row Byte 38
+    USERROW39: byte;  //User Row Byte 39
+    USERROW40: byte;  //User Row Byte 40
+    USERROW41: byte;  //User Row Byte 41
+    USERROW42: byte;  //User Row Byte 42
+    USERROW43: byte;  //User Row Byte 43
+    USERROW44: byte;  //User Row Byte 44
+    USERROW45: byte;  //User Row Byte 45
+    USERROW46: byte;  //User Row Byte 46
+    USERROW47: byte;  //User Row Byte 47
+    USERROW48: byte;  //User Row Byte 48
+    USERROW49: byte;  //User Row Byte 49
+    USERROW50: byte;  //User Row Byte 50
+    USERROW51: byte;  //User Row Byte 51
+    USERROW52: byte;  //User Row Byte 52
+    USERROW53: byte;  //User Row Byte 53
+    USERROW54: byte;  //User Row Byte 54
+    USERROW55: byte;  //User Row Byte 55
+    USERROW56: byte;  //User Row Byte 56
+    USERROW57: byte;  //User Row Byte 57
+    USERROW58: byte;  //User Row Byte 58
+    USERROW59: byte;  //User Row Byte 59
+    USERROW60: byte;  //User Row Byte 60
+    USERROW61: byte;  //User Row Byte 61
+    USERROW62: byte;  //User Row Byte 62
+    USERROW63: byte;  //User Row Byte 63
+  end;
+
+  TVPORT = object //Virtual Ports
+    DIR: byte;  //Data Direction
+    OUT_: byte;  //Output Value
+    IN_: byte;  //Input Value
+    INTFLAGS: byte;  //Interrupt Flags
+  const
+    // Pin Interrupt
+    INT0bm = $01;
+    INT1bm = $02;
+    INT2bm = $04;
+    INT3bm = $08;
+    INT4bm = $10;
+    INT5bm = $20;
+    INT6bm = $40;
+    INT7bm = $80;
+  end;
+
+  TVREF = object //Voltage reference
+    CTRLA: byte;  //Control A
+    CTRLB: byte;  //Control B
+  const
+    // VREF_AC0REFSEL
+    AC0REFSELmask = $07;
+    AC0REFSEL_1V024 = $00;
+    AC0REFSEL_2V048 = $01;
+    AC0REFSEL_2V5 = $02;
+    AC0REFSEL_4V096 = $03;
+    AC0REFSEL_AVDD = $07;
+    // AC0 DACREF reference enable
+    AC0REFENbm = $01;
+    // ADC0 reference enable
+    ADC0REFENbm = $02;
+    // NVM reference enable
+    NVMREFENbm = $04;
+  end;
+
+  TWDT = object //Watch-Dog Timer
+    CTRLA: byte;  //Control A
+    STATUS: byte;  //Status
+  const
+    // WDT_PERIOD
+    PERIODmask = $0F;
+    PERIOD_OFF = $00;
+    PERIOD_8CLK = $01;
+    PERIOD_16CLK = $02;
+    PERIOD_32CLK = $03;
+    PERIOD_64CLK = $04;
+    PERIOD_128CLK = $05;
+    PERIOD_256CLK = $06;
+    PERIOD_512CLK = $07;
+    PERIOD_1KCLK = $08;
+    PERIOD_2KCLK = $09;
+    PERIOD_4KCLK = $0A;
+    PERIOD_8KCLK = $0B;
+    // WDT_WINDOW
+    WINDOWmask = $F0;
+    WINDOW_OFF = $00;
+    WINDOW_8CLK = $10;
+    WINDOW_16CLK = $20;
+    WINDOW_32CLK = $30;
+    WINDOW_64CLK = $40;
+    WINDOW_128CLK = $50;
+    WINDOW_256CLK = $60;
+    WINDOW_512CLK = $70;
+    WINDOW_1KCLK = $80;
+    WINDOW_2KCLK = $90;
+    WINDOW_4KCLK = $A0;
+    WINDOW_8KCLK = $B0;
+    // Lock enable
+    LOCKbm = $80;
+    // Syncronization busy
+    SYNCBUSYbm = $01;
+  end;
+
+
+const
+ Pin0idx = 0;  Pin0bm = 1;
+ Pin1idx = 1;  Pin1bm = 2;
+ Pin2idx = 2;  Pin2bm = 4;
+ Pin3idx = 3;  Pin3bm = 8;
+ Pin4idx = 4;  Pin4bm = 16;
+ Pin5idx = 5;  Pin5bm = 32;
+ Pin6idx = 6;  Pin6bm = 64;
+ Pin7idx = 7;  Pin7bm = 128;
+
+var
+  VPORTA: TVPORT absolute $0000;
+  VPORTB: TVPORT absolute $0004;
+  VPORTC: TVPORT absolute $0008;
+  GPIO: TGPIO absolute $001C;
+  CPU: TCPU absolute $0030;
+  RSTCTRL: TRSTCTRL absolute $0040;
+  SLPCTRL: TSLPCTRL absolute $0050;
+  CLKCTRL: TCLKCTRL absolute $0060;
+  BOD: TBOD absolute $0080;
+  VREF: TVREF absolute $00A0;
+  NVMBIST: TNVMBIST absolute $00C0;
+  WDT: TWDT absolute $0100;
+  CPUINT: TCPUINT absolute $0110;
+  CRCSCAN: TCRCSCAN absolute $0120;
+  RTC: TRTC absolute $0140;
+  EVSYS: TEVSYS absolute $0180;
+  CCL: TCCL absolute $01C0;
+  PORTA: TPORT absolute $0400;
+  PORTB: TPORT absolute $0420;
+  PORTC: TPORT absolute $0440;
+  PORTMUX: TPORTMUX absolute $05E0;
+  ADC0: TADC absolute $0600;
+  AC0: TAC absolute $0680;
+  USART0: TUSART absolute $0800;
+  USART1: TUSART absolute $0820;
+  TWI0: TTWI absolute $08A0;
+  SPI0: TSPI absolute $08C0;
+  TCA0: TTCA absolute $0A00;
+  TCB0: TTCB absolute $0A80;
+  TCB1: TTCB absolute $0A90;
+  SYSCFG: TSYSCFG absolute $0F00;
+  NVMCTRL: TNVMCTRL absolute $1000;
+  SIGROW: TSIGROW absolute $1100;
+  FUSE: TFUSE absolute $1280;
+  LOCKBIT: TLOCKBIT absolute $128A;
+  USERROW: TUSERROW absolute $1300;
+
+implementation
+
+{$i avrcommon.inc}
+
+procedure CRCSCAN_NMI_ISR; external name 'CRCSCAN_NMI_ISR'; // Interrupt 1 
+procedure BOD_VLM_ISR; external name 'BOD_VLM_ISR'; // Interrupt 2 
+procedure RTC_CNT_ISR; external name 'RTC_CNT_ISR'; // Interrupt 3 
+procedure RTC_PIT_ISR; external name 'RTC_PIT_ISR'; // Interrupt 4 
+procedure CCL_CCL_ISR; external name 'CCL_CCL_ISR'; // Interrupt 5 
+procedure PORTA_PORT_ISR; external name 'PORTA_PORT_ISR'; // Interrupt 6 
+procedure PORTB_PORT_ISR; external name 'PORTB_PORT_ISR'; // Interrupt 7 
+procedure TCA0_LUNF_ISR; external name 'TCA0_LUNF_ISR'; // Interrupt 8 
+//procedure TCA0_OVF_ISR; external name 'TCA0_OVF_ISR'; // Interrupt 8 
+procedure TCA0_HUNF_ISR; external name 'TCA0_HUNF_ISR'; // Interrupt 9 
+procedure TCA0_LCMP0_ISR; external name 'TCA0_LCMP0_ISR'; // Interrupt 10 
+//procedure TCA0_CMP0_ISR; external name 'TCA0_CMP0_ISR'; // Interrupt 10 
+procedure TCA0_CMP1_ISR; external name 'TCA0_CMP1_ISR'; // Interrupt 11 
+//procedure TCA0_LCMP1_ISR; external name 'TCA0_LCMP1_ISR'; // Interrupt 11 
+procedure TCA0_CMP2_ISR; external name 'TCA0_CMP2_ISR'; // Interrupt 12 
+//procedure TCA0_LCMP2_ISR; external name 'TCA0_LCMP2_ISR'; // Interrupt 12 
+procedure TCB0_INT_ISR; external name 'TCB0_INT_ISR'; // Interrupt 13 
+procedure TWI0_TWIS_ISR; external name 'TWI0_TWIS_ISR'; // Interrupt 14 
+procedure TWI0_TWIM_ISR; external name 'TWI0_TWIM_ISR'; // Interrupt 15 
+procedure SPI0_INT_ISR; external name 'SPI0_INT_ISR'; // Interrupt 16 
+procedure USART0_RXC_ISR; external name 'USART0_RXC_ISR'; // Interrupt 17 
+procedure USART0_DRE_ISR; external name 'USART0_DRE_ISR'; // Interrupt 18 
+procedure USART0_TXC_ISR; external name 'USART0_TXC_ISR'; // Interrupt 19 
+procedure AC0_AC_ISR; external name 'AC0_AC_ISR'; // Interrupt 20 
+procedure ADC0_ERROR_ISR; external name 'ADC0_ERROR_ISR'; // Interrupt 21 
+procedure ADC0_RESRDY_ISR; external name 'ADC0_RESRDY_ISR'; // Interrupt 22 
+procedure ADC0_SAMPRDY_ISR; external name 'ADC0_SAMPRDY_ISR'; // Interrupt 23 
+procedure PORTC_PORT_ISR; external name 'PORTC_PORT_ISR'; // Interrupt 24 
+procedure TCB1_INT_ISR; external name 'TCB1_INT_ISR'; // Interrupt 25 
+procedure USART1_RXC_ISR; external name 'USART1_RXC_ISR'; // Interrupt 26 
+procedure USART1_DRE_ISR; external name 'USART1_DRE_ISR'; // Interrupt 27 
+procedure USART1_TXC_ISR; external name 'USART1_TXC_ISR'; // Interrupt 28 
+procedure NVMCTRL_EE_ISR; external name 'NVMCTRL_EE_ISR'; // Interrupt 29 
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  jmp _start
+  jmp CRCSCAN_NMI_ISR
+  jmp BOD_VLM_ISR
+  jmp RTC_CNT_ISR
+  jmp RTC_PIT_ISR
+  jmp CCL_CCL_ISR
+  jmp PORTA_PORT_ISR
+  jmp PORTB_PORT_ISR
+  jmp TCA0_LUNF_ISR
+//  jmp TCA0_OVF_ISR
+  jmp TCA0_HUNF_ISR
+  jmp TCA0_LCMP0_ISR
+//  jmp TCA0_CMP0_ISR
+  jmp TCA0_CMP1_ISR
+//  jmp TCA0_LCMP1_ISR
+  jmp TCA0_CMP2_ISR
+//  jmp TCA0_LCMP2_ISR
+  jmp TCB0_INT_ISR
+  jmp TWI0_TWIS_ISR
+  jmp TWI0_TWIM_ISR
+  jmp SPI0_INT_ISR
+  jmp USART0_RXC_ISR
+  jmp USART0_DRE_ISR
+  jmp USART0_TXC_ISR
+  jmp AC0_AC_ISR
+  jmp ADC0_ERROR_ISR
+  jmp ADC0_RESRDY_ISR
+  jmp ADC0_SAMPRDY_ISR
+  jmp PORTC_PORT_ISR
+  jmp TCB1_INT_ISR
+  jmp USART1_RXC_ISR
+  jmp USART1_DRE_ISR
+  jmp USART1_TXC_ISR
+  jmp NVMCTRL_EE_ISR
+
+  {$i start.inc}
+
+  .weak CRCSCAN_NMI_ISR
+  .weak BOD_VLM_ISR
+  .weak RTC_CNT_ISR
+  .weak RTC_PIT_ISR
+  .weak CCL_CCL_ISR
+  .weak PORTA_PORT_ISR
+  .weak PORTB_PORT_ISR
+  .weak TCA0_LUNF_ISR
+//  .weak TCA0_OVF_ISR
+  .weak TCA0_HUNF_ISR
+  .weak TCA0_LCMP0_ISR
+//  .weak TCA0_CMP0_ISR
+  .weak TCA0_CMP1_ISR
+//  .weak TCA0_LCMP1_ISR
+  .weak TCA0_CMP2_ISR
+//  .weak TCA0_LCMP2_ISR
+  .weak TCB0_INT_ISR
+  .weak TWI0_TWIS_ISR
+  .weak TWI0_TWIM_ISR
+  .weak SPI0_INT_ISR
+  .weak USART0_RXC_ISR
+  .weak USART0_DRE_ISR
+  .weak USART0_TXC_ISR
+  .weak AC0_AC_ISR
+  .weak ADC0_ERROR_ISR
+  .weak ADC0_RESRDY_ISR
+  .weak ADC0_SAMPRDY_ISR
+  .weak PORTC_PORT_ISR
+  .weak TCB1_INT_ISR
+  .weak USART1_RXC_ISR
+  .weak USART1_DRE_ISR
+  .weak USART1_TXC_ISR
+  .weak NVMCTRL_EE_ISR
+
+  .set CRCSCAN_NMI_ISR, Default_IRQ_handler
+  .set BOD_VLM_ISR, Default_IRQ_handler
+  .set RTC_CNT_ISR, Default_IRQ_handler
+  .set RTC_PIT_ISR, Default_IRQ_handler
+  .set CCL_CCL_ISR, Default_IRQ_handler
+  .set PORTA_PORT_ISR, Default_IRQ_handler
+  .set PORTB_PORT_ISR, Default_IRQ_handler
+  .set TCA0_LUNF_ISR, Default_IRQ_handler
+//  .set TCA0_OVF_ISR, Default_IRQ_handler
+  .set TCA0_HUNF_ISR, Default_IRQ_handler
+  .set TCA0_LCMP0_ISR, Default_IRQ_handler
+//  .set TCA0_CMP0_ISR, Default_IRQ_handler
+  .set TCA0_CMP1_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP1_ISR, Default_IRQ_handler
+  .set TCA0_CMP2_ISR, Default_IRQ_handler
+//  .set TCA0_LCMP2_ISR, Default_IRQ_handler
+  .set TCB0_INT_ISR, Default_IRQ_handler
+  .set TWI0_TWIS_ISR, Default_IRQ_handler
+  .set TWI0_TWIM_ISR, Default_IRQ_handler
+  .set SPI0_INT_ISR, Default_IRQ_handler
+  .set USART0_RXC_ISR, Default_IRQ_handler
+  .set USART0_DRE_ISR, Default_IRQ_handler
+  .set USART0_TXC_ISR, Default_IRQ_handler
+  .set AC0_AC_ISR, Default_IRQ_handler
+  .set ADC0_ERROR_ISR, Default_IRQ_handler
+  .set ADC0_RESRDY_ISR, Default_IRQ_handler
+  .set ADC0_SAMPRDY_ISR, Default_IRQ_handler
+  .set PORTC_PORT_ISR, Default_IRQ_handler
+  .set TCB1_INT_ISR, Default_IRQ_handler
+  .set USART1_RXC_ISR, Default_IRQ_handler
+  .set USART1_DRE_ISR, Default_IRQ_handler
+  .set USART1_TXC_ISR, Default_IRQ_handler
+  .set NVMCTRL_EE_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/attiny441.pp

@@ -0,0 +1,669 @@
+unit ATtiny441;
+
+{$goto on}
+interface
+
+var
+  ADCSRB: byte absolute $24;  // ADC Control and Status Register B
+  ADCSRA: byte absolute $25;  // The ADC Control and Status register
+  ADC: word absolute $26;  // ADC Data Register  Bytes
+  ADCL: byte absolute $26;  // ADC Data Register  Bytes
+  ADCH: byte absolute $27;  // ADC Data Register  Bytes;
+  ADMUXB: byte absolute $28;  // The ADC multiplexer Selection Register B
+  ADMUXA: byte absolute $29;  // The ADC multiplexer Selection Register A
+  ACSR0A: byte absolute $2A;  // Analog Comparator 0 Control And Status Register A
+  ACSR0B: byte absolute $2B;  // Analog Comparator 0 Control And Status Register B
+  ACSR1A: byte absolute $2C;  // Analog Comparator 1 Control And Status Register A
+  ACSR1B: byte absolute $2D;  // Analog Comparator 1 Control And Status Register B
+  TIFR1: byte absolute $2E;  // Timer/Counter Interrupt Flag register
+  TIMSK1: byte absolute $2F;  // Timer/Counter1 Interrupt Mask Register
+  TIFR2: byte absolute $30;  // Timer/Counter Interrupt Flag register
+  TIMSK2: byte absolute $31;  // Timer/Counter2 Interrupt Mask Register
+  PCMSK0: byte absolute $32;  // Pin Change Enable Mask 0
+  GPIOR0: byte absolute $33;  // General Purpose I/O Register 0
+  GPIOR1: byte absolute $34;  // General Purpose I/O Register 1
+  GPIOR2: byte absolute $35;  // General Purpose I/O Register 2
+  PINB: byte absolute $36;  // Port B Data register
+  DDRB: byte absolute $37;  // Data Direction Register, Port B
+  PORTB: byte absolute $38;  // Input Pins, Port B
+  PINA: byte absolute $39;  // Port A Input Pins
+  DDRA: byte absolute $3A;  // Data Direction Register, Port A
+  PORTA: byte absolute $3B;  // Port A Data Register
+  EECR: byte absolute $3C;  // EEPROM Control Register
+  EEDR: byte absolute $3D;  // EEPROM Data Register
+  EEAR: word absolute $3E;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $3E;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $3F;  // EEPROM Address Register  Bytes;
+  PCMSK1: byte absolute $40;  // Pin Change Enable Mask 1
+  WDTCSR: byte absolute $41;  // Watchdog Timer Control and Status Register
+  TCCR1C: byte absolute $42;  // Timer/Counter1 Control Register C
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  ICR1: word absolute $44;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $44;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $45;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1B: word absolute $48;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $48;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $49;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1A: word absolute $4A;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $4A;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $4B;  // Timer/Counter1 Output Compare Register A  Bytes;
+  TCNT1: word absolute $4C;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $4C;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $4D;  // Timer/Counter1  Bytes;
+  TCCR1B: byte absolute $4E;  // Timer/Counter1 Control Register B
+  TCCR1A: byte absolute $4F;  // Timer/Counter1 Control Register A
+  TCCR0A: byte absolute $50;  // Timer/Counter  Control Register A
+  TCNT0: byte absolute $52;  // Timer/Counter0
+  TCCR0B: byte absolute $53;  // Timer/Counter Control Register B
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  OCR0A: byte absolute $56;  // Timer/Counter0 Output Compare Register A
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  TIFR0: byte absolute $58;  // Timer/Counter0 Interrupt Flag Register
+  TIMSK0: byte absolute $59;  // Timer/Counter Interrupt Mask Register
+  GIFR: byte absolute $5A;  // General Interrupt Flag register
+  GIMSK: byte absolute $5B;  // General Interrupt Mask Register
+  OCR0B: byte absolute $5C;  // Timer/Counter0 Output Compare Register B
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  DIDR0: byte absolute $60;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $61;  // Digital Input Disable Register 1
+  PUEB: byte absolute $62;  // Pull-up Enable Control Register
+  PUEA: byte absolute $63;  // Pull-up Enable Control Register
+  PORTCR: byte absolute $64;  // Port Control Register
+  REMAP: byte absolute $65;  // Remap Port Pins
+  TOCPMCOE: byte absolute $66;  // Timer Output Compare Pin Mux Channel Output Enable
+  TOCPMSA0: byte absolute $67;  // Timer Output Compare Pin Mux Selection 0
+  TOCPMSA1: byte absolute $68;  // Timer Output Compare Pin Mux Selection 1
+  PHDE: byte absolute $6A;  // Port High Drive Enable Register
+  PRR: byte absolute $70;  // Power Reduction Register
+  CCP: byte absolute $71;  // Configuration Change Protection
+  CLKCR: byte absolute $72;  // Clock Control Register
+  CLKPR: byte absolute $73;  // Clock Prescale Register
+  OSCCAL0: byte absolute $74;  // Oscillator Calibration Register 8MHz
+  OSCTCAL0A: byte absolute $75;  // Oscillator Temperature Calibration Register A
+  OSCTCAL0B: byte absolute $76;  // Oscillator Temperature Calibration Register B
+  OSCCAL1: byte absolute $77;  // Oscillator Calibration Register 32kHz
+  UDR0: byte absolute $80;  // USART I/O Data Register
+  UBRR0: word absolute $81;  // USART Baud Rate Register  Bytes
+  UBRR0L: byte absolute $81;  // USART Baud Rate Register  Bytes
+  UBRR0H: byte absolute $82;  // USART Baud Rate Register  Bytes;
+  UCSR0D: byte absolute $83;  // USART Control and Status Register D
+  UCSR0C: byte absolute $84;  // USART Control and Status Register C
+  UCSR0B: byte absolute $85;  // USART Control and Status Register B
+  UCSR0A: byte absolute $86;  // USART Control and Status Register A
+  UDR1: byte absolute $90;  // USART I/O Data Register
+  UBRR1: word absolute $91;  // USART Baud Rate Register  Bytes
+  UBRR1L: byte absolute $91;  // USART Baud Rate Register  Bytes
+  UBRR1H: byte absolute $92;  // USART Baud Rate Register  Bytes;
+  UCSR1D: byte absolute $93;  // USART Control and Status Register D
+  UCSR1C: byte absolute $94;  // USART Control and Status Register C
+  UCSR1B: byte absolute $95;  // USART Control and Status Register B
+  UCSR1A: byte absolute $96;  // USART Control and Status Register A
+  TWSD: byte absolute $A0;  // TWI Slave Data Register
+  TWSAM: byte absolute $A1;  // TWI Slave Address Mask Register
+  TWSA: byte absolute $A2;  // TWI Slave Address Register
+  TWSSRA: byte absolute $A3;  // TWI Slave Status Register A
+  TWSCRB: byte absolute $A4;  // TWI Slave Control Register B
+  TWSCRA: byte absolute $A5;  // TWI Slave Control Register A
+  SPDR: byte absolute $B0;  // SPI Data Register
+  SPSR: byte absolute $B1;  // SPI Status Register
+  SPCR: byte absolute $B2;  // SPI Control Register
+  ICR2: word absolute $C0;  // Timer/Counter2 Input Capture Register  Bytes
+  ICR2L: byte absolute $C0;  // Timer/Counter2 Input Capture Register  Bytes
+  ICR2H: byte absolute $C1;  // Timer/Counter2 Input Capture Register  Bytes;
+  OCR2B: word absolute $C2;  // Timer/Counter2 Output Compare Register B  Bytes
+  OCR2BL: byte absolute $C2;  // Timer/Counter2 Output Compare Register B  Bytes
+  OCR2BH: byte absolute $C3;  // Timer/Counter2 Output Compare Register B  Bytes;
+  OCR2A: word absolute $C4;  // Timer/Counter2 Output Compare Register A  Bytes
+  OCR2AL: byte absolute $C4;  // Timer/Counter2 Output Compare Register A  Bytes
+  OCR2AH: byte absolute $C5;  // Timer/Counter2 Output Compare Register A  Bytes;
+  TCNT2: word absolute $C6;  // Timer/Counter2  Bytes
+  TCNT2L: byte absolute $C6;  // Timer/Counter2  Bytes
+  TCNT2H: byte absolute $C7;  // Timer/Counter2  Bytes;
+  TCCR2C: byte absolute $C8;  // Timer/Counter2 Control Register C
+  TCCR2B: byte absolute $C9;  // Timer/Counter2 Control Register B
+  TCCR2A: byte absolute $CA;  // Timer/Counter2 Control Register A
+
+const
+  // ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Sources
+  ADTS1 = $01;  // ADC Auto Trigger Sources
+  ADTS2 = $02;  // ADC Auto Trigger Sources
+  ADLAR = $03;  
+  // The ADC Control and Status register
+  ADPS0 = $00;  // ADC Prescaler Select Bits
+  ADPS1 = $01;  // ADC Prescaler Select Bits
+  ADPS2 = $02;  // ADC Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC multiplexer Selection Register B
+  GSEL0 = $00;  // Gain Selection Bits
+  GSEL1 = $01;  // Gain Selection Bits
+  REFS0 = $05;  // Reference Selection Bits
+  REFS1 = $06;  // Reference Selection Bits
+  REFS2 = $07;  // Reference Selection Bits
+  // The ADC multiplexer Selection Register A
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  MUX5 = $05;  // Analog Channel and Gain Selection Bits
+  // Analog Comparator 0 Control And Status Register A
+  ACIS00 = $00;  // Analog Comparator 0 Interrupt Mode Select bits
+  ACIS01 = $01;  // Analog Comparator 0 Interrupt Mode Select bits
+  ACIC0 = $02;  
+  ACIE0 = $03;  
+  ACI0 = $04;  
+  ACO0 = $05;  
+  ACPMUX2 = $06;  
+  ACD0 = $07;  
+  // Analog Comparator 0 Control And Status Register B
+  ACPMUX0 = $00;  // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
+  ACPMUX1 = $01;  // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
+  ACNMUX0 = $02;  // Analog Comparator 0 Negative Input Multiplexer
+  ACNMUX1 = $03;  // Analog Comparator 0 Negative Input Multiplexer
+  ACOE0 = $04;  
+  HLEV0 = $06;  
+  HSEL0 = $07;  
+  // Analog Comparator 1 Control And Status Register A
+  ACIS10 = $00;  // Analog Comparator 1 Interrupt Mode Select bits
+  ACIS11 = $01;  // Analog Comparator 1 Interrupt Mode Select bits
+  ACIC1 = $02;  
+  ACIE1 = $03;  
+  ACI1 = $04;  
+  ACO1 = $05;  
+  ACBG1 = $06;  
+  ACD1 = $07;  
+  // Analog Comparator 1 Control And Status Register B
+  ACME1 = $02;  
+  ACOE1 = $04;  
+  HLEV1 = $06;  
+  HSEL1 = $07;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $05;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Flag register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  ICF2 = $05;  
+  // Timer/Counter2 Interrupt Mask Register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  ICIE2 = $05;  
+  // Pin Change Enable Mask 0
+  PCINT0 = $00;  
+  PCINT1 = $01;  
+  PCINT2 = $02;  
+  PCINT3 = $03;  
+  PCINT4 = $04;  
+  PCINT5 = $05;  
+  PCINT6 = $06;  
+  PCINT7 = $07;  
+  // Input Pins, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode Bits
+  EEPM1 = $05;  // EEPROM Programming Mode Bits
+  // Pin Change Enable Mask 1
+  PCINT8 = $00;  
+  PCINT9 = $01;  
+  PCINT10 = $02;  
+  PCINT11 = $03;  
+  // Watchdog Timer Control and Status Register
+  WDE = $03;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // General Timer/Counter Control Register
+  PSR = $00;  
+  TSM = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select bits
+  CS11 = $01;  // Clock Select bits
+  CS12 = $02;  // Clock Select bits
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Pulse Width Modulator Select Bits
+  WGM11 = $01;  // Pulse Width Modulator Select Bits
+  COM1B0 = $04;  // Compare Output Mode 1B, bits
+  COM1B1 = $05;  // Compare Output Mode 1B, bits
+  COM1A0 = $06;  // Compare Output Mode 1A, bits
+  COM1A1 = $07;  // Compare Output Mode 1A, bits
+  // Timer/Counter  Control Register A
+  WGM00 = $00;  // Waveform Generation Mode bits
+  WGM01 = $01;  // Waveform Generation Mode bits
+  COM0B0 = $04;  // Compare Match Output B Mode bits
+  COM0B1 = $05;  // Compare Match Output B Mode bits
+  COM0A0 = $06;  // Compare Match Output A Mode bits
+  COM0A1 = $07;  // Compare Match Output A Mode bits
+  // Timer/Counter Control Register B
+  CS00 = $00;  // Clock Select bits
+  CS01 = $01;  // Clock Select bits
+  CS02 = $02;  // Clock Select bits
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  // MCU Control Register
+  ISC00 = $00;  
+  ISC01 = $01;  
+  SM0 = $03;  // Sleep Mode Select Bits
+  SM1 = $04;  // Sleep Mode Select Bits
+  SE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  RFLB = $03;  
+  CTPB = $04;  
+  RSIG = $05;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // General Interrupt Flag register
+  PCIF0 = $04;  // Pin Change Interrupt Flags
+  PCIF1 = $05;  // Pin Change Interrupt Flags
+  INTF0 = $06;  
+  // General Interrupt Mask Register
+  PCIE0 = $04;  // Pin Change Interrupt Enables
+  PCIE1 = $05;  // Pin Change Interrupt Enables
+  INT0 = $06;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  ADC11D = $00;  
+  ADC10D = $01;  
+  ADC8D = $02;  
+  ADC9D = $03;  
+  // Port Control Register
+  BBMA = $00;  
+  BBMB = $01;  
+  // Remap Port Pins
+  U0MAP = $00;  
+  SPIMAP = $01;  
+  // Timer Output Compare Pin Mux Channel Output Enable
+  TOCC0OE = $00;  
+  TOCC1OE = $01;  
+  TOCC2OE = $02;  
+  TOCC3OE = $03;  
+  TOCC4OE = $04;  
+  TOCC5OE = $05;  
+  TOCC6OE = $06;  
+  TOCC7OE = $07;  
+  // Timer Output Compare Pin Mux Selection 0
+  TOCC0S0 = $00;  // Timer Output Compare Channel 0 Selection Bits
+  TOCC0S1 = $01;  // Timer Output Compare Channel 0 Selection Bits
+  TOCC1S0 = $02;  // Timer Output Compare Channel 1 Selection Bits
+  TOCC1S1 = $03;  // Timer Output Compare Channel 1 Selection Bits
+  TOCC2S0 = $04;  // Timer Output Compare Channel 2 Selection Bits
+  TOCC2S1 = $05;  // Timer Output Compare Channel 2 Selection Bits
+  TOCC3S0 = $06;  // Timer Output Compare Channel 3 Selection Bits
+  TOCC3S1 = $07;  // Timer Output Compare Channel 3 Selection Bits
+  // Timer Output Compare Pin Mux Selection 1
+  TOCC4S0 = $00;  // Timer Output Compare Channel 4 Selection Bits
+  TOCC4S1 = $01;  // Timer Output Compare Channel 4 Selection Bits
+  TOCC5S0 = $02;  // Timer Output Compare Channel 5 Selection Bits
+  TOCC5S1 = $03;  // Timer Output Compare Channel 5 Selection Bits
+  TOCC6S0 = $04;  // Timer Output Compare Channel 6 Selection Bits
+  TOCC6S1 = $05;  // Timer Output Compare Channel 6 Selection Bits
+  TOCC7S0 = $06;  // Timer Output Compare Channel 7 Selection Bits
+  TOCC7S1 = $07;  // Timer Output Compare Channel 7 Selection Bits
+  // Port High Drive Enable Register
+  PHDEA0 = $00;  // PortA High Drive Enable
+  PHDEA1 = $01;  // PortA High Drive Enable
+  // Power Reduction Register
+  PRADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRTIM2 = $03;  
+  PRSPI = $04;  
+  PRUSART0 = $05;  
+  PRUSART1 = $06;  
+  PRTWI = $07;  
+  // Clock Control Register
+  CKSEL0 = $00;  // Clock Select Bits
+  CKSEL1 = $01;  // Clock Select Bits
+  CKSEL2 = $02;  // Clock Select Bits
+  CKSEL3 = $03;  // Clock Select Bits
+  SUT = $04;  
+  CKOUTC = $05;  
+  CSTR = $06;  
+  OSCRDY = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  // USART Control and Status Register D
+  SFDE0 = $05;  
+  RXS0 = $06;  
+  RXSIE0 = $07;  
+  // USART Control and Status Register C
+  UCPOL0 = $00;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode Bits
+  UPM01 = $05;  // Parity Mode Bits
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART Control and Status Register D
+  SFDE1 = $05;  
+  RXS1 = $06;  
+  RXSIE1 = $07;  
+  // USART Control and Status Register C
+  UCPOL1 = $00;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode Bits
+  UPM11 = $05;  // Parity Mode Bits
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // USART Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // TWI Slave Data Register
+  TWSD0 = $00;  // TWI slave data bit
+  TWSD1 = $01;  // TWI slave data bit
+  TWSD2 = $02;  // TWI slave data bit
+  TWSD3 = $03;  // TWI slave data bit
+  TWSD4 = $04;  // TWI slave data bit
+  TWSD5 = $05;  // TWI slave data bit
+  TWSD6 = $06;  // TWI slave data bit
+  TWSD7 = $07;  // TWI slave data bit
+  // TWI Slave Address Mask Register
+  TWAE = $00;  
+  TWSAM1 = $01;  // TWI Address Mask Bits
+  TWSAM2 = $02;  // TWI Address Mask Bits
+  TWSAM3 = $03;  // TWI Address Mask Bits
+  TWSAM4 = $04;  // TWI Address Mask Bits
+  TWSAM5 = $05;  // TWI Address Mask Bits
+  TWSAM6 = $06;  // TWI Address Mask Bits
+  TWSAM7 = $07;  // TWI Address Mask Bits
+  // TWI Slave Status Register A
+  TWAS = $00;  
+  TWDIR = $01;  
+  TWBE = $02;  
+  TWC = $03;  
+  TWRA = $04;  
+  TWCH = $05;  
+  TWASIF = $06;  
+  TWDIF = $07;  
+  // TWI Slave Control Register B
+  TWCMD0 = $00;
+  TWCMD1 = $01;
+  TWAA = $02;  
+  TWHNM = $03;  
+  // TWI Slave Control Register A
+  TWSME = $00;  
+  TWPME = $01;  
+  TWSIE = $02;  
+  TWEN = $03;  
+  TWASIE = $04;  
+  TWDIE = $05;  
+  TWSHE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // Timer/Counter2 Control Register C
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select bits
+  CS21 = $01;  // Clock Select bits
+  CS22 = $02;  // Clock Select bits
+  ICES2 = $06;  
+  ICNC2 = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Pulse Width Modulator Select Bits
+  WGM21 = $01;  // Pulse Width Modulator Select Bits
+  COM2B0 = $04;  // Compare Output Mode 2B, bits
+  COM2B1 = $05;  // Compare Output Mode 2B, bits
+  COM2A0 = $06;  // Compare Output Mode 2A, bits
+  COM2A1 = $07;  // Compare Output Mode 2A, bits
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Time-out Interrupt
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 9 TimerCounter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 10 TimerCounter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Couner0 Overflow
+procedure ANA_COMP0_ISR; external name 'ANA_COMP0_ISR'; // Interrupt 12 Analog Comparator 0
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete
+procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 14 EEPROM Ready
+procedure ANA_COMP1_ISR; external name 'ANA_COMP1_ISR'; // Interrupt 15 Analog Comparator 1
+procedure TIMER2_CAPT_ISR; external name 'TIMER2_CAPT_ISR'; // Interrupt 16 Timer/Counter2 Capture Event
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 17 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 18 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 19 Timer/Counter2 Overflow
+procedure SPI_ISR; external name 'SPI_ISR'; // Interrupt 20 Serial Peripheral Interface
+procedure USART0_START_ISR; external name 'USART0_START_ISR'; // Interrupt 21 USART0, Start
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 22 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 23 USART0 Data Register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 24 USART0, Tx Complete
+procedure USART1_START_ISR; external name 'USART1_START_ISR'; // Interrupt 25 USART1, Start
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 26 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 27 USART1 Data Register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 28 USART1, Tx Complete
+procedure TWI_SLAVE_ISR; external name 'TWI_SLAVE_ISR'; // Interrupt 29 Two-wire Serial Interface
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp INT0_ISR
+  rjmp PCINT0_ISR
+  rjmp PCINT1_ISR
+  rjmp WDT_ISR
+  rjmp TIMER1_CAPT_ISR
+  rjmp TIMER1_COMPA_ISR
+  rjmp TIMER1_COMPB_ISR
+  rjmp TIMER1_OVF_ISR
+  rjmp TIMER0_COMPA_ISR
+  rjmp TIMER0_COMPB_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp ANA_COMP0_ISR
+  rjmp ADC_ISR
+  rjmp EE_RDY_ISR
+  rjmp ANA_COMP1_ISR
+  rjmp TIMER2_CAPT_ISR
+  rjmp TIMER2_COMPA_ISR
+  rjmp TIMER2_COMPB_ISR
+  rjmp TIMER2_OVF_ISR
+  rjmp SPI_ISR
+  rjmp USART0_START_ISR
+  rjmp USART0_RX_ISR
+  rjmp USART0_UDRE_ISR
+  rjmp USART0_TX_ISR
+  rjmp USART1_START_ISR
+  rjmp USART1_RX_ISR
+  rjmp USART1_UDRE_ISR
+  rjmp USART1_TX_ISR
+  rjmp TWI_SLAVE_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak ANA_COMP0_ISR
+  .weak ADC_ISR
+  .weak EE_RDY_ISR
+  .weak ANA_COMP1_ISR
+  .weak TIMER2_CAPT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak SPI_ISR
+  .weak USART0_START_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak USART1_START_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_SLAVE_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set ANA_COMP0_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_RDY_ISR, Default_IRQ_handler
+  .set ANA_COMP1_ISR, Default_IRQ_handler
+  .set TIMER2_CAPT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set SPI_ISR, Default_IRQ_handler
+  .set USART0_START_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set USART1_START_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_SLAVE_ISR, Default_IRQ_handler
+end;
+
+end.

rtl/embedded/avr/attiny841.pp

@@ -0,0 +1,669 @@
+unit ATtiny841;
+
+{$goto on}
+interface
+
+var
+  ADCSRB: byte absolute $24;  // ADC Control and Status Register B
+  ADCSRA: byte absolute $25;  // The ADC Control and Status register
+  ADC: word absolute $26;  // ADC Data Register  Bytes
+  ADCL: byte absolute $26;  // ADC Data Register  Bytes
+  ADCH: byte absolute $27;  // ADC Data Register  Bytes;
+  ADMUXB: byte absolute $28;  // The ADC multiplexer Selection Register B
+  ADMUXA: byte absolute $29;  // The ADC multiplexer Selection Register A
+  ACSR0A: byte absolute $2A;  // Analog Comparator 0 Control And Status Register A
+  ACSR0B: byte absolute $2B;  // Analog Comparator 0 Control And Status Register B
+  ACSR1A: byte absolute $2C;  // Analog Comparator 1 Control And Status Register A
+  ACSR1B: byte absolute $2D;  // Analog Comparator 1 Control And Status Register B
+  TIFR1: byte absolute $2E;  // Timer/Counter Interrupt Flag register
+  TIMSK1: byte absolute $2F;  // Timer/Counter1 Interrupt Mask Register
+  TIFR2: byte absolute $30;  // Timer/Counter Interrupt Flag register
+  TIMSK2: byte absolute $31;  // Timer/Counter2 Interrupt Mask Register
+  PCMSK0: byte absolute $32;  // Pin Change Enable Mask 0
+  GPIOR0: byte absolute $33;  // General Purpose I/O Register 0
+  GPIOR1: byte absolute $34;  // General Purpose I/O Register 1
+  GPIOR2: byte absolute $35;  // General Purpose I/O Register 2
+  PINB: byte absolute $36;  // Port B Data register
+  DDRB: byte absolute $37;  // Data Direction Register, Port B
+  PORTB: byte absolute $38;  // Input Pins, Port B
+  PINA: byte absolute $39;  // Port A Input Pins
+  DDRA: byte absolute $3A;  // Data Direction Register, Port A
+  PORTA: byte absolute $3B;  // Port A Data Register
+  EECR: byte absolute $3C;  // EEPROM Control Register
+  EEDR: byte absolute $3D;  // EEPROM Data Register
+  EEAR: word absolute $3E;  // EEPROM Address Register  Bytes
+  EEARL: byte absolute $3E;  // EEPROM Address Register  Bytes
+  EEARH: byte absolute $3F;  // EEPROM Address Register  Bytes;
+  PCMSK1: byte absolute $40;  // Pin Change Enable Mask 1
+  WDTCSR: byte absolute $41;  // Watchdog Timer Control and Status Register
+  TCCR1C: byte absolute $42;  // Timer/Counter1 Control Register C
+  GTCCR: byte absolute $43;  // General Timer/Counter Control Register
+  ICR1: word absolute $44;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1L: byte absolute $44;  // Timer/Counter1 Input Capture Register  Bytes
+  ICR1H: byte absolute $45;  // Timer/Counter1 Input Capture Register  Bytes;
+  OCR1B: word absolute $48;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BL: byte absolute $48;  // Timer/Counter1 Output Compare Register B  Bytes
+  OCR1BH: byte absolute $49;  // Timer/Counter1 Output Compare Register B  Bytes;
+  OCR1A: word absolute $4A;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AL: byte absolute $4A;  // Timer/Counter1 Output Compare Register A  Bytes
+  OCR1AH: byte absolute $4B;  // Timer/Counter1 Output Compare Register A  Bytes;
+  TCNT1: word absolute $4C;  // Timer/Counter1  Bytes
+  TCNT1L: byte absolute $4C;  // Timer/Counter1  Bytes
+  TCNT1H: byte absolute $4D;  // Timer/Counter1  Bytes;
+  TCCR1B: byte absolute $4E;  // Timer/Counter1 Control Register B
+  TCCR1A: byte absolute $4F;  // Timer/Counter1 Control Register A
+  TCCR0A: byte absolute $50;  // Timer/Counter  Control Register A
+  TCNT0: byte absolute $52;  // Timer/Counter0
+  TCCR0B: byte absolute $53;  // Timer/Counter Control Register B
+  MCUSR: byte absolute $54;  // MCU Status Register
+  MCUCR: byte absolute $55;  // MCU Control Register
+  OCR0A: byte absolute $56;  // Timer/Counter0 Output Compare Register A
+  SPMCSR: byte absolute $57;  // Store Program Memory Control and Status Register
+  TIFR0: byte absolute $58;  // Timer/Counter0 Interrupt Flag Register
+  TIMSK0: byte absolute $59;  // Timer/Counter Interrupt Mask Register
+  GIFR: byte absolute $5A;  // General Interrupt Flag register
+  GIMSK: byte absolute $5B;  // General Interrupt Mask Register
+  OCR0B: byte absolute $5C;  // Timer/Counter0 Output Compare Register B
+  SP: word absolute $5D;  // Stack Pointer 
+  SPL: byte absolute $5D;  // Stack Pointer 
+  SPH: byte absolute $5E;  // Stack Pointer ;
+  SREG: byte absolute $5F;  // Status Register
+  DIDR0: byte absolute $60;  // Digital Input Disable Register 0
+  DIDR1: byte absolute $61;  // Digital Input Disable Register 1
+  PUEB: byte absolute $62;  // Pull-up Enable Control Register
+  PUEA: byte absolute $63;  // Pull-up Enable Control Register
+  PORTCR: byte absolute $64;  // Port Control Register
+  REMAP: byte absolute $65;  // Remap Port Pins
+  TOCPMCOE: byte absolute $66;  // Timer Output Compare Pin Mux Channel Output Enable
+  TOCPMSA0: byte absolute $67;  // Timer Output Compare Pin Mux Selection 0
+  TOCPMSA1: byte absolute $68;  // Timer Output Compare Pin Mux Selection 1
+  PHDE: byte absolute $6A;  // Port High Drive Enable Register
+  PRR: byte absolute $70;  // Power Reduction Register
+  CCP: byte absolute $71;  // Configuration Change Protection
+  CLKCR: byte absolute $72;  // Clock Control Register
+  CLKPR: byte absolute $73;  // Clock Prescale Register
+  OSCCAL0: byte absolute $74;  // Oscillator Calibration Register 8MHz
+  OSCTCAL0A: byte absolute $75;  // Oscillator Temperature Calibration Register A
+  OSCTCAL0B: byte absolute $76;  // Oscillator Temperature Calibration Register B
+  OSCCAL1: byte absolute $77;  // Oscillator Calibration Register 32kHz
+  UDR0: byte absolute $80;  // USART I/O Data Register
+  UBRR0: word absolute $81;  // USART Baud Rate Register Bytes
+  UBRR0L: byte absolute $81;  // USART Baud Rate Register Bytes
+  UBRR0H: byte absolute $82;  // USART Baud Rate Register Bytes;
+  UCSR0D: byte absolute $83;  // USART Control and Status Register D
+  UCSR0C: byte absolute $84;  // USART Control and Status Register C
+  UCSR0B: byte absolute $85;  // USART Control and Status Register B
+  UCSR0A: byte absolute $86;  // USART Control and Status Register A
+  UDR1: byte absolute $90;  // USART I/O Data Register
+  UBRR1: word absolute $91;  // USART Baud Rate Register Bytes
+  UBRR1L: byte absolute $91;  // USART Baud Rate Register Bytes
+  UBRR1H: byte absolute $92;  // USART Baud Rate Register Bytes;
+  UCSR1D: byte absolute $93;  // USART Control and Status Register D
+  UCSR1C: byte absolute $94;  // USART Control and Status Register C
+  UCSR1B: byte absolute $95;  // USART Control and Status Register B
+  UCSR1A: byte absolute $96;  // USART Control and Status Register A
+  TWSD: byte absolute $A0;  // TWI Slave Data Register
+  TWSAM: byte absolute $A1;  // TWI Slave Address Mask Register
+  TWSA: byte absolute $A2;  // TWI Slave Address Register
+  TWSSRA: byte absolute $A3;  // TWI Slave Status Register A
+  TWSCRB: byte absolute $A4;  // TWI Slave Control Register B
+  TWSCRA: byte absolute $A5;  // TWI Slave Control Register A
+  SPDR: byte absolute $B0;  // SPI Data Register
+  SPSR: byte absolute $B1;  // SPI Status Register
+  SPCR: byte absolute $B2;  // SPI Control Register
+  ICR2: word absolute $C0;  // Timer/Counter2 Input Capture Register  Bytes
+  ICR2L: byte absolute $C0;  // Timer/Counter2 Input Capture Register  Bytes
+  ICR2H: byte absolute $C1;  // Timer/Counter2 Input Capture Register  Bytes;
+  OCR2B: word absolute $C2;  // Timer/Counter2 Output Compare Register B  Bytes
+  OCR2BL: byte absolute $C2;  // Timer/Counter2 Output Compare Register B  Bytes
+  OCR2BH: byte absolute $C3;  // Timer/Counter2 Output Compare Register B  Bytes;
+  OCR2A: word absolute $C4;  // Timer/Counter2 Output Compare Register A  Bytes
+  OCR2AL: byte absolute $C4;  // Timer/Counter2 Output Compare Register A  Bytes
+  OCR2AH: byte absolute $C5;  // Timer/Counter2 Output Compare Register A  Bytes;
+  TCNT2: word absolute $C6;  // Timer/Counter2  Bytes
+  TCNT2L: byte absolute $C6;  // Timer/Counter2  Bytes
+  TCNT2H: byte absolute $C7;  // Timer/Counter2  Bytes;
+  TCCR2C: byte absolute $C8;  // Timer/Counter2 Control Register C
+  TCCR2B: byte absolute $C9;  // Timer/Counter2 Control Register B
+  TCCR2A: byte absolute $CA;  // Timer/Counter2 Control Register A
+
+const
+  // ADC Control and Status Register B
+  ADTS0 = $00;  // ADC Auto Trigger Sources
+  ADTS1 = $01;  // ADC Auto Trigger Sources
+  ADTS2 = $02;  // ADC Auto Trigger Sources
+  ADLAR = $03;  
+  // The ADC Control and Status register
+  ADPS0 = $00;  // ADC Prescaler Select Bits
+  ADPS1 = $01;  // ADC Prescaler Select Bits
+  ADPS2 = $02;  // ADC Prescaler Select Bits
+  ADIE = $03;  
+  ADIF = $04;  
+  ADATE = $05;  
+  ADSC = $06;  
+  ADEN = $07;  
+  // The ADC multiplexer Selection Register B
+  GSEL0 = $00;  // Gain Selection Bits
+  GSEL1 = $01;  // Gain Selection Bits
+  REFS0 = $05;  // Reference Selection Bits
+  REFS1 = $06;  // Reference Selection Bits
+  REFS2 = $07;  // Reference Selection Bits
+  // The ADC multiplexer Selection Register A
+  MUX0 = $00;  // Analog Channel and Gain Selection Bits
+  MUX1 = $01;  // Analog Channel and Gain Selection Bits
+  MUX2 = $02;  // Analog Channel and Gain Selection Bits
+  MUX3 = $03;  // Analog Channel and Gain Selection Bits
+  MUX4 = $04;  // Analog Channel and Gain Selection Bits
+  MUX5 = $05;  // Analog Channel and Gain Selection Bits
+  // Analog Comparator 0 Control And Status Register A
+  ACIS00 = $00;  // Analog Comparator 0 Interrupt Mode Select bits
+  ACIS01 = $01;  // Analog Comparator 0 Interrupt Mode Select bits
+  ACIC0 = $02;  
+  ACIE0 = $03;  
+  ACI0 = $04;  
+  ACO0 = $05;  
+  ACPMUX2 = $06;  
+  ACD0 = $07;  
+  // Analog Comparator 0 Control And Status Register B
+  ACPMUX0 = $00;  // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
+  ACPMUX1 = $01;  // Analog Comparator 0 Positive Input Multiplexer Bits 1:0
+  ACNMUX0 = $02;  // Analog Comparator 0 Negative Input Multiplexer
+  ACNMUX1 = $03;  // Analog Comparator 0 Negative Input Multiplexer
+  ACOE0 = $04;  
+  HLEV0 = $06;  
+  HSEL0 = $07;  
+  // Analog Comparator 1 Control And Status Register A
+  ACIS10 = $00;  // Analog Comparator 1 Interrupt Mode Select bits
+  ACIS11 = $01;  // Analog Comparator 1 Interrupt Mode Select bits
+  ACIC1 = $02;  
+  ACIE1 = $03;  
+  ACI1 = $04;  
+  ACO1 = $05;  
+  ACBG1 = $06;  
+  ACD1 = $07;  
+  // Analog Comparator 1 Control And Status Register B
+  ACME1 = $02;  
+  ACOE1 = $04;  
+  HLEV1 = $06;  
+  HSEL1 = $07;  
+  // Timer/Counter Interrupt Flag register
+  TOV1 = $00;  
+  OCF1A = $01;  
+  OCF1B = $02;  
+  ICF1 = $05;  
+  // Timer/Counter1 Interrupt Mask Register
+  TOIE1 = $00;  
+  OCIE1A = $01;  
+  OCIE1B = $02;  
+  ICIE1 = $05;  
+  // Timer/Counter Interrupt Flag register
+  TOV2 = $00;  
+  OCF2A = $01;  
+  OCF2B = $02;  
+  ICF2 = $05;  
+  // Timer/Counter2 Interrupt Mask Register
+  TOIE2 = $00;  
+  OCIE2A = $01;  
+  OCIE2B = $02;  
+  ICIE2 = $05;  
+  // Pin Change Enable Mask 0
+  PCINT0 = $00;  
+  PCINT1 = $01;  
+  PCINT2 = $02;  
+  PCINT3 = $03;  
+  PCINT4 = $04;  
+  PCINT5 = $05;  
+  PCINT6 = $06;  
+  PCINT7 = $07;  
+  // Input Pins, Port B
+  PB0 = $00;  
+  PB1 = $01;  
+  PB2 = $02;  
+  PB3 = $03;  
+  // Port A Data Register
+  PA0 = $00;  
+  PA1 = $01;  
+  PA2 = $02;  
+  PA3 = $03;  
+  PA4 = $04;  
+  PA5 = $05;  
+  PA6 = $06;  
+  PA7 = $07;  
+  // EEPROM Control Register
+  EERE = $00;  
+  EEPE = $01;  
+  EEMPE = $02;  
+  EERIE = $03;  
+  EEPM0 = $04;  // EEPROM Programming Mode Bits
+  EEPM1 = $05;  // EEPROM Programming Mode Bits
+  // Pin Change Enable Mask 1
+  PCINT8 = $00;  
+  PCINT9 = $01;  
+  PCINT10 = $02;  
+  PCINT11 = $03;  
+  // Watchdog Timer Control and Status Register
+  WDE = $03;  
+  WDP0 = $00;  // Watchdog Timer Prescaler Bits
+  WDP1 = $01;  // Watchdog Timer Prescaler Bits
+  WDP2 = $02;  // Watchdog Timer Prescaler Bits
+  WDP3 = $05;  // Watchdog Timer Prescaler Bits
+  WDIE = $06;  
+  WDIF = $07;  
+  // Timer/Counter1 Control Register C
+  FOC1B = $06;  
+  FOC1A = $07;  
+  // General Timer/Counter Control Register
+  PSR = $00;  
+  TSM = $07;  
+  // Timer/Counter1 Control Register B
+  CS10 = $00;  // Clock Select bits
+  CS11 = $01;  // Clock Select bits
+  CS12 = $02;  // Clock Select bits
+  ICES1 = $06;  
+  ICNC1 = $07;  
+  // Timer/Counter1 Control Register A
+  WGM10 = $00;  // Pulse Width Modulator Select Bits
+  WGM11 = $01;  // Pulse Width Modulator Select Bits
+  COM1B0 = $04;  // Compare Output Mode 1B, bits
+  COM1B1 = $05;  // Compare Output Mode 1B, bits
+  COM1A0 = $06;  // Compare Output Mode 1A, bits
+  COM1A1 = $07;  // Compare Output Mode 1A, bits
+  // Timer/Counter  Control Register A
+  WGM00 = $00;  // Waveform Generation Mode bits
+  WGM01 = $01;  // Waveform Generation Mode bits
+  COM0B0 = $04;  // Compare Match Output B Mode bits
+  COM0B1 = $05;  // Compare Match Output B Mode bits
+  COM0A0 = $06;  // Compare Match Output A Mode bits
+  COM0A1 = $07;  // Compare Match Output A Mode bits
+  // Timer/Counter Control Register B
+  CS00 = $00;  // Clock Select bits
+  CS01 = $01;  // Clock Select bits
+  CS02 = $02;  // Clock Select bits
+  WGM02 = $03;  
+  FOC0B = $06;  
+  FOC0A = $07;  
+  // MCU Status Register
+  PORF = $00;  
+  EXTRF = $01;  
+  BORF = $02;  
+  WDRF = $03;  
+  // MCU Control Register
+  ISC00 = $00;  // Interrupt Sense Control 0 bits
+  ISC01 = $01;  // Interrupt Sense Control 0 bits
+  SM0 = $03;  // Sleep Mode Select Bits
+  SM1 = $04;  // Sleep Mode Select Bits
+  SE = $05;  
+  // Store Program Memory Control and Status Register
+  SPMEN = $00;  
+  PGERS = $01;  
+  PGWRT = $02;  
+  RFLB = $03;  
+  CTPB = $04;  
+  RSIG = $05;  
+  // Timer/Counter0 Interrupt Flag Register
+  TOV0 = $00;  
+  OCF0A = $01;  
+  OCF0B = $02;  
+  // Timer/Counter Interrupt Mask Register
+  TOIE0 = $00;  
+  OCIE0A = $01;  
+  OCIE0B = $02;  
+  // General Interrupt Flag register
+  PCIF0 = $04;  // Pin Change Interrupt Flags
+  PCIF1 = $05;  // Pin Change Interrupt Flags
+  INTF0 = $06;  
+  // General Interrupt Mask Register
+  PCIE0 = $04;  // Pin Change Interrupt Enables
+  PCIE1 = $05;  // Pin Change Interrupt Enables
+  INT0 = $06;  
+  // Status Register
+  C = $00;  
+  Z = $01;  
+  N = $02;  
+  V = $03;  
+  S = $04;  
+  H = $05;  
+  T = $06;  
+  I = $07;  
+  // Digital Input Disable Register 0
+  ADC0D = $00;  
+  ADC1D = $01;  
+  ADC2D = $02;  
+  ADC3D = $03;  
+  ADC4D = $04;  
+  ADC5D = $05;  
+  ADC6D = $06;  
+  ADC7D = $07;  
+  // Digital Input Disable Register 1
+  ADC11D = $00;  
+  ADC10D = $01;  
+  ADC8D = $02;  
+  ADC9D = $03;  
+  // Port Control Register
+  BBMA = $00;  
+  BBMB = $01;  
+  // Remap Port Pins
+  U0MAP = $00;  
+  SPIMAP = $01;  
+  // Timer Output Compare Pin Mux Channel Output Enable
+  TOCC0OE = $00;  
+  TOCC1OE = $01;  
+  TOCC2OE = $02;  
+  TOCC3OE = $03;  
+  TOCC4OE = $04;  
+  TOCC5OE = $05;  
+  TOCC6OE = $06;  
+  TOCC7OE = $07;  
+  // Timer Output Compare Pin Mux Selection 0
+  TOCC0S0 = $00;  // Timer Output Compare Channel 0 Selection Bits
+  TOCC0S1 = $01;  // Timer Output Compare Channel 0 Selection Bits
+  TOCC1S0 = $02;  // Timer Output Compare Channel 1 Selection Bits
+  TOCC1S1 = $03;  // Timer Output Compare Channel 1 Selection Bits
+  TOCC2S0 = $04;  // Timer Output Compare Channel 2 Selection Bits
+  TOCC2S1 = $05;  // Timer Output Compare Channel 2 Selection Bits
+  TOCC3S0 = $06;  // Timer Output Compare Channel 3 Selection Bits
+  TOCC3S1 = $07;  // Timer Output Compare Channel 3 Selection Bits
+  // Timer Output Compare Pin Mux Selection 1
+  TOCC4S0 = $00;  // Timer Output Compare Channel 4 Selection Bits
+  TOCC4S1 = $01;  // Timer Output Compare Channel 4 Selection Bits
+  TOCC5S0 = $02;  // Timer Output Compare Channel 5 Selection Bits
+  TOCC5S1 = $03;  // Timer Output Compare Channel 5 Selection Bits
+  TOCC6S0 = $04;  // Timer Output Compare Channel 6 Selection Bits
+  TOCC6S1 = $05;  // Timer Output Compare Channel 6 Selection Bits
+  TOCC7S0 = $06;  // Timer Output Compare Channel 7 Selection Bits
+  TOCC7S1 = $07;  // Timer Output Compare Channel 7 Selection Bits
+  // Port High Drive Enable Register
+  PHDEA0 = $00;  // PortA High Drive Enable
+  PHDEA1 = $01;  // PortA High Drive Enable
+  // Power Reduction Register
+  PRADC = $00;  
+  PRTIM0 = $01;  
+  PRTIM1 = $02;  
+  PRTIM2 = $03;  
+  PRSPI = $04;  
+  PRUSART0 = $05;  
+  PRUSART1 = $06;  
+  PRTWI = $07;  
+  // Clock Control Register
+  CKSEL0 = $00;  // Clock Select Bits
+  CKSEL1 = $01;  // Clock Select Bits
+  CKSEL2 = $02;  // Clock Select Bits
+  CKSEL3 = $03;  // Clock Select Bits
+  SUT = $04;  
+  CKOUTC = $05;  
+  CSTR = $06;  
+  OSCRDY = $07;  
+  // Clock Prescale Register
+  CLKPS0 = $00;  // Clock Prescaler Select Bits
+  CLKPS1 = $01;  // Clock Prescaler Select Bits
+  CLKPS2 = $02;  // Clock Prescaler Select Bits
+  CLKPS3 = $03;  // Clock Prescaler Select Bits
+  // USART Control and Status Register D
+  SFDE0 = $05;  
+  RXS0 = $06;  
+  RXSIE0 = $07;  
+  // USART Control and Status Register C
+  UCPOL0 = $00;  
+  UCSZ00 = $01;  // Character Size
+  UCSZ01 = $02;  // Character Size
+  USBS0 = $03;  
+  UPM00 = $04;  // Parity Mode Bits
+  UPM01 = $05;  // Parity Mode Bits
+  UMSEL00 = $06;  // USART Mode Select
+  UMSEL01 = $07;  // USART Mode Select
+  // USART Control and Status Register B
+  TXB80 = $00;  
+  RXB80 = $01;  
+  UCSZ02 = $02;  
+  TXEN0 = $03;  
+  RXEN0 = $04;  
+  UDRIE0 = $05;  
+  TXCIE0 = $06;  
+  RXCIE0 = $07;  
+  // USART Control and Status Register A
+  MPCM0 = $00;  
+  U2X0 = $01;  
+  UPE0 = $02;  
+  DOR0 = $03;  
+  FE0 = $04;  
+  UDRE0 = $05;  
+  TXC0 = $06;  
+  RXC0 = $07;  
+  // USART Control and Status Register D
+  SFDE1 = $05;  
+  RXS1 = $06;  
+  RXSIE1 = $07;  
+  // USART Control and Status Register C
+  UCPOL1 = $00;  
+  UCSZ10 = $01;  // Character Size
+  UCSZ11 = $02;  // Character Size
+  USBS1 = $03;  
+  UPM10 = $04;  // Parity Mode Bits
+  UPM11 = $05;  // Parity Mode Bits
+  UMSEL10 = $06;  // USART Mode Select
+  UMSEL11 = $07;  // USART Mode Select
+  // USART Control and Status Register B
+  TXB81 = $00;  
+  RXB81 = $01;  
+  UCSZ12 = $02;  
+  TXEN1 = $03;  
+  RXEN1 = $04;  
+  UDRIE1 = $05;  
+  TXCIE1 = $06;  
+  RXCIE1 = $07;  
+  // USART Control and Status Register A
+  MPCM1 = $00;  
+  U2X1 = $01;  
+  UPE1 = $02;  
+  DOR1 = $03;  
+  FE1 = $04;  
+  UDRE1 = $05;  
+  TXC1 = $06;  
+  RXC1 = $07;  
+  // TWI Slave Data Register
+  TWSD0 = $00;  // TWI slave data bit
+  TWSD1 = $01;  // TWI slave data bit
+  TWSD2 = $02;  // TWI slave data bit
+  TWSD3 = $03;  // TWI slave data bit
+  TWSD4 = $04;  // TWI slave data bit
+  TWSD5 = $05;  // TWI slave data bit
+  TWSD6 = $06;  // TWI slave data bit
+  TWSD7 = $07;  // TWI slave data bit
+  // TWI Slave Address Mask Register
+  TWAE = $00;  
+  TWSAM1 = $01;  // TWI Address Mask Bits
+  TWSAM2 = $02;  // TWI Address Mask Bits
+  TWSAM3 = $03;  // TWI Address Mask Bits
+  TWSAM4 = $04;  // TWI Address Mask Bits
+  TWSAM5 = $05;  // TWI Address Mask Bits
+  TWSAM6 = $06;  // TWI Address Mask Bits
+  TWSAM7 = $07;  // TWI Address Mask Bits
+  // TWI Slave Status Register A
+  TWAS = $00;  
+  TWDIR = $01;  
+  TWBE = $02;  
+  TWC = $03;  
+  TWRA = $04;  
+  TWCH = $05;  
+  TWASIF = $06;  
+  TWDIF = $07;  
+  // TWI Slave Control Register B
+  TWCMD0 = $00;
+  TWCMD1 = $01;
+  TWAA = $02;  
+  TWHNM = $03;  
+  // TWI Slave Control Register A
+  TWSME = $00;  
+  TWPME = $01;  
+  TWSIE = $02;  
+  TWEN = $03;  
+  TWASIE = $04;  
+  TWDIE = $05;  
+  TWSHE = $07;  
+  // SPI Status Register
+  SPI2X = $00;  
+  WCOL = $06;  
+  SPIF = $07;  
+  // SPI Control Register
+  SPR0 = $00;  // SPI Clock Rate Selects
+  SPR1 = $01;  // SPI Clock Rate Selects
+  CPHA = $02;  
+  CPOL = $03;  
+  MSTR = $04;  
+  DORD = $05;  
+  SPE = $06;  
+  SPIE = $07;  
+  // Timer/Counter2 Control Register C
+  FOC2B = $06;  
+  FOC2A = $07;  
+  // Timer/Counter2 Control Register B
+  CS20 = $00;  // Clock Select bits
+  CS21 = $01;  // Clock Select bits
+  CS22 = $02;  // Clock Select bits
+  ICES2 = $06;  
+  ICNC2 = $07;  
+  // Timer/Counter2 Control Register A
+  WGM20 = $00;  // Pulse Width Modulator Select Bits
+  WGM21 = $01;  // Pulse Width Modulator Select Bits
+  COM2B0 = $04;  // Compare Output Mode 2B, bits
+  COM2B1 = $05;  // Compare Output Mode 2B, bits
+  COM2A0 = $06;  // Compare Output Mode 2A, bits
+  COM2A1 = $07;  // Compare Output Mode 2A, bits
+
+
+implementation
+{$define RELBRANCHES}
+{$i avrcommon.inc}
+
+procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
+procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
+procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
+procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Time-out Interrupt
+procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Capture Event
+procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A
+procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B
+procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow
+procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 9 TimerCounter0 Compare Match A
+procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 10 TimerCounter0 Compare Match B
+procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Couner0 Overflow
+procedure ANA_COMP0_ISR; external name 'ANA_COMP0_ISR'; // Interrupt 12 Analog Comparator 0
+procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 13 ADC Conversion Complete
+procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 14 EEPROM Ready
+procedure ANA_COMP1_ISR; external name 'ANA_COMP1_ISR'; // Interrupt 15 Analog Comparator 1
+procedure TIMER2_CAPT_ISR; external name 'TIMER2_CAPT_ISR'; // Interrupt 16 Timer/Counter2 Capture Event
+procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 17 Timer/Counter2 Compare Match A
+procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 18 Timer/Counter2 Compare Match B
+procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 19 Timer/Counter2 Overflow
+procedure SPI_ISR; external name 'SPI_ISR'; // Interrupt 20 Serial Peripheral Interface
+procedure USART0_START_ISR; external name 'USART0_START_ISR'; // Interrupt 21 USART0, Start
+procedure USART0_RX_ISR; external name 'USART0_RX_ISR'; // Interrupt 22 USART0, Rx Complete
+procedure USART0_UDRE_ISR; external name 'USART0_UDRE_ISR'; // Interrupt 23 USART0 Data Register Empty
+procedure USART0_TX_ISR; external name 'USART0_TX_ISR'; // Interrupt 24 USART0, Tx Complete
+procedure USART1_START_ISR; external name 'USART1_START_ISR'; // Interrupt 25 USART1, Start
+procedure USART1_RX_ISR; external name 'USART1_RX_ISR'; // Interrupt 26 USART1, Rx Complete
+procedure USART1_UDRE_ISR; external name 'USART1_UDRE_ISR'; // Interrupt 27 USART1 Data Register Empty
+procedure USART1_TX_ISR; external name 'USART1_TX_ISR'; // Interrupt 28 USART1, Tx Complete
+procedure TWI_SLAVE_ISR; external name 'TWI_SLAVE_ISR'; // Interrupt 29 Two-wire Serial Interface
+
+procedure _FPC_start; assembler; nostackframe;
+label
+  _start;
+asm
+  .init
+  .globl _start
+
+  rjmp _start
+  rjmp INT0_ISR
+  rjmp PCINT0_ISR
+  rjmp PCINT1_ISR
+  rjmp WDT_ISR
+  rjmp TIMER1_CAPT_ISR
+  rjmp TIMER1_COMPA_ISR
+  rjmp TIMER1_COMPB_ISR
+  rjmp TIMER1_OVF_ISR
+  rjmp TIMER0_COMPA_ISR
+  rjmp TIMER0_COMPB_ISR
+  rjmp TIMER0_OVF_ISR
+  rjmp ANA_COMP0_ISR
+  rjmp ADC_ISR
+  rjmp EE_RDY_ISR
+  rjmp ANA_COMP1_ISR
+  rjmp TIMER2_CAPT_ISR
+  rjmp TIMER2_COMPA_ISR
+  rjmp TIMER2_COMPB_ISR
+  rjmp TIMER2_OVF_ISR
+  rjmp SPI_ISR
+  rjmp USART0_START_ISR
+  rjmp USART0_RX_ISR
+  rjmp USART0_UDRE_ISR
+  rjmp USART0_TX_ISR
+  rjmp USART1_START_ISR
+  rjmp USART1_RX_ISR
+  rjmp USART1_UDRE_ISR
+  rjmp USART1_TX_ISR
+  rjmp TWI_SLAVE_ISR
+
+  {$i start.inc}
+
+  .weak INT0_ISR
+  .weak PCINT0_ISR
+  .weak PCINT1_ISR
+  .weak WDT_ISR
+  .weak TIMER1_CAPT_ISR
+  .weak TIMER1_COMPA_ISR
+  .weak TIMER1_COMPB_ISR
+  .weak TIMER1_OVF_ISR
+  .weak TIMER0_COMPA_ISR
+  .weak TIMER0_COMPB_ISR
+  .weak TIMER0_OVF_ISR
+  .weak ANA_COMP0_ISR
+  .weak ADC_ISR
+  .weak EE_RDY_ISR
+  .weak ANA_COMP1_ISR
+  .weak TIMER2_CAPT_ISR
+  .weak TIMER2_COMPA_ISR
+  .weak TIMER2_COMPB_ISR
+  .weak TIMER2_OVF_ISR
+  .weak SPI_ISR
+  .weak USART0_START_ISR
+  .weak USART0_RX_ISR
+  .weak USART0_UDRE_ISR
+  .weak USART0_TX_ISR
+  .weak USART1_START_ISR
+  .weak USART1_RX_ISR
+  .weak USART1_UDRE_ISR
+  .weak USART1_TX_ISR
+  .weak TWI_SLAVE_ISR
+
+  .set INT0_ISR, Default_IRQ_handler
+  .set PCINT0_ISR, Default_IRQ_handler
+  .set PCINT1_ISR, Default_IRQ_handler
+  .set WDT_ISR, Default_IRQ_handler
+  .set TIMER1_CAPT_ISR, Default_IRQ_handler
+  .set TIMER1_COMPA_ISR, Default_IRQ_handler
+  .set TIMER1_COMPB_ISR, Default_IRQ_handler
+  .set TIMER1_OVF_ISR, Default_IRQ_handler
+  .set TIMER0_COMPA_ISR, Default_IRQ_handler
+  .set TIMER0_COMPB_ISR, Default_IRQ_handler
+  .set TIMER0_OVF_ISR, Default_IRQ_handler
+  .set ANA_COMP0_ISR, Default_IRQ_handler
+  .set ADC_ISR, Default_IRQ_handler
+  .set EE_RDY_ISR, Default_IRQ_handler
+  .set ANA_COMP1_ISR, Default_IRQ_handler
+  .set TIMER2_CAPT_ISR, Default_IRQ_handler
+  .set TIMER2_COMPA_ISR, Default_IRQ_handler
+  .set TIMER2_COMPB_ISR, Default_IRQ_handler
+  .set TIMER2_OVF_ISR, Default_IRQ_handler
+  .set SPI_ISR, Default_IRQ_handler
+  .set USART0_START_ISR, Default_IRQ_handler
+  .set USART0_RX_ISR, Default_IRQ_handler
+  .set USART0_UDRE_ISR, Default_IRQ_handler
+  .set USART0_TX_ISR, Default_IRQ_handler
+  .set USART1_START_ISR, Default_IRQ_handler
+  .set USART1_RX_ISR, Default_IRQ_handler
+  .set USART1_UDRE_ISR, Default_IRQ_handler
+  .set USART1_TX_ISR, Default_IRQ_handler
+  .set TWI_SLAVE_ISR, Default_IRQ_handler
+end;
+
+end.