* correct change information for some instructions where the change

    information cannot be modelled in x86ins.dat

compiler/x86/aasmcpu.pas

@@ -4747,6 +4747,29 @@ implementation
                 internalerror(200506055);
             end
           end
+        else if (opcode=VMOVHPD) or (opcode=VMOVHPS) or (opcode=VMOVLHPS) or (opcode=VMOVLPD) or (opcode=VMOVLPS) then
+          begin
+            if ops=2 then
+              case opnr of
+                0:
+                  result:=operand_read;
+                1:
+                  result:=operand_readwrite;
+                else
+                  internalerror(2024060101);
+              end
+            else if ops=3 then
+              case opnr of
+                0,1:
+                  result:=operand_read;
+                2:
+                  result:=operand_write;
+                else
+                  internalerror(̄2024060102);
+              end
+            else
+              internalerror(2024060103);
+          end
         { IMUL has 1, 2 and 3-operand forms }
         else if opcode=A_IMUL then
           begin

compiler/x86/x86ins.dat

@@ -4530,32 +4530,35 @@ ymmrm,ymmreg                         \333\362\364\370\1\x7F\101           AVX,SA
 (Ch_Wop3, Ch_Rop2, Ch_Rop1)
 xmmreg,xmmreg,xmmreg                      \350\362\370\1\x12\75\120                 AVX,SANDYBRIDGE
 
+; 2/3 operands cannot be modeled here, it is corrected in taicpu.spilling_get_operation_type
 [VMOVHPD]
 (Ch_All)
 mem64,xmmreg                              \350\352\361\362\370\1\x17\101            AVX,SANDYBRIDGE,T1S
 xmmreg,xmmreg,mem64                       \350\352\361\362\370\1\x16\75\120         AVX,SANDYBRIDGE,T1S
 
+; 2/3 operands cannot be modeled here, it is corrected in taicpu.spilling_get_operation_type
 [VMOVHPS]
 (Ch_All)
 mem64,xmmreg                              \350\362\370\1\x17\101                    AVX,SANDYBRIDGE,T2
 xmmreg,xmmreg,mem64                       \350\362\370\1\x16\75\120                 AVX,SANDYBRIDGE,T2
 
+; 2/3 operands cannot be modeled here, it is corrected in taicpu.spilling_get_operation_type
 [VMOVLHPS]
 (Ch_All)
 xmmreg,xmmreg,xmmreg                      \350\362\370\1\x16\75\120                 AVX,SANDYBRIDGE
 
+; 2/3 operands cannot be modeled here, it is corrected in taicpu.spilling_get_operation_type
 [VMOVLPD]
 (Ch_All)
 mem64,xmmreg                              \350\352\361\362\370\1\x13\101            AVX,SANDYBRIDGE,T1S
 xmmreg,xmmreg,mem64                       \350\352\361\362\370\1\x12\75\120         AVX,SANDYBRIDGE,T1S
 
-
+; 2/3 operands cannot be modeled here, it is corrected in taicpu.spilling_get_operation_type
 [VMOVLPS]
 (Ch_All)
 mem64,xmmreg                              \350\362\370\1\x13\101                    AVX,SANDYBRIDGE,T2
 xmmreg,xmmreg,mem64                       \350\362\370\1\x12\75\120                 AVX,SANDYBRIDGE,T2
 
-
 [VMOVMSKPD]
 (Ch_Wop2, Ch_Rop1)
 reg32,ymmreg                         \361\362\364\370\1\x50\110           AVX,SANDYBRIDGE