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@@ -0,0 +1,1521 @@
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+{
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+ $Id$
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+ Copyright (c) 2000-2002 by Florian Klaempfl and Jonas Maebe
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+
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+ Code generation for add nodes on the PowerPC
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program; if not, write to the Free Software
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+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+
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+ ****************************************************************************
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+}
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+unit nppcadd;
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+
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+{$i fpcdefs.inc}
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+
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+interface
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+
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+ uses
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+ node,nadd,cpubase,cginfo;
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+
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+ type
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+ tppcaddnode = class(taddnode)
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+ procedure pass_2;override;
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+ private
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+ procedure pass_left_and_right(var pushedfpu:boolean);
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+ function getresflags : tresflags;
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+{
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+ procedure left_must_be_reg(opsize:TOpSize;noswap:boolean);
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+ procedure emit_op_right_left(op:TAsmOp;opsize:TOpSize);
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+ procedure emit_generic_code(op:TAsmOp;opsize:TOpSize;unsigned,extra_not,mboverflow:boolean);
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+ procedure set_result_location(cmpop,unsigned:boolean);
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+}
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+ procedure second_addboolean; virtual; abstract;
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+ procedure second_addfloat; virtual; abstract;
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+ procedure second_addsmallset; virtual; abstract;
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+{$ifdef SUPPORT_MMX}
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+ procedure second_addmmx;
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+{$endif SUPPORT_MMX}
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+ procedure second_add64bit; virtual; abstract;
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+ end;
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+
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+ implementation
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+
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+ uses
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+ globtype,systems,
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+ cutils,verbose,globals,
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+ symconst,symdef,paramgr,
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+ aasmbase,aasmtai,aasmcpu,defbase,htypechk,
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+ cgbase,cpuinfo,pass_2,regvars,
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+ cpupara,
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+ ncon,nset,
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+ cga,ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32;
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+
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+{*****************************************************************************
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+ Helpers
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+*****************************************************************************}
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+
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+ procedure tppcaddnode.pass_left_and_right(var pushedfpu:boolean);
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+ var
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+ pushedregs : tmaybesave;
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+ begin
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+ { calculate the operator which is more difficult }
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+ firstcomplex(self);
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+
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+ { in case of constant put it to the left }
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+ if (left.nodetype=ordconstn) then
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+ swapleftright;
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+ secondpass(left);
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+
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+ { are too few registers free? }
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+ maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
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+ if location.loc=LOC_FPUREGISTER then
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+ pushedfpu:=maybe_pushfpu(exprasmlist,right.registersfpu,left.location)
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+ else
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+ pushedfpu:=false;
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+ secondpass(right);
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+ maybe_restore(exprasmlist,left.location,pushedregs);
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+ end;
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+
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+
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+ function tppcaddnode.getresflags : tresflags;
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+ begin
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+ if (left.resulttype.def.deftype <> floatdef) then
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+ result.cr := R_CR0
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+ else
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+ result.cr := R_CR1;
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+ case nodetype of
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+ equaln : result.flag:=F_EQ;
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+ unequaln : result.flag:=F_NE;
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+ else
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+ if nf_swaped in flags then
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+ case nodetype of
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+ ltn : result.flag:=F_GT;
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+ lten : result.flag:=F_GE;
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+ gtn : result.flag:=F_LT;
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+ gten : result.flag:=F_LE;
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+ end
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+ else
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+ case nodetype of
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+ ltn : result.flag:=F_LT;
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+ lten : result.flag:=F_LE;
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+ gtn : result.flag:=F_GT;
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+ gten : result.flag:=F_GE;
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+ end;
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+ end
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+ end;
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+
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+(*
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+ procedure tppcaddnode.left_must_be_reg(opsize:TOpSize;noswap:boolean);
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+ begin
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+ { left location is not a register? }
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+ if (left.location.loc<>LOC_REGISTER) then
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+ begin
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+ { if right is register then we can swap the locations }
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+ if (not noswap) and
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+ (right.location.loc=LOC_REGISTER) then
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+ begin
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+ location_swap(left.location,right.location);
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+ toggleflag(nf_swaped);
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+ end
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+ else
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+ begin
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+ { maybe we can reuse a constant register when the
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+ operation is a comparison that doesn't change the
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+ value of the register }
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+ location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
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+ end;
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+ end;
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+*)
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+
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+(*
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+ procedure tppcaddnode.emit_op_right_left(op:TAsmOp;opsize:TOpsize);
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+ begin
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+ { left must be a register }
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+ case right.location.loc of
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+ LOC_REGISTER,
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+ LOC_CREGISTER :
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(op,opsize,location.register,left.location.register,right.location.register));
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+ LOC_CONSTANT :
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+!!! exprasmlist.concat(taicpu.op_const_reg(op,opsize,right.location.value,left.location.register));
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+ else
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+ internalerror(200203232);
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+ end;
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+ end;
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+*)
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+
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+(*
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+ procedure tppcaddnode.set_result_location(cmpop,unsigned:boolean);
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+ begin
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+ if cmpop then
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+ begin
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+ location_reset(location,LOC_FLAGS,OS_NO);
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+ location.resflags:=getresflags(unsigned);
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+ end
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+ else
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+ location_copy(location,left.location);
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+ end;
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+
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+*)
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+
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+(*
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+ procedure tppcaddnode.emit_generic_code(op:TAsmOp;opsize:TOpSize;unsigned,extra_not,mboverflow:boolean);
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+ var
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+ power : longint;
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+ hl4 : tasmlabel;
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+ begin
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+ { at this point, left.location.loc should be LOC_REGISTER and right
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+ should be a constant or in a register }
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+ if (right.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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+ begin
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+ { right.location is a register }
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+ { when swapped another result register }
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+ if (nodetype=subn) and (nf_swaped in flags) then
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+ op := A_SUBF;
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+ { adapt for overflow checking if necessary }
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+ if (cs_check_overflow in aktlocalswitches) then
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+ case op of
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+ A_ADD, A_SUB, A_SUBF:
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+ // convert to ADDO, SUBO, SUBFO
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+ op := succ(succ(op));
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+ end;
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+ exprasmlist.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register);
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+ end
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+ else
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+ begin
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+ { right.location is a constant }
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+ if (right.location.loc <> LOC_CONSTANT) then
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+ internalerror(2002072401);
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+ if (nodetype=subn) and (nf_swaped in flags) then
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+ begin
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+ if extra_not then
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+ emit_reg(A_NOT,opsize,left.location.register);
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+ rg.getexplicitregisterint(exprasmlist,R_EDI);
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+ cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
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+ emit_reg_reg(op,opsize,left.location.register,R_EDI);
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+ emit_reg_reg(A_MOV,opsize,R_EDI,left.location.register);
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+ rg.ungetregisterint(exprasmlist,R_EDI);
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+ end
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+ else
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+ begin
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+ { Optimizations when right.location is a constant value }
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+ if (op=A_CMP) and
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+ (nodetype in [equaln,unequaln]) and
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+ (right.location.loc=LOC_CONSTANT) and
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+ (right.location.value=0) then
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+ begin
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+ emit_reg_reg(A_TEST,opsize,left.location.register,left.location.register);
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+ end
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+ else
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+ if (op=A_ADD) and
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+ (right.location.loc=LOC_CONSTANT) and
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+ (right.location.value=1) and
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+ not(cs_check_overflow in aktlocalswitches) then
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+ begin
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+ emit_reg(A_INC,opsize,left.location.register);
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+ end
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+ else
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+ if (op=A_SUB) and
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+ (right.location.loc=LOC_CONSTANT) and
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+ (right.location.value=1) and
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+ not(cs_check_overflow in aktlocalswitches) then
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+ begin
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+ emit_reg(A_DEC,opsize,left.location.register);
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+ end
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+ else
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+ if (op=A_IMUL) and
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+ (right.location.loc=LOC_CONSTANT) and
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+ (ispowerof2(right.location.value,power)) and
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+ not(cs_check_overflow in aktlocalswitches) then
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+ begin
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+ emit_const_reg(A_SHL,opsize,power,left.location.register);
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+ end
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+ else
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+ begin
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+ if extra_not then
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+ begin
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+ rg.getexplicitregisterint(exprasmlist,R_EDI);
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+ cg.a_load_loc_reg(exprasmlist,right.location,R_EDI);
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+ emit_reg(A_NOT,S_L,R_EDI);
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+ emit_reg_reg(A_AND,S_L,R_EDI,left.location.register);
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+ rg.ungetregisterint(exprasmlist,R_EDI);
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+ end
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+ else
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+ begin
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+ emit_op_right_left(op,opsize);
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+ end;
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+ end;
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+ end;
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+ end;
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+
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+ { only in case of overflow operations }
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+ { produce overflow code }
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+ { we must put it here directly, because sign of operation }
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+ { is in unsigned VAR!! }
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+ if mboverflow then
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+ begin
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+ if cs_check_overflow in aktlocalswitches then
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+ begin
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+ getlabel(hl4);
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+ if unsigned then
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+ emitjmp(C_NB,hl4)
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+ else
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+ emitjmp(C_NO,hl4);
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+ cg.a_call_name(exprasmlist,'FPC_OVERFLOW');
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+ cg.a_label(exprasmlist,hl4);
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+ end;
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+ end;
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+ end;
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+
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+*)
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+
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+{*****************************************************************************
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+ AddBoolean
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+*****************************************************************************}
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+
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+(*
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+ procedure ti386addnode.second_addboolean;
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+ var
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+ op : TAsmOp;
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+ opsize : TOpsize;
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+ cmpop,
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+ isjump : boolean;
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+ otl,ofl : tasmlabel;
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+ pushedregs : tmaybesave;
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+ begin
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+ { calculate the operator which is more difficult }
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+ firstcomplex(self);
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+
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+ cmpop:=false;
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+ if (torddef(left.resulttype.def).typ=bool8bit) or
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+ (torddef(right.resulttype.def).typ=bool8bit) then
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+ opsize:=S_B
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+ else
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+ if (torddef(left.resulttype.def).typ=bool16bit) or
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+ (torddef(right.resulttype.def).typ=bool16bit) then
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+ opsize:=S_W
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+ else
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+ opsize:=S_L;
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+
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+ if (cs_full_boolean_eval in aktlocalswitches) or
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+ (nodetype in [unequaln,ltn,lten,gtn,gten,equaln,xorn]) then
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+ begin
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+ if left.nodetype in [ordconstn,realconstn] then
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+ swapleftright;
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+
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+ isjump:=(left.location.loc=LOC_JUMP);
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+ if isjump then
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+ begin
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+ otl:=truelabel;
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+ getlabel(truelabel);
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+ ofl:=falselabel;
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+ getlabel(falselabel);
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+ end;
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+ secondpass(left);
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+ if left.location.loc in [LOC_FLAGS,LOC_JUMP] then
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+ location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],false);
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+ if isjump then
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+ begin
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+ truelabel:=otl;
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+ falselabel:=ofl;
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+ end;
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+
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+ maybe_save(exprasmlist,right.registers32,left.location,pushedregs);
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+ isjump:=(right.location.loc=LOC_JUMP);
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+ if isjump then
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+ begin
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+ otl:=truelabel;
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+ getlabel(truelabel);
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+ ofl:=falselabel;
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+ getlabel(falselabel);
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+ end;
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+ secondpass(right);
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+ maybe_restore(exprasmlist,left.location,pushedregs);
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+ if right.location.loc in [LOC_FLAGS,LOC_JUMP] then
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+ location_force_reg(exprasmlist,right.location,opsize_2_cgsize[opsize],false);
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+ if isjump then
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+ begin
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+ truelabel:=otl;
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+ falselabel:=ofl;
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+ end;
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+
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+ { left must be a register }
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+ left_must_be_reg(opsize,false);
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+ { compare the }
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+ case nodetype of
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+ ltn,lten,gtn,gten,
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+ equaln,unequaln :
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+ begin
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+ op:=A_CMP;
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+ cmpop:=true;
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+ end;
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+ xorn :
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+ op:=A_XOR;
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+ orn :
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+ op:=A_OR;
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+ andn :
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+ op:=A_AND;
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+ else
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+ internalerror(200203247);
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+ end;
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+ emit_op_right_left(op,opsize);
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+ location_freetemp(exprasmlist,right.location);
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+ location_release(exprasmlist,right.location);
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+ if cmpop then
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+ begin
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+ location_freetemp(exprasmlist,left.location);
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+ location_release(exprasmlist,left.location);
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+ end;
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+ set_result_location(cmpop,true);
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+ end
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+ else
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+ begin
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+ case nodetype of
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+ andn,
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+ orn :
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+ begin
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+ location_reset(location,LOC_JUMP,OS_NO);
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+ case nodetype of
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+ andn :
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+ begin
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+ otl:=truelabel;
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+ getlabel(truelabel);
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+ secondpass(left);
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+ maketojumpbool(exprasmlist,left,lr_load_regvars);
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+ cg.a_label(exprasmlist,truelabel);
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+ truelabel:=otl;
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+ end;
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+ orn :
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+ begin
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+ ofl:=falselabel;
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+ getlabel(falselabel);
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+ secondpass(left);
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+ maketojumpbool(exprasmlist,left,lr_load_regvars);
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+ cg.a_label(exprasmlist,falselabel);
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+ falselabel:=ofl;
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+ end;
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+ else
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+ CGMessage(type_e_mismatch);
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+ end;
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+ secondpass(right);
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+ maketojumpbool(exprasmlist,right,lr_load_regvars);
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+ end;
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+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+*)
|
|
|
+
|
|
|
+{*****************************************************************************
|
|
|
+ AddFloat
|
|
|
+*****************************************************************************}
|
|
|
+
|
|
|
+(*
|
|
|
+ procedure ti386addnode.second_addfloat;
|
|
|
+ var
|
|
|
+ op : TAsmOp;
|
|
|
+ resflags : tresflags;
|
|
|
+ pushedfpu,
|
|
|
+ cmpop : boolean;
|
|
|
+ begin
|
|
|
+ pass_left_and_right(pushedfpu);
|
|
|
+
|
|
|
+ cmpop:=false;
|
|
|
+ case nodetype of
|
|
|
+ addn :
|
|
|
+ op:=A_FADDP;
|
|
|
+ muln :
|
|
|
+ op:=A_FMULP;
|
|
|
+ subn :
|
|
|
+ op:=A_FSUBP;
|
|
|
+ slashn :
|
|
|
+ op:=A_FDIVP;
|
|
|
+ ltn,lten,gtn,gten,
|
|
|
+ equaln,unequaln :
|
|
|
+ begin
|
|
|
+ op:=A_FCOMPP;
|
|
|
+ cmpop:=true;
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (right.location.loc<>LOC_FPUREGISTER) then
|
|
|
+ begin
|
|
|
+ cg.a_loadfpu_loc_reg(exprasmlist,
|
|
|
+ right.location,R_ST);
|
|
|
+ if (right.location.loc <> LOC_CFPUREGISTER) and
|
|
|
+ pushedfpu then
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ if (left.location.loc<>LOC_FPUREGISTER) then
|
|
|
+ begin
|
|
|
+ cg.a_loadfpu_loc_reg(exprasmlist,left.location,R_ST);
|
|
|
+ if (left.location.loc <> LOC_CFPUREGISTER) and
|
|
|
+ pushedfpu then
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { left was on the stack => swap }
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { releases the right reference }
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end
|
|
|
+ { the nominator in st0 }
|
|
|
+ else if (left.location.loc<>LOC_FPUREGISTER) then
|
|
|
+ begin
|
|
|
+ cg.a_loadfpu_loc_reg(exprasmlist,left.location,R_ST);
|
|
|
+ if (left.location.loc <> LOC_CFPUREGISTER) and
|
|
|
+ pushedfpu then
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { fpu operands are always in the wrong order on the stack }
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { releases the left reference }
|
|
|
+ if (left.location.loc in [LOC_CREFERENCE,LOC_REFERENCE]) then
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+
|
|
|
+ { if we swaped the tree nodes, then use the reverse operator }
|
|
|
+ if nf_swaped in flags then
|
|
|
+ begin
|
|
|
+ if (nodetype=slashn) then
|
|
|
+ op:=A_FDIVRP
|
|
|
+ else if (nodetype=subn) then
|
|
|
+ op:=A_FSUBRP;
|
|
|
+ end;
|
|
|
+ { to avoid the pentium bug
|
|
|
+ if (op=FDIVP) and (opt_processors=pentium) then
|
|
|
+ cg.a_call_name(exprasmlist,'EMUL_FDIVP')
|
|
|
+ else
|
|
|
+ }
|
|
|
+ { the Intel assemblers want operands }
|
|
|
+ if op<>A_FCOMPP then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(op,S_NO,R_ST,R_ST1);
|
|
|
+ dec(trgcpu(rg).fpuvaroffset);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ emit_none(op,S_NO);
|
|
|
+ dec(trgcpu(rg).fpuvaroffset,2);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { on comparison load flags }
|
|
|
+ if cmpop then
|
|
|
+ begin
|
|
|
+ if not(R_EAX in rg.unusedregsint) then
|
|
|
+ begin
|
|
|
+ rg.getexplicitregisterint(exprasmlist,R_EDI);
|
|
|
+ emit_reg_reg(A_MOV,S_L,R_EAX,R_EDI);
|
|
|
+ end;
|
|
|
+ emit_reg(A_FNSTSW,S_NO,R_AX);
|
|
|
+ emit_none(A_SAHF,S_NO);
|
|
|
+ if not(R_EAX in rg.unusedregsint) then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_MOV,S_L,R_EDI,R_EAX);
|
|
|
+ rg.ungetregisterint(exprasmlist,R_EDI);
|
|
|
+ end;
|
|
|
+ if nf_swaped in flags then
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ equaln : resflags:=F_E;
|
|
|
+ unequaln : resflags:=F_NE;
|
|
|
+ ltn : resflags:=F_A;
|
|
|
+ lten : resflags:=F_AE;
|
|
|
+ gtn : resflags:=F_B;
|
|
|
+ gten : resflags:=F_BE;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ equaln : resflags:=F_E;
|
|
|
+ unequaln : resflags:=F_NE;
|
|
|
+ ltn : resflags:=F_B;
|
|
|
+ lten : resflags:=F_BE;
|
|
|
+ gtn : resflags:=F_A;
|
|
|
+ gten : resflags:=F_AE;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ location_reset(location,LOC_FLAGS,OS_NO);
|
|
|
+ location.resflags:=resflags;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
|
|
|
+ location.register:=R_ST;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+*)
|
|
|
+
|
|
|
+{*****************************************************************************
|
|
|
+ AddSmallSet
|
|
|
+*****************************************************************************}
|
|
|
+
|
|
|
+(*
|
|
|
+ procedure ti386addnode.second_addsmallset;
|
|
|
+ var
|
|
|
+ opsize : TOpSize;
|
|
|
+ op : TAsmOp;
|
|
|
+ cmpop,
|
|
|
+ pushedfpu,
|
|
|
+ extra_not,
|
|
|
+ noswap : boolean;
|
|
|
+ begin
|
|
|
+ pass_left_and_right(pushedfpu);
|
|
|
+
|
|
|
+ { when a setdef is passed, it has to be a smallset }
|
|
|
+ if ((left.resulttype.def.deftype=setdef) and
|
|
|
+ (tsetdef(left.resulttype.def).settype<>smallset)) or
|
|
|
+ ((right.resulttype.def.deftype=setdef) and
|
|
|
+ (tsetdef(right.resulttype.def).settype<>smallset)) then
|
|
|
+ internalerror(200203301);
|
|
|
+
|
|
|
+ cmpop:=false;
|
|
|
+ noswap:=false;
|
|
|
+ extra_not:=false;
|
|
|
+ opsize:=S_L;
|
|
|
+ case nodetype of
|
|
|
+ addn :
|
|
|
+ begin
|
|
|
+ { this is a really ugly hack!!!!!!!!!! }
|
|
|
+ { this could be done later using EDI }
|
|
|
+ { as it is done for subn }
|
|
|
+ { instead of two registers!!!! }
|
|
|
+ { adding elements is not commutative }
|
|
|
+ if (nf_swaped in flags) and (left.nodetype=setelementn) then
|
|
|
+ swapleftright;
|
|
|
+ { are we adding set elements ? }
|
|
|
+ if right.nodetype=setelementn then
|
|
|
+ begin
|
|
|
+ { no range support for smallsets! }
|
|
|
+ if assigned(tsetelementnode(right).right) then
|
|
|
+ internalerror(43244);
|
|
|
+ { bts requires both elements to be registers }
|
|
|
+ location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],false);
|
|
|
+ location_force_reg(exprasmlist,right.location,opsize_2_cgsize[opsize],true);
|
|
|
+ op:=A_BTS;
|
|
|
+ noswap:=true;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ op:=A_OR;
|
|
|
+ end;
|
|
|
+ symdifn :
|
|
|
+ op:=A_XOR;
|
|
|
+ muln :
|
|
|
+ op:=A_AND;
|
|
|
+ subn :
|
|
|
+ begin
|
|
|
+ op:=A_AND;
|
|
|
+ if (not(nf_swaped in flags)) then
|
|
|
+ if (right.location.loc=LOC_CONSTANT) then
|
|
|
+ right.location.value := not(right.location.value)
|
|
|
+ else
|
|
|
+ op := A_ANDC
|
|
|
+ else
|
|
|
+ if (left.location.loc=LOC_CONSTANT) then
|
|
|
+ left.location.value := not(left.location.value)
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ swapleftright;
|
|
|
+ op := A_ANDC;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ equaln,
|
|
|
+ unequaln :
|
|
|
+ begin
|
|
|
+ op:=A_CMP;
|
|
|
+ cmpop:=true;
|
|
|
+ end;
|
|
|
+ lten,gten:
|
|
|
+ begin
|
|
|
+ If (not(nf_swaped in flags) and
|
|
|
+ (nodetype = lten)) or
|
|
|
+ ((nf_swaped in flags) and
|
|
|
+ (nodetype = gten)) then
|
|
|
+ swapleftright;
|
|
|
+ location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],true);
|
|
|
+ emit_op_right_left(A_AND,opsize);
|
|
|
+ op:=A_CMP;
|
|
|
+ cmpop:=true;
|
|
|
+ { warning: ugly hack, we need a JE so change the node to equaln }
|
|
|
+ nodetype:=equaln;
|
|
|
+ end;
|
|
|
+ xorn :
|
|
|
+ op:=A_XOR;
|
|
|
+ orn :
|
|
|
+ op:=A_OR;
|
|
|
+ andn :
|
|
|
+ op:=A_AND;
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { no < or > support for sets }
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ { left must be a register }
|
|
|
+ left_must_be_reg(opsize,noswap);
|
|
|
+ emit_generic_code(op,opsize,true,extra_not,false);
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ if cmpop then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+ end;
|
|
|
+ set_result_location(cmpop,true);
|
|
|
+ end;
|
|
|
+*)
|
|
|
+
|
|
|
+{*****************************************************************************
|
|
|
+ Add64bit
|
|
|
+*****************************************************************************}
|
|
|
+
|
|
|
+(*
|
|
|
+ procedure ti386addnode.second_add64bit;
|
|
|
+ var
|
|
|
+ op : TOpCG;
|
|
|
+ op1,op2 : TAsmOp;
|
|
|
+ opsize : TOpSize;
|
|
|
+ hregister,
|
|
|
+ hregister2 : tregister;
|
|
|
+ href : treference;
|
|
|
+ hl4 : tasmlabel;
|
|
|
+ pushedfpu,
|
|
|
+ mboverflow,
|
|
|
+ cmpop,
|
|
|
+ unsigned : boolean;
|
|
|
+
|
|
|
+ procedure firstjmp64bitcmp;
|
|
|
+
|
|
|
+ var
|
|
|
+ oldnodetype : tnodetype;
|
|
|
+
|
|
|
+ begin
|
|
|
+ load_all_regvars(exprasmlist);
|
|
|
+ { the jump the sequence is a little bit hairy }
|
|
|
+ case nodetype of
|
|
|
+ ltn,gtn:
|
|
|
+ begin
|
|
|
+ emitjmp(flags_to_cond(getresflags(unsigned)),truelabel);
|
|
|
+ { cheat a little bit for the negative test }
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ emitjmp(flags_to_cond(getresflags(unsigned)),falselabel);
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end;
|
|
|
+ lten,gten:
|
|
|
+ begin
|
|
|
+ oldnodetype:=nodetype;
|
|
|
+ if nodetype=lten then
|
|
|
+ nodetype:=ltn
|
|
|
+ else
|
|
|
+ nodetype:=gtn;
|
|
|
+ emitjmp(flags_to_cond(getresflags(unsigned)),truelabel);
|
|
|
+ { cheat for the negative test }
|
|
|
+ if nodetype=ltn then
|
|
|
+ nodetype:=gtn
|
|
|
+ else
|
|
|
+ nodetype:=ltn;
|
|
|
+ emitjmp(flags_to_cond(getresflags(unsigned)),falselabel);
|
|
|
+ nodetype:=oldnodetype;
|
|
|
+ end;
|
|
|
+ equaln:
|
|
|
+ emitjmp(C_NE,falselabel);
|
|
|
+ unequaln:
|
|
|
+ emitjmp(C_NE,truelabel);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
+ procedure secondjmp64bitcmp;
|
|
|
+
|
|
|
+ begin
|
|
|
+ { the jump the sequence is a little bit hairy }
|
|
|
+ case nodetype of
|
|
|
+ ltn,gtn,lten,gten:
|
|
|
+ begin
|
|
|
+ { the comparisaion of the low dword have to be }
|
|
|
+ { always unsigned! }
|
|
|
+ emitjmp(flags_to_cond(getresflags(true)),truelabel);
|
|
|
+ cg.a_jmp_always(exprasmlist,falselabel);
|
|
|
+ end;
|
|
|
+ equaln:
|
|
|
+ begin
|
|
|
+ emitjmp(C_NE,falselabel);
|
|
|
+ cg.a_jmp_always(exprasmlist,truelabel);
|
|
|
+ end;
|
|
|
+ unequaln:
|
|
|
+ begin
|
|
|
+ emitjmp(C_NE,truelabel);
|
|
|
+ cg.a_jmp_always(exprasmlist,falselabel);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ begin
|
|
|
+ firstcomplex(self);
|
|
|
+
|
|
|
+ pass_left_and_right(pushedfpu);
|
|
|
+
|
|
|
+ op1:=A_NONE;
|
|
|
+ op2:=A_NONE;
|
|
|
+ mboverflow:=false;
|
|
|
+ cmpop:=false;
|
|
|
+ opsize:=S_L;
|
|
|
+ unsigned:=((left.resulttype.def.deftype=orddef) and
|
|
|
+ (torddef(left.resulttype.def).typ=u64bit)) or
|
|
|
+ ((right.resulttype.def.deftype=orddef) and
|
|
|
+ (torddef(right.resulttype.def).typ=u64bit));
|
|
|
+ case nodetype of
|
|
|
+ addn :
|
|
|
+ begin
|
|
|
+ op:=OP_ADD;
|
|
|
+ mboverflow:=true;
|
|
|
+ end;
|
|
|
+ subn :
|
|
|
+ begin
|
|
|
+ op:=OP_SUB;
|
|
|
+ op1:=A_SUB;
|
|
|
+ op2:=A_SBB;
|
|
|
+ mboverflow:=true;
|
|
|
+ end;
|
|
|
+ ltn,lten,
|
|
|
+ gtn,gten,
|
|
|
+ equaln,unequaln:
|
|
|
+ begin
|
|
|
+ op:=OP_NONE;
|
|
|
+ cmpop:=true;
|
|
|
+ end;
|
|
|
+ xorn:
|
|
|
+ op:=OP_XOR;
|
|
|
+ orn:
|
|
|
+ op:=OP_OR;
|
|
|
+ andn:
|
|
|
+ op:=OP_AND;
|
|
|
+ muln:
|
|
|
+ begin
|
|
|
+ { should be handled in pass_1 (JM) }
|
|
|
+ internalerror(200109051);
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { left and right no register? }
|
|
|
+ { then one must be demanded }
|
|
|
+ if (left.location.loc<>LOC_REGISTER) then
|
|
|
+ begin
|
|
|
+ if (right.location.loc<>LOC_REGISTER) then
|
|
|
+ begin
|
|
|
+ { we can reuse a CREGISTER for comparison }
|
|
|
+ if not((left.location.loc=LOC_CREGISTER) and cmpop) then
|
|
|
+ begin
|
|
|
+ if (left.location.loc<>LOC_CREGISTER) then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+ end;
|
|
|
+ hregister:=rg.getregisterint(exprasmlist);
|
|
|
+ hregister2:=rg.getregisterint(exprasmlist);
|
|
|
+ cg64.a_load64_loc_reg(exprasmlist,left.location,joinreg64(hregister,hregister2));
|
|
|
+ location_reset(left.location,LOC_REGISTER,OS_64);
|
|
|
+ left.location.registerlow:=hregister;
|
|
|
+ left.location.registerhigh:=hregister2;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ location_swap(left.location,right.location);
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { at this point, left.location.loc should be LOC_REGISTER }
|
|
|
+ if right.location.loc=LOC_REGISTER then
|
|
|
+ begin
|
|
|
+ { when swapped another result register }
|
|
|
+ if (nodetype=subn) and (nf_swaped in flags) then
|
|
|
+ begin
|
|
|
+ cg64.a_op64_reg_reg(exprasmlist,op,
|
|
|
+ left.location.register64,
|
|
|
+ right.location.register64);
|
|
|
+ location_swap(left.location,right.location);
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end
|
|
|
+ else if cmpop then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_CMP,S_L,right.location.registerhigh,left.location.registerhigh);
|
|
|
+ firstjmp64bitcmp;
|
|
|
+ emit_reg_reg(A_CMP,S_L,right.location.registerlow,left.location.registerlow);
|
|
|
+ secondjmp64bitcmp;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ cg64.a_op64_reg_reg(exprasmlist,op,
|
|
|
+ right.location.register64,
|
|
|
+ left.location.register64);
|
|
|
+ end;
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { right.location<>LOC_REGISTER }
|
|
|
+ if (nodetype=subn) and (nf_swaped in flags) then
|
|
|
+ begin
|
|
|
+ rg.getexplicitregisterint(exprasmlist,R_EDI);
|
|
|
+ cg64.a_load64low_loc_reg(exprasmlist,right.location,R_EDI);
|
|
|
+ emit_reg_reg(op1,opsize,left.location.registerlow,R_EDI);
|
|
|
+ emit_reg_reg(A_MOV,opsize,R_EDI,left.location.registerlow);
|
|
|
+ cg64.a_load64high_loc_reg(exprasmlist,right.location,R_EDI);
|
|
|
+ { the carry flag is still ok }
|
|
|
+ emit_reg_reg(op2,opsize,left.location.registerhigh,R_EDI);
|
|
|
+ emit_reg_reg(A_MOV,opsize,R_EDI,left.location.registerhigh);
|
|
|
+ rg.ungetregisterint(exprasmlist,R_EDI);
|
|
|
+ if right.location.loc<>LOC_CREGISTER then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else if cmpop then
|
|
|
+ begin
|
|
|
+ case right.location.loc of
|
|
|
+ LOC_CREGISTER :
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_CMP,S_L,right.location.registerhigh,left.location.registerhigh);
|
|
|
+ firstjmp64bitcmp;
|
|
|
+ emit_reg_reg(A_CMP,S_L,right.location.registerlow,left.location.registerlow);
|
|
|
+ secondjmp64bitcmp;
|
|
|
+ end;
|
|
|
+ LOC_CREFERENCE,
|
|
|
+ LOC_REFERENCE :
|
|
|
+ begin
|
|
|
+ href:=right.location.reference;
|
|
|
+ inc(href.offset,4);
|
|
|
+ emit_ref_reg(A_CMP,S_L,href,left.location.registerhigh);
|
|
|
+ firstjmp64bitcmp;
|
|
|
+ emit_ref_reg(A_CMP,S_L,right.location.reference,left.location.registerlow);
|
|
|
+ secondjmp64bitcmp;
|
|
|
+ cg.a_jmp_always(exprasmlist,falselabel);
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end;
|
|
|
+ LOC_CONSTANT :
|
|
|
+ begin
|
|
|
+ exprasmlist.concat(taicpu.op_const_reg(A_CMP,S_L,right.location.valuehigh,left.location.registerhigh));
|
|
|
+ firstjmp64bitcmp;
|
|
|
+ exprasmlist.concat(taicpu.op_const_reg(A_CMP,S_L,right.location.valuelow,left.location.registerlow));
|
|
|
+ secondjmp64bitcmp;
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ internalerror(200203282);
|
|
|
+ end;
|
|
|
+ end
|
|
|
+
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ cg64.a_op64_loc_reg(exprasmlist,op,right.location,
|
|
|
+ left.location.register64);
|
|
|
+ if (right.location.loc<>LOC_CREGISTER) then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (left.location.loc<>LOC_CREGISTER) and cmpop then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { only in case of overflow operations }
|
|
|
+ { produce overflow code }
|
|
|
+ { we must put it here directly, because sign of operation }
|
|
|
+ { is in unsigned VAR!! }
|
|
|
+ if mboverflow then
|
|
|
+ begin
|
|
|
+ if cs_check_overflow in aktlocalswitches then
|
|
|
+ begin
|
|
|
+ getlabel(hl4);
|
|
|
+ if unsigned then
|
|
|
+ emitjmp(C_NB,hl4)
|
|
|
+ else
|
|
|
+ emitjmp(C_NO,hl4);
|
|
|
+ cg.a_call_name(exprasmlist,'FPC_OVERFLOW');
|
|
|
+ cg.a_label(exprasmlist,hl4);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { we have LOC_JUMP as result }
|
|
|
+ if cmpop then
|
|
|
+ location_reset(location,LOC_JUMP,OS_NO)
|
|
|
+ else
|
|
|
+ location_copy(location,left.location);
|
|
|
+ end;
|
|
|
+*)
|
|
|
+
|
|
|
+
|
|
|
+{*****************************************************************************
|
|
|
+ AddMMX
|
|
|
+*****************************************************************************}
|
|
|
+
|
|
|
+{$ifdef SUPPORT_MMX}
|
|
|
+ procedure ti386addnode.second_addmmx;
|
|
|
+ var
|
|
|
+ op : TAsmOp;
|
|
|
+ pushedfpu,
|
|
|
+ cmpop : boolean;
|
|
|
+ mmxbase : tmmxtype;
|
|
|
+ hregister : tregister;
|
|
|
+ begin
|
|
|
+ pass_left_and_right(pushedfpu);
|
|
|
+
|
|
|
+ cmpop:=false;
|
|
|
+ mmxbase:=mmx_type(left.resulttype.def);
|
|
|
+ case nodetype of
|
|
|
+ addn :
|
|
|
+ begin
|
|
|
+ if (cs_mmx_saturation in aktlocalswitches) then
|
|
|
+ begin
|
|
|
+ case mmxbase of
|
|
|
+ mmxs8bit:
|
|
|
+ op:=A_PADDSB;
|
|
|
+ mmxu8bit:
|
|
|
+ op:=A_PADDUSB;
|
|
|
+ mmxs16bit,mmxfixed16:
|
|
|
+ op:=A_PADDSB;
|
|
|
+ mmxu16bit:
|
|
|
+ op:=A_PADDUSW;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ case mmxbase of
|
|
|
+ mmxs8bit,mmxu8bit:
|
|
|
+ op:=A_PADDB;
|
|
|
+ mmxs16bit,mmxu16bit,mmxfixed16:
|
|
|
+ op:=A_PADDW;
|
|
|
+ mmxs32bit,mmxu32bit:
|
|
|
+ op:=A_PADDD;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ muln :
|
|
|
+ begin
|
|
|
+ case mmxbase of
|
|
|
+ mmxs16bit,mmxu16bit:
|
|
|
+ op:=A_PMULLW;
|
|
|
+ mmxfixed16:
|
|
|
+ op:=A_PMULHW;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ subn :
|
|
|
+ begin
|
|
|
+ if (cs_mmx_saturation in aktlocalswitches) then
|
|
|
+ begin
|
|
|
+ case mmxbase of
|
|
|
+ mmxs8bit:
|
|
|
+ op:=A_PSUBSB;
|
|
|
+ mmxu8bit:
|
|
|
+ op:=A_PSUBUSB;
|
|
|
+ mmxs16bit,mmxfixed16:
|
|
|
+ op:=A_PSUBSB;
|
|
|
+ mmxu16bit:
|
|
|
+ op:=A_PSUBUSW;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ case mmxbase of
|
|
|
+ mmxs8bit,mmxu8bit:
|
|
|
+ op:=A_PSUBB;
|
|
|
+ mmxs16bit,mmxu16bit,mmxfixed16:
|
|
|
+ op:=A_PSUBW;
|
|
|
+ mmxs32bit,mmxu32bit:
|
|
|
+ op:=A_PSUBD;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ xorn:
|
|
|
+ op:=A_PXOR;
|
|
|
+ orn:
|
|
|
+ op:=A_POR;
|
|
|
+ andn:
|
|
|
+ op:=A_PAND;
|
|
|
+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+
|
|
|
+ { left and right no register? }
|
|
|
+ { then one must be demanded }
|
|
|
+ if (left.location.loc<>LOC_MMXREGISTER) then
|
|
|
+ begin
|
|
|
+ if (right.location.loc=LOC_MMXREGISTER) then
|
|
|
+ begin
|
|
|
+ location_swap(left.location,right.location);
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { register variable ? }
|
|
|
+ if (left.location.loc=LOC_CMMXREGISTER) then
|
|
|
+ begin
|
|
|
+ hregister:=rg.getregistermm(exprasmlist);
|
|
|
+ emit_reg_reg(A_MOVQ,S_NO,left.location.register,hregister);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if not(left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
|
|
|
+ internalerror(200203245);
|
|
|
+
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+
|
|
|
+ hregister:=rg.getregistermm(exprasmlist);
|
|
|
+ emit_ref_reg(A_MOVQ,S_NO,left.location.reference,hregister);
|
|
|
+ end;
|
|
|
+
|
|
|
+ location_reset(left.location,LOC_MMXREGISTER,OS_NO);
|
|
|
+ left.location.register:=hregister;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { at this point, left.location.loc should be LOC_MMXREGISTER }
|
|
|
+ if right.location.loc<>LOC_MMXREGISTER then
|
|
|
+ begin
|
|
|
+ if (nodetype=subn) and (nf_swaped in flags) then
|
|
|
+ begin
|
|
|
+ if right.location.loc=LOC_CMMXREGISTER then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_MOVQ,S_NO,right.location.register,R_MM7);
|
|
|
+ emit_reg_reg(op,S_NO,left.location.register,R_MM7);
|
|
|
+ emit_reg_reg(A_MOVQ,S_NO,R_MM7,left.location.register);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if not(left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
|
|
|
+ internalerror(200203247);
|
|
|
+ emit_ref_reg(A_MOVQ,S_NO,right.location.reference,R_MM7);
|
|
|
+ emit_reg_reg(op,S_NO,left.location.register,R_MM7);
|
|
|
+ emit_reg_reg(A_MOVQ,S_NO,R_MM7,left.location.register);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if (right.location.loc=LOC_CMMXREGISTER) then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(op,S_NO,right.location.register,left.location.register);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if not(right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
|
|
|
+ internalerror(200203246);
|
|
|
+ emit_ref_reg(op,S_NO,right.location.reference,left.location.register);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { right.location=LOC_MMXREGISTER }
|
|
|
+ if (nodetype=subn) and (nf_swaped in flags) then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(op,S_NO,left.location.register,right.location.register);
|
|
|
+ location_swap(left.location,right.location);
|
|
|
+ toggleflag(nf_swaped);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ emit_reg_reg(op,S_NO,right.location.register,left.location.register);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ if cmpop then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+ end;
|
|
|
+ set_result_location(cmpop,true);
|
|
|
+ end;
|
|
|
+{$endif SUPPORT_MMX}
|
|
|
+
|
|
|
+
|
|
|
+{*****************************************************************************
|
|
|
+ pass_2
|
|
|
+*****************************************************************************}
|
|
|
+
|
|
|
+ procedure tppcaddnode.pass_2;
|
|
|
+ { is also being used for xor, and "mul", "sub, or and comparative }
|
|
|
+ { operators }
|
|
|
+ var
|
|
|
+ pushedfpu,useconst,
|
|
|
+ { mboverflow, } cmpop : boolean;
|
|
|
+ op : tasmop;
|
|
|
+ cgop: topcg;
|
|
|
+{ cgsize : tcgsize; }
|
|
|
+ tmpreg: tregister;
|
|
|
+
|
|
|
+ { true, if unsigned types are compared }
|
|
|
+ unsigned : boolean;
|
|
|
+ { true, if for sets subtractions the extra not should generated }
|
|
|
+{ extra_not : boolean; }
|
|
|
+
|
|
|
+ regstopush: tregisterset;
|
|
|
+
|
|
|
+ begin
|
|
|
+ { to make it more readable, string and set (not smallset!) have their
|
|
|
+ own procedures }
|
|
|
+ case left.resulttype.def.deftype of
|
|
|
+ orddef :
|
|
|
+ begin
|
|
|
+ { handling boolean expressions }
|
|
|
+ if is_boolean(left.resulttype.def) and
|
|
|
+ is_boolean(right.resulttype.def) then
|
|
|
+ begin
|
|
|
+ second_addboolean;
|
|
|
+ exit;
|
|
|
+ end
|
|
|
+ { 64bit operations }
|
|
|
+ else if is_64bitint(left.resulttype.def) then
|
|
|
+ begin
|
|
|
+ second_add64bit;
|
|
|
+ exit;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ stringdef :
|
|
|
+ begin
|
|
|
+ internalerror(2002072402);
|
|
|
+ exit;
|
|
|
+ end;
|
|
|
+ setdef :
|
|
|
+ begin
|
|
|
+ { normalsets are already handled in pass1 }
|
|
|
+ if (tsetdef(left.resulttype.def).settype<>smallset) then
|
|
|
+ internalerror(200109041);
|
|
|
+ second_addsmallset;
|
|
|
+ exit;
|
|
|
+ end;
|
|
|
+ arraydef :
|
|
|
+ begin
|
|
|
+{$ifdef SUPPORT_MMX}
|
|
|
+ if is_mmx_able_array(left.resulttype.def) then
|
|
|
+ begin
|
|
|
+ second_addmmx;
|
|
|
+ exit;
|
|
|
+ end;
|
|
|
+{$endif SUPPORT_MMX}
|
|
|
+ end;
|
|
|
+ floatdef :
|
|
|
+ begin
|
|
|
+ second_addfloat;
|
|
|
+ exit;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { defaults }
|
|
|
+ {is_in_dest:=false;}
|
|
|
+{ extra_not:=false; }
|
|
|
+{ mboverflow:=false; }
|
|
|
+ cmpop:=nodetype in [ltn,lten,gtn,gten,equaln,unequaln];
|
|
|
+ unsigned:=not(is_signed(left.resulttype.def)) or
|
|
|
+ not(is_signed(right.resulttype.def));
|
|
|
+{ cgsize := def_cgsize(left.resulttype.def);}
|
|
|
+
|
|
|
+ pass_left_and_right(pushedfpu);
|
|
|
+
|
|
|
+(*
|
|
|
+ if (left.resulttype.def.deftype=pointerdef) or
|
|
|
+ (right.resulttype.def.deftype=pointerdef) or
|
|
|
+
|
|
|
+ (is_class_or_interface(right.resulttype.def) and is_class_or_interface(left.resulttype.def)) or
|
|
|
+
|
|
|
+ (left.resulttype.def.deftype=classrefdef) or
|
|
|
+
|
|
|
+ (left.resulttype.def.deftype=procvardef) or
|
|
|
+
|
|
|
+ ((left.resulttype.def.deftype=enumdef) and
|
|
|
+ (left.resulttype.def.size=4)) or
|
|
|
+
|
|
|
+ ((left.resulttype.def.deftype=orddef) and
|
|
|
+ (torddef(left.resulttype.def).typ in [s32bit,u32bit])) or
|
|
|
+ ((right.resulttype.def.deftype=orddef) and
|
|
|
+ (torddef(right.resulttype.def).typ in [s32bit,u32bit])) then
|
|
|
+*)
|
|
|
+ begin
|
|
|
+ { Convert flags to register first }
|
|
|
+ { can any of these things be in the flags actually?? (JM) }
|
|
|
+
|
|
|
+ if (left.location.loc = LOC_FLAGS) or
|
|
|
+ (right.location.loc = LOC_FLAGS) then
|
|
|
+ internalerror(2002072602);
|
|
|
+{
|
|
|
+ if (left.location.loc=LOC_FLAGS) then
|
|
|
+ location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],false);
|
|
|
+ if (right.location.loc=LOC_FLAGS) then
|
|
|
+ location_force_reg(exprasmlist,right.location,opsize_2_cgsize[opsize],false);
|
|
|
+}
|
|
|
+
|
|
|
+ { set result location }
|
|
|
+ if not cmpop then
|
|
|
+ location_reset(location,LOC_REGISTER,def_cgsize(resulttype.def))
|
|
|
+ else
|
|
|
+ location_reset(location,LOC_FLAGS,OS_NO);
|
|
|
+
|
|
|
+ case left.location.loc of
|
|
|
+ LOC_REGISTER:
|
|
|
+ if not cmpop then
|
|
|
+ location.register := left.location.register;
|
|
|
+ LOC_REFERENCE,LOC_CREFERENCE:
|
|
|
+ begin
|
|
|
+ location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
|
|
|
+ if not cmpop then
|
|
|
+ location.register := left.location.register;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ case right.location.loc of
|
|
|
+ LOC_REGISTER:
|
|
|
+ if not cmpop then
|
|
|
+ location.register := right.location.register;
|
|
|
+ LOC_REFERENCE,LOC_CREFERENCE:
|
|
|
+ begin
|
|
|
+ location_force_reg(exprasmlist,right.location,def_cgsize(right.resulttype.def),false);
|
|
|
+ if not cmpop then
|
|
|
+ location.register := right.location.register;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ // when overflow checking is on, all operands have to be in
|
|
|
+ // a register
|
|
|
+ if (cs_check_overflow in aktlocalswitches) and
|
|
|
+ not cmpop and
|
|
|
+ not (nodetype in [orn,andn,xorn]) then
|
|
|
+ begin
|
|
|
+ { left and right can't be both constants }
|
|
|
+ if (left.location.loc = LOC_CONSTANT) then
|
|
|
+ begin
|
|
|
+ location_force_reg(exprasmlist,left.location,
|
|
|
+ def_cgsize(left.resulttype.def),false);
|
|
|
+ location.register := left.location.register;
|
|
|
+ end
|
|
|
+ else if (right.location.loc = LOC_CONSTANT) then
|
|
|
+ begin
|
|
|
+ location_force_reg(exprasmlist,right.location,
|
|
|
+ def_cgsize(right.resulttype.def),false);
|
|
|
+ location.register := right.location.register;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (location.register = R_NO) and
|
|
|
+ not(cmpop) then
|
|
|
+ location.register := rg.getregisterint(exprasmlist);
|
|
|
+
|
|
|
+ if not(cs_check_overflow in aktlocalswitches) or
|
|
|
+ (cmpop) or
|
|
|
+ (nodetype in [orn,andn,xorn]) then
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ addn, muln, xorn, orn, andn:
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ addn:
|
|
|
+ cgop := OP_ADD;
|
|
|
+ muln:
|
|
|
+ if unsigned then
|
|
|
+ cgop := OP_MUL
|
|
|
+ else
|
|
|
+ cgop := OP_IMUL;
|
|
|
+ xorn:
|
|
|
+ cgop := OP_XOR;
|
|
|
+ orn:
|
|
|
+ cgop := OP_OR;
|
|
|
+ andn:
|
|
|
+ cgop := OP_AND;
|
|
|
+ end;
|
|
|
+ if (left.location.loc = LOC_CONSTANT) then
|
|
|
+ swapleftright;
|
|
|
+ if (right.location.loc <> LOC_CONSTANT) then
|
|
|
+ cg.a_op_reg_reg_reg(exprasmlist,cgop,OS_INT,
|
|
|
+ left.location.register,right.location.register,
|
|
|
+ location.register)
|
|
|
+ else
|
|
|
+ cg.a_op_const_reg_reg(exprasmlist,cgop,OS_INT,
|
|
|
+ aword(right.location.value),left.location.register,
|
|
|
+ location.register);
|
|
|
+ end;
|
|
|
+ subn:
|
|
|
+ begin
|
|
|
+ if (nf_swaped in flags) then
|
|
|
+ swapleftright;
|
|
|
+ if left.location.loc <> LOC_CONSTANT then
|
|
|
+ if right.location.loc <> LOC_CONSTANT then
|
|
|
+ cg.a_op_reg_reg_reg(exprasmlist,OP_SUB,OS_INT,
|
|
|
+ right.location.register,left.location.register,
|
|
|
+ location.register)
|
|
|
+ else
|
|
|
+ cg.a_op_const_reg_reg(exprasmlist,OP_SUB,OS_INT,
|
|
|
+ aword(right.location.value),left.location.register,
|
|
|
+ location.register)
|
|
|
+ else
|
|
|
+ if (longint(left.location.value) >= low(smallint)) and
|
|
|
+ (longint(left.location.value) <= high(smallint)) then
|
|
|
+ begin
|
|
|
+ exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,
|
|
|
+ location.register,right.location.register,
|
|
|
+ left.location.value));
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ tmpreg := cg.get_scratch_reg_int(exprasmlist);
|
|
|
+ cg.a_load_const_reg(exprasmlist,OS_INT,
|
|
|
+ left.location.value,tmpreg);
|
|
|
+ cg.a_op_reg_reg_reg(exprasmlist,OP_SUB,OS_INT,
|
|
|
+ right.location.register,tmpreg,location.register);
|
|
|
+ cg.free_scratch_reg(exprasmlist,tmpreg);
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ ltn,lten,gtn,gten, equaln,unequaln :
|
|
|
+ begin
|
|
|
+ // get the constant on the right if there is one
|
|
|
+ if (left.location.loc = LOC_CONSTANT) then
|
|
|
+ swapleftright;
|
|
|
+ // can we use an immediate, or do we have to load the
|
|
|
+ // constant in a register first?
|
|
|
+ if (right.location.loc = LOC_CONSTANT) then
|
|
|
+ if (unsigned and
|
|
|
+ (aword(right.location.value) > high(word))) or
|
|
|
+ (not(unsigned) and
|
|
|
+ ((longint(right.location.value) < low(smallint)) or
|
|
|
+ (longint(right.location.value) > high(smallint)))) then
|
|
|
+ useconst := true
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ useconst := false;
|
|
|
+ tmpreg := cg.get_scratch_reg_int(exprasmlist);
|
|
|
+ cg.a_load_const_reg(exprasmlist,OS_INT,
|
|
|
+ aword(right.location.value),tmpreg);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ useconst := false;
|
|
|
+ location.loc := LOC_FLAGS;
|
|
|
+ location.resflags := getresflags;
|
|
|
+ if not unsigned then
|
|
|
+ if useconst then
|
|
|
+ op := A_CMPWI
|
|
|
+ else
|
|
|
+ op := A_CMPW
|
|
|
+ else
|
|
|
+ if useconst then
|
|
|
+ op := A_CMPLWI
|
|
|
+ else
|
|
|
+ op := A_CMPLW;
|
|
|
+
|
|
|
+ if (right.location.loc = LOC_CONSTANT) then
|
|
|
+ if useconst then
|
|
|
+ exprasmlist.concat(taicpu.op_reg_const(op,
|
|
|
+ left.location.register,right.location.value))
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ exprasmlist.concat(taicpu.op_reg_reg(op,
|
|
|
+ left.location.register,tmpreg));
|
|
|
+ cg.free_scratch_reg(exprasmlist,tmpreg);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ exprasmlist.concat(taicpu.op_reg_reg(op,
|
|
|
+ left.location.register,right.location.register));
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ end
|
|
|
+ else
|
|
|
+ // overflow checking is on and we have an addn, subn or muln
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ addn:
|
|
|
+ op := A_ADDO;
|
|
|
+ subn:
|
|
|
+ op := A_SUBO;
|
|
|
+ muln:
|
|
|
+ op := A_MULLWO;
|
|
|
+ else
|
|
|
+ internalerror(2002072601);
|
|
|
+ end;
|
|
|
+ exprasmlist.concat(taicpu.op_reg_reg_reg(op,location.register,
|
|
|
+ left.location.register,right.location.register));
|
|
|
+ end;
|
|
|
+
|
|
|
+ end;
|
|
|
+
|
|
|
+ if (right.location.loc = LOC_REGISTER) and
|
|
|
+ (cmpop or
|
|
|
+ (location.register <> right.location.register)) then
|
|
|
+ rg.ungetregister(exprasmlist,right.location.register);
|
|
|
+ if (left.location.loc = LOC_REGISTER) and
|
|
|
+ (cmpop or
|
|
|
+ (location.register <> left.location.register)) then
|
|
|
+ rg.ungetregister(exprasmlist,left.location.register);
|
|
|
+
|
|
|
+ cg.g_overflowcheck(exprasmlist,self);
|
|
|
+(*
|
|
|
+ { 8/16 bit enum,char,wchar types }
|
|
|
+ else
|
|
|
+ if ((left.resulttype.def.deftype=orddef) and
|
|
|
+ (torddef(left.resulttype.def).typ in [uchar,uwidechar])) or
|
|
|
+ ((left.resulttype.def.deftype=enumdef) and
|
|
|
+ ((left.resulttype.def.size=1) or
|
|
|
+ (left.resulttype.def.size=2))) then
|
|
|
+ begin
|
|
|
+ case nodetype of
|
|
|
+ ltn,lten,gtn,gten,
|
|
|
+ equaln,unequaln :
|
|
|
+ cmpop:=true;
|
|
|
+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+ end;
|
|
|
+ left_must_be_reg(opsize,false);
|
|
|
+ emit_op_right_left(A_CMP,opsize);
|
|
|
+ location_freetemp(exprasmlist,right.location);
|
|
|
+ location_release(exprasmlist,right.location);
|
|
|
+ if left.location.loc<>LOC_CREGISTER then
|
|
|
+ begin
|
|
|
+ location_freetemp(exprasmlist,left.location);
|
|
|
+ location_release(exprasmlist,left.location);
|
|
|
+ end;
|
|
|
+ set_result_location(true,true);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ CGMessage(type_e_mismatch);
|
|
|
+*)
|
|
|
+ end;
|
|
|
+
|
|
|
+begin
|
|
|
+ caddnode:=tppcaddnode;
|
|
|
+end.
|
|
|
+{
|
|
|
+ $Log$
|
|
|
+ Revision 1.1 2002-07-26 12:31:57 jonas
|
|
|
+ + intial implementation of add nodes, only integer/enumeration/pointer/...
|
|
|
+ handling is finished
|
|
|
+
|
|
|
+
|
|
|
+}
|
Jonas Maebe