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@@ -829,10 +829,10 @@ Implementation
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end;
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end;
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{ Change the common
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- mov r0, r0, lsr #24
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- and r0, r0, #255
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+ mov r0, r0, lsr #xxx
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+ and r0, r0, #yyy/bic r0, r0, #xxx
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- and remove the superfluous and
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+ and remove the superfluous and/bic if possible
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This could be extended to handle more cases.
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}
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@@ -840,30 +840,46 @@ Implementation
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(taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oper[2]^.shifterop^.rs = NR_NO) and
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(taicpu(p).oper[2]^.shifterop^.shiftmode = SM_LSR) and
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- (taicpu(p).oper[2]^.shifterop^.shiftimm >= 24 ) and
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GetNextInstructionUsingReg(p,hp1, taicpu(p).oper[0]^.reg) and
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(assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) or
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- regLoadedWithNewValue(taicpu(p).oper[0]^.reg, hp1)) and
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- MatchInstruction(hp1, A_AND, [taicpu(p).condition], [taicpu(p).oppostfix]) and
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- (taicpu(hp1).ops=3) and
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- MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^) and
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- MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[1]^) and
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- (taicpu(hp1).oper[2]^.typ = top_const) and
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- { Check if the AND actually would only mask out bits beeing already zero because of the shift
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- For LSR #25 and an AndConst of 255 that whould go like this:
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- 255 and ((2 shl (32-25))-1)
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- which results in 127, which is one less a power-of-2, meaning all lower bits are set.
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-
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- LSR #25 and AndConst of 254:
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- 254 and ((2 shl (32-25))-1) = 126 -> lowest bit is clear, so we can't remove it.
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- }
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- ispowerof2((taicpu(hp1).oper[2]^.val and ((2 shl (32-taicpu(p).oper[2]^.shifterop^.shiftimm))-1))+1) then
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- begin
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- DebugMsg('Peephole LsrAnd2Lsr done', hp1);
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- asml.remove(hp1);
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- hp1.free;
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- result:=true;
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- end;
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+ regLoadedWithNewValue(taicpu(p).oper[0]^.reg, hp1)) then
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+ begin
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+ if (taicpu(p).oper[2]^.shifterop^.shiftimm >= 24 ) and
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+ MatchInstruction(hp1, A_AND, [taicpu(p).condition], [taicpu(p).oppostfix]) and
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+ (taicpu(hp1).ops=3) and
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+ MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[1]^) and
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+ (taicpu(hp1).oper[2]^.typ = top_const) and
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+ { Check if the AND actually would only mask out bits beeing already zero because of the shift
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+ For LSR #25 and an AndConst of 255 that whould go like this:
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+ 255 and ((2 shl (32-25))-1)
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+ which results in 127, which is one less a power-of-2, meaning all lower bits are set.
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+
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+ LSR #25 and AndConst of 254:
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+ 254 and ((2 shl (32-25))-1) = 126 -> lowest bit is clear, so we can't remove it.
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+ }
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+ ispowerof2((taicpu(hp1).oper[2]^.val and ((2 shl (32-taicpu(p).oper[2]^.shifterop^.shiftimm))-1))+1) then
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+ begin
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+ DebugMsg('Peephole LsrAnd2Lsr done', hp1);
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+ taicpu(p).oper[0]^.reg:=taicpu(hp1).oper[0]^.reg;
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+ asml.remove(hp1);
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+ hp1.free;
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+ result:=true;
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+ end
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+ else if MatchInstruction(hp1, A_BIC, [taicpu(p).condition], [taicpu(p).oppostfix]) and
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+ (taicpu(hp1).ops=3) and
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+ MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[1]^) and
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+ (taicpu(hp1).oper[2]^.typ = top_const) and
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+ { Check if the BIC actually would only mask out bits beeing already zero because of the shift }
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+ (taicpu(hp1).oper[2]^.val<>0) and
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+ (BsfDWord(taicpu(hp1).oper[2]^.val)>=32-taicpu(p).oper[2]^.shifterop^.shiftimm) then
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+ begin
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+ DebugMsg('Peephole LsrBic2Lsr done', hp1);
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+ taicpu(p).oper[0]^.reg:=taicpu(hp1).oper[0]^.reg;
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+ asml.remove(hp1);
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+ hp1.free;
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+ result:=true;
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+ end;
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+ end;
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{
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optimize
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florian