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@@ -14751,152 +14751,159 @@ unit aoptx86;
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{ changes some movzx constructs to faster synonyms (all examples
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{ changes some movzx constructs to faster synonyms (all examples
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are given with eax/ax, but are also valid for other registers)}
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are given with eax/ax, but are also valid for other registers)}
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if MatchOpType(taicpu(p),top_reg,top_reg) then
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if MatchOpType(taicpu(p),top_reg,top_reg) then
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- begin
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- case taicpu(p).opsize of
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- { Technically, movzbw %al,%ax cannot be encoded in 32/64-bit mode
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- (the machine code is equivalent to movzbl %al,%eax), but the
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- code generator still generates that assembler instruction and
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- it is silently converted. This should probably be checked.
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- [Kit] }
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- S_BW:
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+ begin
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+ case taicpu(p).opsize of
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+ { Technically, movzbw %al,%ax cannot be encoded in 32/64-bit mode
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+ (the machine code is equivalent to movzbl %al,%eax), but the
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+ code generator still generates that assembler instruction and
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+ it is silently converted. This should probably be checked.
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+ [Kit] }
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+ S_BW:
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+ begin
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+ if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
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+ (
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+ not IsMOVZXAcceptable
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+ { and $0xff,%ax has a smaller encoding but risks a partial write penalty }
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+ or (
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+ (cs_opt_size in current_settings.optimizerswitches) and
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+ (taicpu(p).oper[1]^.reg = NR_AX)
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+ )
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+ ) then
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+ {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'var7',p);
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+ taicpu(p).opcode := A_AND;
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+ taicpu(p).changeopsize(S_W);
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+ taicpu(p).loadConst(0,$ff);
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+ Result := True;
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+ end
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+ else if not IsMOVZXAcceptable and
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+ GetNextInstruction(p, hp1) and
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+ (tai(hp1).typ = ait_instruction) and
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+ (taicpu(hp1).opcode = A_AND) and
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+ MatchOpType(taicpu(hp1),top_const,top_reg) and
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+ (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ { Change "movzbw %reg1, %reg2; andw $const, %reg2"
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+ to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'var8',p);
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+ taicpu(p).opcode := A_MOV;
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+ taicpu(p).changeopsize(S_W);
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+ setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
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+ taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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+ Result := True;
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+ end;
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+ end;
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+{$ifndef i8086} { movzbl %al,%eax cannot be encoded in 16-bit mode (the machine code is equivalent to movzbw %al,%ax }
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+ S_BL:
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+ if not IsMOVZXAcceptable then
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begin
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begin
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- if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) and
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- (
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- not IsMOVZXAcceptable
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- { and $0xff,%ax has a smaller encoding but risks a partial write penalty }
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- or (
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- (cs_opt_size in current_settings.optimizerswitches) and
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- (taicpu(p).oper[1]^.reg = NR_AX)
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- )
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- ) then
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- {Change "movzbw %al, %ax" to "andw $0x0ffh, %ax"}
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+ if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) then
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+ { Change "movzbl %al, %eax" to "andl $0x0ffh, %eax" }
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begin
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begin
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- DebugMsg(SPeepholeOptimization + 'var7',p);
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+ DebugMsg(SPeepholeOptimization + 'var9',p);
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taicpu(p).opcode := A_AND;
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taicpu(p).opcode := A_AND;
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- taicpu(p).changeopsize(S_W);
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+ taicpu(p).changeopsize(S_L);
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taicpu(p).loadConst(0,$ff);
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taicpu(p).loadConst(0,$ff);
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Result := True;
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Result := True;
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end
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end
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- else if not IsMOVZXAcceptable and
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- GetNextInstruction(p, hp1) and
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+ else if GetNextInstruction(p, hp1) and
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(tai(hp1).typ = ait_instruction) and
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(tai(hp1).typ = ait_instruction) and
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(taicpu(hp1).opcode = A_AND) and
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(taicpu(hp1).opcode = A_AND) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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MatchOpType(taicpu(hp1),top_const,top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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- { Change "movzbw %reg1, %reg2; andw $const, %reg2"
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- to "movw %reg1, reg2; andw $(const1 and $ff), %reg2"}
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+ { Change "movzbl %reg1, %reg2; andl $const, %reg2"
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+ to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
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begin
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begin
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- DebugMsg(SPeepholeOptimization + 'var8',p);
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+ DebugMsg(SPeepholeOptimization + 'var10',p);
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taicpu(p).opcode := A_MOV;
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taicpu(p).opcode := A_MOV;
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- taicpu(p).changeopsize(S_W);
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- setsubreg(taicpu(p).oper[0]^.reg,R_SUBW);
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+ taicpu(p).changeopsize(S_L);
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+ { do not use R_SUBWHOLE
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+ as movl %rdx,%eax
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+ is invalid in assembler PM }
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+ setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
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taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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Result := True;
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Result := True;
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end;
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end;
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end;
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end;
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-{$ifndef i8086} { movzbl %al,%eax cannot be encoded in 16-bit mode (the machine code is equivalent to movzbw %al,%ax }
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- S_BL:
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- if not IsMOVZXAcceptable then
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- begin
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- if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) then
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- { Change "movzbl %al, %eax" to "andl $0x0ffh, %eax" }
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- begin
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- DebugMsg(SPeepholeOptimization + 'var9',p);
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- taicpu(p).opcode := A_AND;
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- taicpu(p).changeopsize(S_L);
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- taicpu(p).loadConst(0,$ff);
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- Result := True;
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- end
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- else if GetNextInstruction(p, hp1) and
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- (tai(hp1).typ = ait_instruction) and
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- (taicpu(hp1).opcode = A_AND) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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- { Change "movzbl %reg1, %reg2; andl $const, %reg2"
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- to "movl %reg1, reg2; andl $(const1 and $ff), %reg2"}
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- begin
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- DebugMsg(SPeepholeOptimization + 'var10',p);
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- taicpu(p).opcode := A_MOV;
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- taicpu(p).changeopsize(S_L);
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- { do not use R_SUBWHOLE
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- as movl %rdx,%eax
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- is invalid in assembler PM }
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- setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
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- taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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- Result := True;
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- end;
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- end;
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{$endif i8086}
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{$endif i8086}
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- S_WL:
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- if not IsMOVZXAcceptable then
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- begin
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- if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) then
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- { Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax" }
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- begin
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- DebugMsg(SPeepholeOptimization + 'var11',p);
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- taicpu(p).opcode := A_AND;
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- taicpu(p).changeopsize(S_L);
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- taicpu(p).loadConst(0,$ffff);
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- Result := True;
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- end
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- else if GetNextInstruction(p, hp1) and
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- (tai(hp1).typ = ait_instruction) and
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- (taicpu(hp1).opcode = A_AND) and
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- (taicpu(hp1).oper[0]^.typ = top_const) and
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- (taicpu(hp1).oper[1]^.typ = top_reg) and
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- (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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- { Change "movzwl %reg1, %reg2; andl $const, %reg2"
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- to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
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- begin
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- DebugMsg(SPeepholeOptimization + 'var12',p);
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- taicpu(p).opcode := A_MOV;
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- taicpu(p).changeopsize(S_L);
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- { do not use R_SUBWHOLE
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- as movl %rdx,%eax
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- is invalid in assembler PM }
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- setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
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- taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
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- Result := True;
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- end;
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- end;
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- else
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- InternalError(2017050705);
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- end;
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- end
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- else if not IsMOVZXAcceptable and (taicpu(p).oper[0]^.typ = top_ref) then
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- begin
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- if GetNextInstruction(p, hp1) and
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- (tai(hp1).typ = ait_instruction) and
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- (taicpu(hp1).opcode = A_AND) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ S_WL:
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+ if not IsMOVZXAcceptable then
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begin
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begin
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- //taicpu(p).opcode := A_MOV;
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- case taicpu(p).opsize Of
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- S_BL:
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- begin
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- DebugMsg(SPeepholeOptimization + 'var13',p);
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- taicpu(hp1).changeopsize(S_L);
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- taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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- end;
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- S_WL:
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- begin
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- DebugMsg(SPeepholeOptimization + 'var14',p);
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- taicpu(hp1).changeopsize(S_L);
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- taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
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- end;
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- S_BW:
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- begin
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- DebugMsg(SPeepholeOptimization + 'var15',p);
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- taicpu(hp1).changeopsize(S_W);
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- taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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- end;
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- else
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- Internalerror(2017050704)
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- end;
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- Result := True;
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+ if (getsupreg(taicpu(p).oper[0]^.reg)=getsupreg(taicpu(p).oper[1]^.reg)) then
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+ { Change "movzwl %ax, %eax" to "andl $0x0ffffh, %eax" }
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'var11',p);
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+ taicpu(p).opcode := A_AND;
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+ taicpu(p).changeopsize(S_L);
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+ taicpu(p).loadConst(0,$ffff);
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+ Result := True;
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+ end
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+ else if GetNextInstruction(p, hp1) and
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+ (tai(hp1).typ = ait_instruction) and
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+ (taicpu(hp1).opcode = A_AND) and
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+ (taicpu(hp1).oper[0]^.typ = top_const) and
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+ (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ { Change "movzwl %reg1, %reg2; andl $const, %reg2"
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+ to "movl %reg1, reg2; andl $(const1 and $ffff), %reg2"}
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'var12',p);
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+ taicpu(p).opcode := A_MOV;
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+ taicpu(p).changeopsize(S_L);
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+ { do not use R_SUBWHOLE
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+ as movl %rdx,%eax
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+ is invalid in assembler PM }
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+ setsubreg(taicpu(p).oper[0]^.reg, R_SUBD);
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+ taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
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+ Result := True;
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+ end;
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end;
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end;
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+ else
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+ InternalError(2017050705);
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+ end;
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+ end
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+ else if not IsMOVZXAcceptable and (taicpu(p).oper[0]^.typ = top_ref) then
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+ begin
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+ if GetNextInstruction(p, hp1) and
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+ (tai(hp1).typ = ait_instruction) and
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+ (taicpu(hp1).opcode = A_AND) and
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+ MatchOpType(taicpu(hp1),top_const,top_reg) and
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+ (taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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+ begin
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+ case taicpu(p).opsize Of
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+ S_BL:
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+ if (taicpu(hp1).opsize <> S_L) or
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+ (taicpu(hp1).oper[0]^.val > $FF) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'var13',p);
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+ taicpu(hp1).changeopsize(S_L);
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+ taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
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+ Include(OptsToCheck, aoc_ForceNewIteration);
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+ end;
|
|
|
|
|
+ S_WL:
|
|
|
|
|
+ if (taicpu(hp1).opsize <> S_L) or
|
|
|
|
|
+ (taicpu(hp1).oper[0]^.val > $FFFF) then
|
|
|
|
|
+ begin
|
|
|
|
|
+ DebugMsg(SPeepholeOptimization + 'var14',p);
|
|
|
|
|
+ taicpu(hp1).changeopsize(S_L);
|
|
|
|
|
+ taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ffff);
|
|
|
|
|
+ Include(OptsToCheck, aoc_ForceNewIteration);
|
|
|
|
|
+ end;
|
|
|
|
|
+ S_BW:
|
|
|
|
|
+ if (taicpu(hp1).opsize <> S_W) or
|
|
|
|
|
+ (taicpu(hp1).oper[0]^.val > $FF) then
|
|
|
|
|
+ begin
|
|
|
|
|
+ DebugMsg(SPeepholeOptimization + 'var15',p);
|
|
|
|
|
+ taicpu(hp1).changeopsize(S_W);
|
|
|
|
|
+ taicpu(hp1).loadConst(0,taicpu(hp1).oper[0]^.val and $ff);
|
|
|
|
|
+ Include(OptsToCheck, aoc_ForceNewIteration);
|
|
|
|
|
+ end;
|
|
|
|
|
+ else
|
|
|
|
|
+ Internalerror(2017050704)
|
|
|
|
|
+ end;
|
|
|
end;
|
|
end;
|
|
|
|
|
+ end;
|
|
|
end;
|
|
end;
|
|
|
end;
|
|
end;
|
|
|
|
|
|
J. Gareth "Curious Kit" Moreton