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@@ -0,0 +1,474 @@
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+{
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+ Copyright (c) 1998-2002 by Florian Klaempfl
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+
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+ Generate i8086 assembler for math nodes
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+
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+ This program is free software; you can redistribute it and/or modify
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+ it under the terms of the GNU General Public License as published by
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+ the Free Software Foundation; either version 2 of the License, or
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+ (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful,
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+ but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ GNU General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program; if not, write to the Free Software
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+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+
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+ ****************************************************************************
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+}
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+unit n8086mat;
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+
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+{$i fpcdefs.inc}
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+
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+interface
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+
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+ uses
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+ node,nmat,ncgmat,nx86mat;
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+
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+ type
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+ ti8086moddivnode = class(tmoddivnode)
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+ procedure pass_generate_code;override;
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+ end;
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+
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+ ti8086shlshrnode = class(tcgshlshrnode)
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+ procedure second_64bit;override;
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+ function first_shlshr64bitint: tnode; override;
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+ end;
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+
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+ ti8086unaryminusnode = class(tx86unaryminusnode)
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+ end;
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+
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+ ti8086notnode = class(tx86notnode)
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+ end;
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+
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+
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+implementation
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+
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+ uses
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+ globtype,systems,constexp,
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+ cutils,verbose,globals,
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+ symconst,symdef,aasmbase,aasmtai,aasmdata,defutil,
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+ cgbase,pass_2,
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+ ncon,
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+ cpubase,cpuinfo,
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+ cga,ncgutil,cgobj,cgutils,
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+ hlcgobj;
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+
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+{*****************************************************************************
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+ ti8086moddivnode
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+*****************************************************************************}
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+
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+ function log2(i : dword) : dword;
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+ begin
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+ result:=0;
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+ i:=i shr 1;
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+ while i<>0 do
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+ begin
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+ i:=i shr 1;
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+ inc(result);
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+ end;
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+ end;
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+
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+
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+ procedure ti8086moddivnode.pass_generate_code;
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+ var
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+ hreg1,hreg2:Tregister;
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+ power:longint;
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+ hl:Tasmlabel;
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+ op:Tasmop;
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+ e : longint;
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+ d,l,r,s,m,a,n,t : dword;
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+ m_low,m_high,j,k : qword;
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+ begin
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+ secondpass(left);
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+ if codegenerror then
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+ exit;
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+ secondpass(right);
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+ if codegenerror then
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+ exit;
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+
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+ if is_64bitint(resultdef) then
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+ { should be handled in pass_1 (JM) }
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+ internalerror(200109052);
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+ { put numerator in register }
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+ location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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+ hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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+ hreg1:=left.location.register;
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+
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+ if (nodetype=divn) and (right.nodetype=ordconstn) then
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+ begin
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+ if ispowerof2(tordconstnode(right).value.svalue,power) then
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+ begin
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+ { for signed numbers, the numerator must be adjusted before the
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+ shift instruction, but not wih unsigned numbers! Otherwise,
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+ "Cardinal($ffffffff) div 16" overflows! (JM) }
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+ if is_signed(left.resultdef) Then
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+ begin
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+ if (current_settings.optimizecputype <> cpu_386) and
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+ not(cs_opt_size in current_settings.optimizerswitches) then
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+ { use a sequence without jumps, saw this in
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+ comp.compilers (JM) }
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+ begin
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+ { no jumps, but more operations }
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+ hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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+ {If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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+ emit_const_reg(A_SAR,S_L,31,hreg2);
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+ {If signed, hreg2=right value-1, otherwise 0.}
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+ emit_const_reg(A_AND,S_L,tordconstnode(right).value.svalue-1,hreg2);
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+ { add to the left value }
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+ emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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+ { do the shift }
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+ emit_const_reg(A_SAR,S_L,power,hreg1);
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+ end
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+ else
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+ begin
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+ { a jump, but less operations }
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+ emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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+ current_asmdata.getjumplabel(hl);
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+ cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NS,hl);
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+ if power=1 then
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+ emit_reg(A_INC,S_L,hreg1)
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+ else
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+ emit_const_reg(A_ADD,S_L,tordconstnode(right).value.svalue-1,hreg1);
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+ cg.a_label(current_asmdata.CurrAsmList,hl);
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+ emit_const_reg(A_SAR,S_L,power,hreg1);
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+ end
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+ end
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+ else
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+ emit_const_reg(A_SHR,S_L,power,hreg1);
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+ location.register:=hreg1;
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+ end
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+ else
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+ begin
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+ if is_signed(left.resultdef) then
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+ begin
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+ e:=tordconstnode(right).value.svalue;
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+ d:=abs(e);
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+ { Determine algorithm (a), multiplier (m), and shift factor (s) for 32-bit
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+ signed integer division. Based on: Granlund, T.; Montgomery, P.L.:
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+ "Division by Invariant Integers using Multiplication". SIGPLAN Notices,
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+ Vol. 29, June 1994, page 61.
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+ }
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+
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+ l:=log2(d);
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+ j:=qword($80000000) mod qword(d);
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+ k:=(qword(1) shl (32+l)) div (qword($80000000-j));
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+ m_low:=((qword(1)) shl (32+l)) div d;
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+ m_high:=(((qword(1)) shl (32+l)) + k) div d;
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+ while ((m_low shr 1) < (m_high shr 1)) and (l > 0) do
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+ begin
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+ m_low:=m_low shr 1;
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+ m_high:=m_high shr 1;
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+ dec(l);
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+ end;
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+ m:=dword(m_high);
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+ s:=l;
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+ if (m_high shr 31)<>0 then
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+ a:=1
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+ else
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+ a:=0;
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ emit_const_reg(A_MOV,S_L,aint(m),NR_EAX);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ emit_reg(A_IMUL,S_L,hreg1);
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+ emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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+ if a<>0 then
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+ begin
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+ emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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+ {
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+ printf ("; dividend: memory location or register other than EAX or EDX\n");
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+ printf ("\n");
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+ printf ("MOV EAX, 0%08LXh\n", m);
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+ printf ("IMUL dividend\n");
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+ printf ("MOV EAX, dividend\n");
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+ printf ("ADD EDX, EAX\n");
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+ if (s) printf ("SAR EDX, %d\n", s);
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+ printf ("SHR EAX, 31\n");
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+ printf ("ADD EDX, EAX\n");
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+ if (e < 0) printf ("NEG EDX\n");
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+ printf ("\n");
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+ printf ("; quotient now in EDX\n");
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+ }
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+ end;
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+ {
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+ printf ("; dividend: memory location of register other than EAX or EDX\n");
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+ printf ("\n");
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+ printf ("MOV EAX, 0%08LXh\n", m);
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+ printf ("IMUL dividend\n");
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+ printf ("MOV EAX, dividend\n");
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+ if (s) printf ("SAR EDX, %d\n", s);
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+ printf ("SHR EAX, 31\n");
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+ printf ("ADD EDX, EAX\n");
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+ if (e < 0) printf ("NEG EDX\n");
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+ printf ("\n");
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+ printf ("; quotient now in EDX\n");
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+ }
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+ if s<>0 then
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+ emit_const_reg(A_SAR,S_L,s,NR_EDX);
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+ emit_const_reg(A_SHR,S_L,31,NR_EAX);
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+ emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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+ if e<0 then
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+ emit_reg(A_NEG,S_L,NR_EDX);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EDX,location.register)
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+ end
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+ else
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+ begin
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+ d:=tordconstnode(right).value.svalue;
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+ if d>=$80000000 then
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+ begin
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+ emit_const_reg(A_CMP,S_L,aint(d),hreg1);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ emit_const_reg(A_MOV,S_L,0,location.register);
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+ emit_const_reg(A_SBB,S_L,-1,location.register);
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+ end
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+ else
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+ begin
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+ { Reduce divisor until it becomes odd }
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+ n:=0;
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+ t:=d;
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+ while (t and 1)=0 do
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+ begin
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+ t:=t shr 1;
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+ inc(n);
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+ end;
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+ { Generate m, s for algorithm 0. Based on: Granlund, T.; Montgomery,
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+ P.L.: "Division by Invariant Integers using Multiplication".
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+ SIGPLAN Notices, Vol. 29, June 1994, page 61.
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+ }
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+ l:=log2(t)+1;
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+ j:=qword($ffffffff) mod qword(t);
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+ k:=(qword(1) shl (32+l)) div (qword($ffffffff-j));
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+ m_low:=((qword(1)) shl (32+l)) div t;
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+ m_high:=(((qword(1)) shl (32+l)) + k) div t;
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+ while ((m_low shr 1) < (m_high shr 1)) and (l>0) do
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+ begin
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+ m_low:=m_low shr 1;
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+ m_high:=m_high shr 1;
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+ l:=l-1;
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+ end;
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+ if (m_high shr 32)=0 then
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+ begin
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+ m:=dword(m_high);
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+ s:=l;
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+ a:=0;
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+ end
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+
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+ { Generate m, s for algorithm 1. Based on: Magenheimer, D.J.; et al:
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+ "Integer Multiplication and Division on the HP Precision Architecture".
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+ IEEE Transactions on Computers, Vol 37, No. 8, August 1988, page 980.
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+ }
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+ else
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+ begin
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+ s:=log2(t);
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+ m_low:=(qword(1) shl (32+s)) div qword(t);
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+ r:=dword(((qword(1)) shl (32+s)) mod qword(t));
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+ if (r < ((t>>1)+1)) then
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+ m:=dword(m_low)
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+ else
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+ m:=dword(m_low)+1;
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+ a:=1;
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+ end;
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+ { Reduce multiplier for either algorithm to smallest possible }
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+ while (m and 1)=0 do
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+ begin
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+ m:=m shr 1;
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+ dec(s);
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+ end;
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+ { Adjust multiplier for reduction of even divisors }
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+ inc(s,n);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ emit_const_reg(A_MOV,S_L,aint(m),NR_EAX);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ emit_reg(A_MUL,S_L,hreg1);
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+ if a<>0 then
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+ begin
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+ {
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+ printf ("; dividend: register other than EAX or memory location\n");
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+ printf ("\n");
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+ printf ("MOV EAX, 0%08lXh\n", m);
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+ printf ("MUL dividend\n");
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+ printf ("ADD EAX, 0%08lXh\n", m);
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+ printf ("ADC EDX, 0\n");
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+ if (s) printf ("SHR EDX, %d\n", s);
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+ printf ("\n");
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+ printf ("; quotient now in EDX\n");
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+ }
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+ emit_const_reg(A_ADD,S_L,aint(m),NR_EAX);
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+ emit_const_reg(A_ADC,S_L,0,NR_EDX);
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+ end;
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+ if s<>0 then
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+ emit_const_reg(A_SHR,S_L,aint(s),NR_EDX);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EDX,location.register)
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+ end;
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+ end
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+ end
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+ end
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+ else
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+ begin
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ {Sign extension depends on the left type.}
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+ if torddef(left.resultdef).ordtype=u32bit then
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+ emit_reg_reg(A_XOR,S_L,NR_EDX,NR_EDX)
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+ else
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+ emit_none(A_CDQ,S_NO);
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+
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+ {Division depends on the right type.}
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+ if Torddef(right.resultdef).ordtype=u32bit then
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+ op:=A_DIV
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+ else
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+ op:=A_IDIV;
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+
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+ if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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+ emit_ref(op,S_L,right.location.reference)
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+ else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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+ emit_reg(op,S_L,right.location.register)
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+ else
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+ begin
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+ hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
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+ hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u32inttype,right.location,hreg1);
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+ emit_reg(op,S_L,hreg1);
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+ end;
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+
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+ {Copy the result into a new register. Release EAX & EDX.}
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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+ location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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+ if nodetype=divn then
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EAX,location.register)
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+ else
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+ cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EDX,location.register);
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+ end;
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+ end;
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+
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+
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+{*****************************************************************************
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+ TI386SHLRSHRNODE
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+*****************************************************************************}
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+
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+
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+ function ti8086shlshrnode.first_shlshr64bitint: tnode;
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+ begin
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+ result := nil;
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+ end;
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+
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+ procedure ti8086shlshrnode.second_64bit;
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+ var
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+ hreg64hi,hreg64lo:Tregister;
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+ v : TConstExprInt;
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+ l1,l2,l3:Tasmlabel;
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+ begin
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+ location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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+
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|
|
+ { load left operator in a register }
|
|
|
+ hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
|
|
|
+ hreg64hi:=left.location.register64.reghi;
|
|
|
+ hreg64lo:=left.location.register64.reglo;
|
|
|
+
|
|
|
+ { shifting by a constant directly coded: }
|
|
|
+ if (right.nodetype=ordconstn) then
|
|
|
+ begin
|
|
|
+ v:=Tordconstnode(right).value and 63;
|
|
|
+ if v>31 then
|
|
|
+ begin
|
|
|
+ if nodetype=shln then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
|
|
|
+ if ((v and 31) <> 0) then
|
|
|
+ emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
|
|
|
+ if ((v and 31) <> 0) then
|
|
|
+ emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
|
|
|
+ end;
|
|
|
+ location.register64.reghi:=hreg64lo;
|
|
|
+ location.register64.reglo:=hreg64hi;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if nodetype=shln then
|
|
|
+ begin
|
|
|
+ emit_const_reg_reg(A_SHLD,S_L,v.svalue and 31,hreg64lo,hreg64hi);
|
|
|
+ emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ emit_const_reg_reg(A_SHRD,S_L,v.svalue and 31,hreg64hi,hreg64lo);
|
|
|
+ emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
|
|
|
+ end;
|
|
|
+ location.register64.reglo:=hreg64lo;
|
|
|
+ location.register64.reghi:=hreg64hi;
|
|
|
+ end;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ { load right operators in a register }
|
|
|
+ cg.getcpuregister(current_asmdata.CurrAsmList,NR_ECX);
|
|
|
+ hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u32inttype,right.location,NR_ECX);
|
|
|
+
|
|
|
+ { left operator is already in a register }
|
|
|
+ { hence are both in a register }
|
|
|
+ { is it in the case ECX ? }
|
|
|
+
|
|
|
+ { the damned shift instructions work only til a count of 32 }
|
|
|
+ { so we've to do some tricks here }
|
|
|
+ current_asmdata.getjumplabel(l1);
|
|
|
+ current_asmdata.getjumplabel(l2);
|
|
|
+ current_asmdata.getjumplabel(l3);
|
|
|
+ emit_const_reg(A_CMP,S_L,64,NR_ECX);
|
|
|
+ cg.a_jmp_flags(current_asmdata.CurrAsmList,F_L,l1);
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
|
|
|
+ cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
|
|
|
+ cg.a_label(current_asmdata.CurrAsmList,l1);
|
|
|
+ emit_const_reg(A_CMP,S_L,32,NR_ECX);
|
|
|
+ cg.a_jmp_flags(current_asmdata.CurrAsmList,F_L,l2);
|
|
|
+ emit_const_reg(A_SUB,S_L,32,NR_ECX);
|
|
|
+ if nodetype=shln then
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
|
|
|
+ emit_reg_reg(A_MOV,S_L,hreg64lo,hreg64hi);
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
|
|
|
+ cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
|
|
|
+ cg.a_label(current_asmdata.CurrAsmList,l2);
|
|
|
+ emit_reg_reg_reg(A_SHLD,S_L,NR_CL,hreg64lo,hreg64hi);
|
|
|
+ emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
|
|
|
+ emit_reg_reg(A_MOV,S_L,hreg64hi,hreg64lo);
|
|
|
+ emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
|
|
|
+ cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
|
|
|
+ cg.a_label(current_asmdata.CurrAsmList,l2);
|
|
|
+ emit_reg_reg_reg(A_SHRD,S_L,NR_CL,hreg64hi,hreg64lo);
|
|
|
+ emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
|
|
|
+ end;
|
|
|
+ cg.a_label(current_asmdata.CurrAsmList,l3);
|
|
|
+
|
|
|
+ cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_ECX);
|
|
|
+ location.register64.reglo:=hreg64lo;
|
|
|
+ location.register64.reghi:=hreg64hi;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
+begin
|
|
|
+ cunaryminusnode:=ti8086unaryminusnode;
|
|
|
+ cmoddivnode:=ti8086moddivnode;
|
|
|
+ cshlshrnode:=ti8086shlshrnode;
|
|
|
+ cnotnode:=ti8086notnode;
|
|
|
+end.
|
nickysn