* Unmerge last merge. accidentally ran the verifying make all in the trunk dir

git-svn-id: branches/fixes_2_6@22527 -

compiler/arm/aasmcpu.pas

@@ -567,12 +567,10 @@ implementation
     function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
       begin
         { allow the register allocator to remove unnecessary moves }
-        result:=(
-                  ((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
-                  ((opcode=A_MVF) and (regtype = R_FPUREGISTER)) or
-                  ((opcode in [A_FCPYS, A_FCPYD]) and (regtype = R_MMREGISTER))
+        result:=(((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
+                 ((opcode=A_MVF) and (regtype = R_FPUREGISTER) and (oppostfix in [PF_None,PF_D])) or
+                 (((opcode=A_FCPYS) or (opcode=A_FCPYD)) and (regtype = R_MMREGISTER))
                 ) and
-                (oppostfix in [PF_None,PF_D]) and
                 (condition=C_None) and
                 (ops=2) and
                 (oper[0]^.typ=top_reg) and

compiler/arm/agarmgas.pas

@@ -147,10 +147,7 @@ unit agarmgas;
 
                      s:=s+gas_regname(index);
 
-                     {RRX always rotates by 1 bit and does not take an imm}
-                     if shiftmode = SM_RRX then
-                       s:=s+', rrx'
-                     else if shiftmode <> SM_None then
+                     if shiftmode<>SM_None then
                        s:=s+', '+gas_shiftmode2str[shiftmode]+' #'+tostr(shiftimm);
                   end
                 else if offset<>0 then
@@ -168,6 +165,10 @@ unit agarmgas;
         getreferencestring:=s;
       end;
 
+
+    const
+      shiftmode2str: array[tshiftmode] of string[3] = ('','lsl','lsr','asr','ror','rrx');
+
     function getopstr(const o:toper) : string;
       var
         hs : string;
@@ -179,13 +180,10 @@ unit agarmgas;
             getopstr:=gas_regname(o.reg);
           top_shifterop:
             begin
-              {RRX is special, it only rotates by 1 and does not take any shiftervalue}
-              if o.shifterop^.shiftmode=SM_RRX then
-                getopstr:='rrx'
-              else if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
-                getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
+              if (o.shifterop^.rs<>NR_NO) and (o.shifterop^.shiftimm=0) then
+                getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' '+gas_regname(o.shifterop^.rs)
               else if (o.shifterop^.rs=NR_NO) then
-                getopstr:=gas_shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
+                getopstr:=shiftmode2str[o.shifterop^.shiftmode]+' #'+tostr(o.shifterop^.shiftimm)
               else internalerror(200308282);
             end;
           top_const:

compiler/arm/narminl.pas

@@ -49,7 +49,6 @@ interface
         procedure second_sin_real; override;
         }
         procedure second_prefetch; override;
-        procedure second_abs_long; override;
       private
         procedure load_fpu_location(out singleprec: boolean);
       end;
@@ -60,14 +59,14 @@ implementation
     uses
       globtype,systems,
       cutils,verbose,globals,fmodule,
-      cpuinfo, defutil,
+      cpuinfo,
       symconst,symdef,
       aasmbase,aasmtai,aasmdata,aasmcpu,
       cgbase,cgutils,
       pass_1,pass_2,
       cpubase,paramgr,
       nbas,ncon,ncal,ncnv,nld,
-      tgobj,ncgutil,cgobj,cg64f32,rgobj,rgcpu,cgcpu, hlcgobj;
+      tgobj,ncgutil,cgobj,cg64f32,rgobj,rgcpu,cgcpu;
 
 {*****************************************************************************
                               tarminlinenode
@@ -332,21 +331,6 @@ implementation
           end;
       end;
 
-    procedure tarminlinenode.second_abs_long;
-      var
-        hregister : tregister;
-        opsize : tcgsize;
-        hp : taicpu;
-      begin
-        secondpass(left);
-        opsize:=def_cgsize(left.resultdef);
-        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
-        hregister:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
-        location:=left.location;
-        location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
-        current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_MOV,location.register,left.location.register), PF_S));
-        current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg_const(A_RSB,location.register,location.register, 0), C_MI));
-      end;
 
 begin
   cinlinenode:=tarminlinenode;

compiler/arm/narmmat.pas

@@ -42,10 +42,6 @@ interface
         procedure second_float;override;
       end;
 
-      tarmshlshrnode = class(tcgshlshrnode)
-         procedure second_64bit;override;
-         function first_shlshr64bitint: tnode; override;
-      end;
 
 implementation
 
@@ -295,142 +291,9 @@ implementation
         end;
       end;
 
-    function tarmshlshrnode.first_shlshr64bitint: tnode;
-      begin
-        result := nil;
-      end;
-
-    procedure tarmshlshrnode.second_64bit;
-      var
-        hreg64hi,hreg64lo,shiftreg:Tregister;
-        v : TConstExprInt;
-        l1,l2,l3:Tasmlabel;
-        so: tshifterop;
-
-      procedure emit_instr(p: tai);
-        begin
-          current_asmdata.CurrAsmList.concat(p);
-        end;
-
-      {Reg1 gets shifted and moved into reg2, and is set to zero afterwards}
-      procedure shift_more_than_32(reg1, reg2: TRegister; shiftval: Byte ; sm: TShiftMode);
-        begin
-          shifterop_reset(so); so.shiftimm:=shiftval - 32; so.shiftmode:=sm;
-          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so));
-          emit_instr(taicpu.op_reg_const(A_MOV, reg1, 0));
-        end;
-
-      procedure shift_less_than_32(reg1, reg2: TRegister; shiftval: Byte; shiftright: boolean);
-        begin
-          shifterop_reset(so); so.shiftimm:=shiftval;
-          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
-          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
-
-          if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
-          so.shiftimm:=32-shiftval;
-          emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg1, reg1, reg2, so));
-
-          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
-          so.shiftimm:=shiftval;
-          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so));
-        end;
-
-      procedure shift_by_variable(reg1, reg2, shiftval: TRegister; shiftright: boolean);
-        var
-          shiftval2:TRegister;
-        begin
-          shifterop_reset(so);
-          shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
-          {Do we shift more than 32 bits?}
-          emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S));
-
-          {This part cares for 32 bits and more}
-          emit_instr(setcondition(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval, 32), C_MI));
-          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
-          so.rs:=shiftval2;
-          emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so), C_MI));
-
-          {Less than 32 bits}
-          so.rs:=shiftval;
-          emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so), C_PL));
-          if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
-          so.rs:=shiftval2;
-          emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL));
-
-          {Final adjustments}
-          if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
-          so.rs:=shiftval;
-          emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
-        end;
-
-      begin
-        location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
-
-        { load left operator in a register }
-        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
-        hreg64hi:=left.location.register64.reghi;
-        hreg64lo:=left.location.register64.reglo;
-        location.register64.reghi:=hreg64hi;
-        location.register64.reglo:=hreg64lo;
-
-        { shifting by a constant directly coded: }
-        if (right.nodetype=ordconstn) then
-          begin
-            v:=Tordconstnode(right).value and 63;
-            {Single bit shift}
-            if v = 1 then
-              if nodetype=shln then
-                begin
-                  {Shift left by one by 2 simple 32bit additions}
-                  emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S));
-                  emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi));
-                end
-              else
-                begin
-                  {Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
-                  shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
-                  emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S));
-                  so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
-                  emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so));
-                end
-            {A 32bit shift just replaces a register and clears the other}
-            else if v = 32 then
-              begin
-                if nodetype=shln then
-                  emit_instr(taicpu.op_reg_const(A_MOV, hreg64hi, 0))
-                else
-                  emit_instr(taicpu.op_reg_const(A_MOV, hreg64lo, 0));
-                location.register64.reghi:=hreg64lo;
-                location.register64.reglo:=hreg64hi;
-              end
-            {Shift LESS than 32}
-            else if v < 32 then
-              if nodetype=shln then
-                shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
-              else
-                shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
-            {More than 32}
-            else
-              if nodetype=shln then
-                shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
-              else
-                shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR)
-          end
-        else
-          begin
-            { force right operators in a register }
-            hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,false);
-            if nodetype = shln then
-              shift_by_variable(hreg64lo,hreg64hi,right.location.register, false)
-            else
-              shift_by_variable(hreg64hi,hreg64lo,right.location.register, true);
-          end;
-      end;
-
 
 begin
   cmoddivnode:=tarmmoddivnode;
   cnotnode:=tarmnotnode;
   cunaryminusnode:=tarmunaryminusnode;
-  cshlshrnode:=tarmshlshrnode;
 end.

compiler/options.pas

@@ -2658,7 +2658,7 @@ begin
   def_system_macro('FPC_HAS_OPERATOR_ENUMERATOR');
   def_system_macro('FPC_HAS_CONSTREF');
   def_system_macro('FPC_STATICRIPFIXED');
-{$if defined(x86) or defined(powerpc) or defined(powerpc64) or defined(cpuarm)}
+{$if defined(x86) or defined(powerpc) or defined(powerpc64)}
   def_system_macro('FPC_HAS_INTERNAL_ABS_LONG');
 {$endif}
   def_system_macro('FPC_HAS_UNICODESTRING');