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@@ -71,12 +71,27 @@ uses
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*****************************************************************************}
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function tmipseltypeconvnode.first_int_to_real: tnode;
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+var
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+ fname: string[19];
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begin
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{ converting a 64bit integer to a float requires a helper }
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if is_64bitint(left.resultdef) or
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is_currency(left.resultdef) then
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begin
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- result:=inherited first_int_to_real;
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+ { hack to avoid double division by 10000, as it's
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+ already done by typecheckpass.resultdef_int_to_real }
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+ if is_currency(left.resultdef) then
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+ left.resultdef := s64inttype;
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+ if is_signed(left.resultdef) then
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+ fname := 'fpc_int64_to_double'
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+ else
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+ fname := 'fpc_qword_to_double';
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+ result := ccallnode.createintern(fname,ccallparanode.create(
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+ left,nil));
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+ left:=nil;
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+ if (tfloatdef(resultdef).floattype=s32real) then
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+ inserttypeconv(result,s32floattype);
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+ firstpass(result);
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exit;
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end
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else
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@@ -105,11 +120,18 @@ procedure tMIPSELtypeconvnode.second_int_to_real;
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procedure loadsigned;
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begin
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- hlcg.location_force_mem(current_asmdata.CurrAsmList, left.location, left.resultdef);
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location.Register := cg.getfpuregister(current_asmdata.CurrAsmList, location.size);
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- { Load memory in fpu register }
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- cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList, OS_F32, OS_F32, left.location.reference, location.Register);
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- tg.ungetiftemp(current_asmdata.CurrAsmList, left.location.reference);
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+ if (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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+ { 32-bit values can be loaded directly }
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+ current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_MTC1, left.location.register, location.register))
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+ else
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+ begin
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+ { Load memory in fpu register }
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+ hlcg.location_force_mem(current_asmdata.CurrAsmList, left.location, left.resultdef);
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+ cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList, OS_F32, OS_F32, left.location.reference, location.Register);
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+ tg.ungetiftemp(current_asmdata.CurrAsmList, left.location.reference);
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+ end;
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+
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{ Convert value in fpu register from integer to float }
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case tfloatdef(resultdef).floattype of
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s32real:
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@@ -125,7 +147,6 @@ var
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href: treference;
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hregister: tregister;
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l1, l2: tasmlabel;
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- ai : TaiCpu;
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addend: array[boolean] of longword;
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bigendian: boolean;
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begin
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@@ -148,9 +169,7 @@ begin
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{ Convert value in fpu register from integer to float }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CVT_D_W, location.Register, location.Register));
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- ai := Taicpu.op_reg_reg_sym(A_BC, hregister, NR_R0, l2);
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- ai.setCondition(C_GE);
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- current_asmdata.CurrAsmList.concat(ai);
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+ cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList, OS_INT, OC_GTE, 0, hregister, l2);
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case tfloatdef(resultdef).floattype of
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{ converting dword to s64real first and cut off at the end avoids precision loss }
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