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@@ -10603,7 +10603,11 @@ movzx_cascade:
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S_WQ:
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begin
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if taicpu(p).opcode = A_MOVZX then
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- taicpu(p).opsize := S_BL
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+ begin
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+ taicpu(p).opsize := S_BL;
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+ { 64-bit zero extension is implicit, so change to the 32-bit register }
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+ setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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+ end
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else
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taicpu(p).opsize := S_BQ;
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RegUsed := True;
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@@ -10618,7 +10622,11 @@ movzx_cascade:
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S_LQ:
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begin
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if taicpu(p).opcode = A_MOVZX then
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- taicpu(p).opsize := S_BL
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+ begin
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+ taicpu(p).opsize := S_BL;
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+ { 64-bit zero extension is implicit, so change to the 32-bit register }
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+ setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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+ end
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else
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taicpu(p).opsize := S_BQ;
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RegUsed := True;
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@@ -10631,7 +10639,11 @@ movzx_cascade:
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S_LQ:
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begin
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if taicpu(p).opcode = A_MOVZX then
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- taicpu(p).opsize := S_WL
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+ begin
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+ taicpu(p).opsize := S_WL;
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+ { 64-bit zero extension is implicit, so change to the 32-bit register }
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+ setsubreg(taicpu(hp1).oper[1]^.reg, R_SUBD);
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+ end
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else
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taicpu(p).opsize := S_WQ;
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RegUsed := True;
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