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@@ -3363,9 +3363,10 @@ unit aoptx86;
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end;
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var
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- hp1,hp2: tai;
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-{$ifdef x86_64}
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- hp3: tai;
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+ hp1,hp2,hp3: tai;
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+{$ifndef x86_64}
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+ hp4: tai;
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+ OperIdx: Integer;
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{$endif x86_64}
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begin
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Result:=false;
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@@ -3510,6 +3511,291 @@ unit aoptx86;
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Result:=true;
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exit;
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end
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+ else if MatchOpType(taicpu(p),top_reg,top_reg) and
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+ MatchInstruction(hp1, A_SAR, []) then
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+ begin
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+ if MatchOperand(taicpu(hp1).oper[0]^, 31) then
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+ begin
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+ { the use of %edx also covers the opsize being S_L }
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+ if MatchOperand(taicpu(hp1).oper[1]^, NR_EDX) then
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+ begin
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+ { Note it has to be specifically "movl %eax,%edx", and those specific sub-registers }
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+ if (taicpu(p).oper[0]^.reg = NR_EAX) and
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+ (taicpu(p).oper[1]^.reg = NR_EDX) then
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+ begin
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+ { Change:
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+ movl %eax,%edx
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+ sarl $31,%edx
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+ To:
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+ cltd
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovSar2Cltd', p);
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+ Asml.Remove(hp1);
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+ hp1.Free;
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+ taicpu(p).opcode := A_CDQ;
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+ taicpu(p).opsize := S_NO;
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+ taicpu(p).clearop(1);
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+ taicpu(p).clearop(0);
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+ taicpu(p).ops:=0;
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+ Result := True;
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+ end
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+ else if (cs_opt_size in current_settings.optimizerswitches) and
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+ (taicpu(p).oper[0]^.reg = NR_EDX) and
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+ (taicpu(p).oper[1]^.reg = NR_EAX) then
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+ begin
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+ { Change:
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+ movl %edx,%eax
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+ sarl $31,%edx
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+ To:
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+ movl %edx,%eax
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+ cltd
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+
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+ Note that this creates a dependency between the two instructions,
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+ so only perform if optimising for size.
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovSar2MovCltd', p);
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+ taicpu(hp1).opcode := A_CDQ;
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+ taicpu(hp1).opsize := S_NO;
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+ taicpu(hp1).clearop(1);
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+ taicpu(hp1).clearop(0);
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+ taicpu(hp1).ops:=0;
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+ end;
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+{$ifndef x86_64}
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+ end
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+ { Don't bother if CMOV is supported, because a more optimal
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+ sequence would have been generated for the Abs() intrinsic }
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+ else if not(CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype]) and
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+ { the use of %eax also covers the opsize being S_L }
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+ MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) and
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+ (taicpu(p).oper[0]^.reg = NR_EAX) and
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+ (taicpu(p).oper[1]^.reg = NR_EDX) and
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+ GetNextInstruction(hp1, hp2) and
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+ MatchInstruction(hp2, A_XOR, [S_L]) and
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+ MatchOperand(taicpu(hp2).oper[0]^, NR_EAX) and
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+ MatchOperand(taicpu(hp2).oper[1]^, NR_EDX) and
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+
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+ GetNextInstruction(hp2, hp3) and
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+ MatchInstruction(hp3, A_SUB, [S_L]) and
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+ MatchOperand(taicpu(hp3).oper[0]^, NR_EAX) and
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+ MatchOperand(taicpu(hp3).oper[1]^, NR_EDX) then
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+ begin
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+ { Change:
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+ movl %eax,%edx
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+ sarl $31,%eax
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+ xorl %eax,%edx
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+ subl %eax,%edx
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+ (Instruction that uses %edx)
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+ (%eax deallocated)
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+ (%edx deallocated)
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+ To:
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+ cltd
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+ xorl %edx,%eax <-- Note the registers have swapped
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+ subl %edx,%eax
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+ (Instruction that uses %eax) <-- %eax rather than %edx
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+ }
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+
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
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+ UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
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+ UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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+
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+ if not RegUsedAfterInstruction(NR_EAX, hp3, TmpUsedRegs) then
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+ begin
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+ if GetNextInstruction(hp3, hp4) and
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+ not RegModifiedByInstruction(NR_EDX, hp4) and
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+ not RegUsedAfterInstruction(NR_EDX, hp4, TmpUsedRegs) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'abs() intrinsic optimisation', p);
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+
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+ taicpu(p).opcode := A_CDQ;
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+ taicpu(p).clearop(1);
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+ taicpu(p).clearop(0);
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+ taicpu(p).ops:=0;
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+
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+ AsmL.Remove(hp1);
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+ hp1.Free;
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+
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+ taicpu(hp2).loadreg(0, NR_EDX);
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+ taicpu(hp2).loadreg(1, NR_EAX);
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+
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+ taicpu(hp3).loadreg(0, NR_EDX);
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+ taicpu(hp3).loadreg(1, NR_EAX);
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+
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+ AllocRegBetween(NR_EAX, hp3, hp4, TmpUsedRegs);
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+ { Convert references in the following instruction (hp4) from %edx to %eax }
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+ for OperIdx := 0 to taicpu(hp4).ops - 1 do
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+ with taicpu(hp4).oper[OperIdx]^ do
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+ case typ of
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+ top_reg:
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+ if reg = NR_EDX then
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+ reg := NR_EAX;
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+ top_ref:
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+ begin
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+ if ref^.base = NR_EDX then
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+ ref^.base := NR_EAX;
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+ if ref^.index = NR_EDX then
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+ ref^.index := NR_EAX;
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+ end;
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+ else
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+ ;
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+ end;
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+ end;
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+ end;
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+{$else x86_64}
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+ end;
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+ end
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+ else if MatchOperand(taicpu(hp1).oper[0]^, 63) and
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+ { the use of %rdx also covers the opsize being S_Q }
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+ MatchOperand(taicpu(hp1).oper[1]^, NR_RDX) then
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+ begin
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+ { Note it has to be specifically "movq %rax,%rdx", and those specific sub-registers }
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+ if (taicpu(p).oper[0]^.reg = NR_RAX) and
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+ (taicpu(p).oper[1]^.reg = NR_RDX) then
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+ begin
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+ { Change:
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+ movq %rax,%rdx
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+ sarq $63,%rdx
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+ To:
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+ cqto
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovSar2Cqto', p);
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+ Asml.Remove(hp1);
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+ hp1.Free;
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+ taicpu(p).opcode := A_CQO;
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+ taicpu(p).opsize := S_NO;
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+ taicpu(p).clearop(1);
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+ taicpu(p).clearop(0);
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+ taicpu(p).ops:=0;
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+ Result := True;
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+ end
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+ else if (cs_opt_size in current_settings.optimizerswitches) and
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+ (taicpu(p).oper[0]^.reg = NR_RDX) and
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+ (taicpu(p).oper[1]^.reg = NR_RAX) then
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+ begin
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+ { Change:
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+ movq %rdx,%rax
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+ sarq $63,%rdx
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+ To:
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+ movq %rdx,%rax
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+ cqto
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+
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+ Note that this creates a dependency between the two instructions,
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+ so only perform if optimising for size.
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovSar2MovCqto', p);
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+ taicpu(hp1).opcode := A_CQO;
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+ taicpu(hp1).opsize := S_NO;
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+ taicpu(hp1).clearop(1);
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+ taicpu(hp1).clearop(0);
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+ taicpu(hp1).ops:=0;
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+{$endif x86_64}
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+ end;
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+ end;
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+ end
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+ else if MatchInstruction(hp1, A_MOV, []) and
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+ (taicpu(hp1).oper[1]^.typ = top_reg) then
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+ { Though "GetNextInstruction" could be factored out, along with
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+ the instructions that depend on hp2, it is an expensive call that
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+ should be delayed for as long as possible, hence we do cheaper
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+ checks first that are likely to be False. [Kit] }
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+ begin
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+
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+ if MatchOperand(taicpu(p).oper[1]^, NR_EDX) and
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+ (
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+ (
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+ (taicpu(hp1).oper[1]^.reg = NR_EAX) and
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+ (
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
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+ MatchOperand(taicpu(hp1).oper[0]^, NR_EDX)
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+ )
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+ ) or
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+ (
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+ (taicpu(hp1).oper[1]^.reg = NR_EDX) and
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+ (
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
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+ MatchOperand(taicpu(hp1).oper[0]^, NR_EAX)
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+ )
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+ )
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+ ) and
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+ GetNextInstruction(hp1, hp2) and
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+ MatchInstruction(hp2, A_SAR, []) and
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+ MatchOperand(taicpu(hp2).oper[0]^, 31) then
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+ begin
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+ if MatchOperand(taicpu(hp2).oper[1]^, NR_EDX) then
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+ begin
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+ { Change:
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+ movl r/m,%edx movl r/m,%eax movl r/m,%edx movl r/m,%eax
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+ movl %edx,%eax or movl %eax,%edx or movl r/m,%eax or movl r/m,%edx
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+ sarl $31,%edx sarl $31,%edx sarl $31,%edx sarl $31,%edx
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+ To:
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+ movl r/m,%eax <- Note the change in register
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+ cltd
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovMovSar2MovCltd', p);
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+
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+ AllocRegBetween(NR_EAX, p, hp1, UsedRegs);
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+ taicpu(p).loadreg(1, NR_EAX);
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+
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+ taicpu(hp1).opcode := A_CDQ;
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+ taicpu(hp1).clearop(1);
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+ taicpu(hp1).clearop(0);
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+ taicpu(hp1).ops:=0;
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+
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+ AsmL.Remove(hp2);
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+ hp2.Free;
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+(*
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+{$ifdef x86_64}
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+ end
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+ else if MatchOperand(taicpu(hp2).oper[1]^, NR_RDX) and
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+ { This code sequence does not get generated - however it might become useful
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+ if and when 128-bit signed integer types make an appearance, so the code
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+ is kept here for when it is eventually needed. [Kit] }
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+ (
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+ (
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+ (taicpu(hp1).oper[1]^.reg = NR_RAX) and
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+ (
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
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+ MatchOperand(taicpu(hp1).oper[0]^, NR_RDX)
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+ )
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+ ) or
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+ (
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+ (taicpu(hp1).oper[1]^.reg = NR_RDX) and
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+ (
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+ MatchOperand(taicpu(hp1).oper[0]^, taicpu(p).oper[0]^) or
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+ MatchOperand(taicpu(hp1).oper[0]^, NR_RAX)
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+ )
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+ )
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+ ) and
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+ GetNextInstruction(hp1, hp2) and
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+ MatchInstruction(hp2, A_SAR, [S_Q]) and
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+ MatchOperand(taicpu(hp2).oper[0]^, 63) and
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+ MatchOperand(taicpu(hp2).oper[1]^, NR_RDX) then
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+ begin
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+ { Change:
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+ movq r/m,%rdx movq r/m,%rax movq r/m,%rdx movq r/m,%rax
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+ movq %rdx,%rax or movq %rax,%rdx or movq r/m,%rax or movq r/m,%rdx
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+ sarq $63,%rdx sarq $63,%rdx sarq $63,%rdx sarq $63,%rdx
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+ To:
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+ movq r/m,%rax <- Note the change in register
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+ cqto
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+ }
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+ DebugMsg(SPeepholeOptimization + 'MovMovSar2MovCqto', p);
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+
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+ AllocRegBetween(NR_RAX, p, hp1, UsedRegs);
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+ taicpu(p).loadreg(1, NR_RAX);
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+
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+ taicpu(hp1).opcode := A_CQO;
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+ taicpu(hp1).clearop(1);
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+ taicpu(hp1).clearop(0);
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+ taicpu(hp1).ops:=0;
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+
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+ AsmL.Remove(hp2);
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+ hp2.Free;
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+{$endif x86_64}
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+*)
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+ end;
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+ end;
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+ end
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else if (taicpu(p).oper[0]^.typ = top_ref) and
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(hp1.typ = ait_instruction) and
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{ while the GetNextInstruction(hp1,hp2) call could be factored out,
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florian