- MIPS: completely removed trgcpu.add_constraints method.

  While it can be correct from some point of view, it does not prevent aliasing a single-precision register into upper half of double-precision one. This is currently handled by making only even floating-point registers available to RA. At the same time, it somehow (possibly due to another bug in RA) generates a lot of unnecessary moves, as if physical double-precision registers conflict with each other. Anyway, removing it considerably improves the code without regressions in the test suite.

git-svn-id: trunk@27999 -

compiler/mips/rgcpu.pas

@@ -34,7 +34,6 @@ unit rgcpu;
 
     type
       trgcpu=class(trgobj)
-        procedure add_constraints(reg:tregister);override;
         function get_spill_subreg(r : tregister) : tsubregister;override;
         procedure do_spill_read(list:tasmlist;pos:tai;const spilltemp:treference;tempreg:tregister);override;
         procedure do_spill_written(list:tasmlist;pos:tai;const spilltemp:treference;tempreg:tregister);override;
@@ -52,36 +51,6 @@ implementation
       verbose,cutils,
       cgobj;
 
-    procedure trgcpu.add_constraints(reg:tregister);
-      var
-        supreg,i : Tsuperregister;
-      begin
-        case getsubreg(reg) of
-          { Let 64bit floats conflict with all odd float regs }
-          R_SUBFD:
-            begin
-              supreg:=getsupreg(reg);
-              i:=RS_F1;
-              while (i<=RS_F31) do
-                begin
-                  add_edge(supreg,i);
-                  inc(i,2);
-                end;
-            end;
-          { Let 64bit ints conflict with all odd int regs }
-          R_SUBQ:
-            begin
-              supreg:=getsupreg(reg);
-              i:=RS_R1;
-              while (i<=RS_R31) do
-                begin
-                  add_edge(supreg,i);
-                  inc(i,2);
-                end;
-            end;
-        end;
-      end;
-
 
     function trgcpu.get_spill_subreg(r : tregister) : tsubregister;
       begin