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@@ -381,6 +381,8 @@ implementation
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if assigned(add_reg_instruction_hook) and (i in regset^) then
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add_reg_instruction_hook(self,newreg(R_MMREGISTER,i,regsetsubregtype));
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end;
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+ else
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+ internalerror(2019050932);
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end;
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end;
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end;
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@@ -1141,6 +1143,8 @@ implementation
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begin
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inc(extradataoffset,multiplier*(((tai_realconst(hp).savesize-4)+3) div 4));
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end;
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+ else
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+ ;
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end;
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{ check if the same constant has been already inserted into the currently handled list,
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if yes, reuse it }
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@@ -1200,6 +1204,8 @@ implementation
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begin
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inc(curinspos,multiplier*((tai_realconst(hp).savesize+3) div 4));
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end;
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+ else
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+ ;
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end;
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{ special case for case jump tables }
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penalty:=0;
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@@ -1270,6 +1276,8 @@ implementation
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or if we splitted them so split before }
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CheckLimit(hp,4);
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end;
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+ else
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+ ;
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end;
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end;
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@@ -1424,8 +1432,11 @@ implementation
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end;
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end;
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end;
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+ else;
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end;
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end;
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -1489,8 +1500,12 @@ implementation
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taicpu(curtai).ops:=2;
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end;
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end;
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+ else
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+ ;
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end;
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end;
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -1536,55 +1551,59 @@ implementation
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begin
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case curtai.typ of
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ait_instruction:
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- if IsIT(taicpu(curtai).opcode) then
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- begin
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- levels := GetITLevels(taicpu(curtai).opcode);
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- if levels < 4 then
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- begin
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- i:=levels;
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- hp1:=tai(curtai.Next);
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- while assigned(hp1) and
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- (i > 0) do
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- begin
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- if hp1.typ=ait_instruction then
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- begin
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- dec(i);
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- if (i = 0) and
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- mustbelast(hp1) then
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- begin
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- hp1:=nil;
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- break;
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- end;
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- end;
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- hp1:=tai(hp1.Next);
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- end;
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+ begin
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+ if IsIT(taicpu(curtai).opcode) then
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+ begin
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+ levels := GetITLevels(taicpu(curtai).opcode);
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+ if levels < 4 then
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+ begin
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+ i:=levels;
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+ hp1:=tai(curtai.Next);
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+ while assigned(hp1) and
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+ (i > 0) do
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+ begin
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+ if hp1.typ=ait_instruction then
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+ begin
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+ dec(i);
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+ if (i = 0) and
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+ mustbelast(hp1) then
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+ begin
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+ hp1:=nil;
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+ break;
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+ end;
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+ end;
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+ hp1:=tai(hp1.Next);
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+ end;
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- if assigned(hp1) then
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- begin
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- // We are pointing at the first instruction after the IT block
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- while assigned(hp1) and
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- (hp1.typ<>ait_instruction) do
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- hp1:=tai(hp1.Next);
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-
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- if assigned(hp1) and
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- (hp1.typ=ait_instruction) and
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- IsIT(taicpu(hp1).opcode) then
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- begin
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- if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
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- ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
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- (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
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- begin
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- taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
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- taicpu(hp1).opcode,
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- taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
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+ if assigned(hp1) then
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+ begin
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+ // We are pointing at the first instruction after the IT block
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+ while assigned(hp1) and
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+ (hp1.typ<>ait_instruction) do
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+ hp1:=tai(hp1.Next);
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+
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+ if assigned(hp1) and
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+ (hp1.typ=ait_instruction) and
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+ IsIT(taicpu(hp1).opcode) then
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+ begin
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+ if (levels+GetITLevels(taicpu(hp1).opcode) <= 4) and
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+ ((taicpu(curtai).oper[0]^.cc=taicpu(hp1).oper[0]^.cc) or
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+ (taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc))) then
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+ begin
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+ taicpu(curtai).opcode:=getMergedInstruction(taicpu(curtai).opcode,
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+ taicpu(hp1).opcode,
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+ taicpu(curtai).oper[0]^.cc=inverse_cond(taicpu(hp1).oper[0]^.cc));
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- list.Remove(hp1);
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- hp1.Free;
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- end;
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- end;
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- end;
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- end;
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- end;
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+ list.Remove(hp1);
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+ hp1.Free;
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+ end;
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+ end;
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+ end;
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+ end;
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+ end;
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+ end
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -1611,6 +1630,8 @@ implementation
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case taicpu(curtai).opcode of
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A_AND: taicpu(curtai).opcode:=A_BIC;
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A_BIC: taicpu(curtai).opcode:=A_AND;
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+ else
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+ internalerror(2019050931);
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end;
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taicpu(curtai).oper[2]^.val:=(not taicpu(curtai).oper[2]^.val) and $FFFFFFFF;
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end
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@@ -1623,10 +1644,14 @@ implementation
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case taicpu(curtai).opcode of
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A_ADD: taicpu(curtai).opcode:=A_SUB;
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A_SUB: taicpu(curtai).opcode:=A_ADD;
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+ else
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+ internalerror(2019050930);
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end;
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taicpu(curtai).oper[2]^.val:=-taicpu(curtai).oper[2]^.val;
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end;
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end;
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -1674,6 +1699,8 @@ implementation
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end;
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end;
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end;
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -1699,6 +1726,7 @@ implementation
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(taicpu(curtai).oper[2]^.typ=top_shifterop) then
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begin
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case taicpu(curtai).oper[2]^.shifterop^.shiftmode of
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+ SM_NONE: ;
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SM_LSL: taicpu(curtai).opcode:=A_LSL;
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SM_LSR: taicpu(curtai).opcode:=A_LSR;
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SM_ASR: taicpu(curtai).opcode:=A_ASR;
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@@ -1735,8 +1763,12 @@ implementation
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begin
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taicpu(curtai).opcode:=A_SVC;
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end;
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+ else
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+ ;
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end;
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end;
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+ else
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+ ;
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end;
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curtai:=tai(curtai.Next);
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@@ -2971,6 +3003,7 @@ implementation
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shift:=0;
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typ:=0;
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case oper[op]^.shifterop^.shiftmode of
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+ SM_None: ;
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SM_LSL: begin typ:=0; shift:=oper[op]^.shifterop^.shiftimm; end;
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SM_LSR: begin typ:=1; shift:=oper[op]^.shifterop^.shiftimm; if shift=32 then shift:=0; end;
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SM_ASR: begin typ:=2; shift:=oper[op]^.shifterop^.shiftimm; if shift=32 then shift:=0; end;
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@@ -3983,6 +4016,8 @@ implementation
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bytes:=bytes or ((Rd and $F) shl 12);
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bytes:=bytes or (((Rd and $10) shr 4) shl 22);
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end;
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+ else
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+ Message(asmw_e_invalid_opcode_and_operands);
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end;
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end;
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#$41,#$91: // VMRS/VMSR
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@@ -4143,6 +4178,8 @@ implementation
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d:=(rd shr 4) and 1;
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rd:=rd and $F;
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end;
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+ else
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+ internalerror(2019050929);
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end;
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m:=0;
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@@ -4163,6 +4200,8 @@ implementation
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m:=(rm shr 4) and 1;
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rm:=rm and $F;
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end;
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+ else
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+ internalerror(2019050928);
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end;
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bytes:=bytes or (Rd shl 12);
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@@ -4179,6 +4218,8 @@ implementation
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PF_F64S32,
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PF_F64U32:
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bytes:=bytes or (1 shl 8);
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+ else
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+ ;
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end;
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if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64] then
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@@ -4187,6 +4228,8 @@ implementation
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PF_S32F64,
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PF_S32F32:
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bytes:=bytes or (1 shl 16);
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+ else
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+ ;
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end;
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bytes:=bytes or (1 shl 18);
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@@ -4257,9 +4300,9 @@ implementation
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rn:=16;
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end;
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- else
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- Rn:=0;
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- message(asmw_e_invalid_opcode_and_operands);
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+ else
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+ Rn:=0;
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+ message(asmw_e_invalid_opcode_and_operands);
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end;
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case oppostfix of
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@@ -4271,10 +4314,10 @@ implementation
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bytes:=bytes or (1 shl 8);
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D:=(rd shr 4) and $1; Rd:=Rd and $F;
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end;
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- else
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- begin
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- D:=rd and $1; Rd:=Rd shr 1;
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- end;
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+ else
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+ begin
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+ D:=rd and $1; Rd:=Rd shr 1;
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+ end;
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end;
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case oppostfix of
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@@ -4283,6 +4326,8 @@ implementation
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PF_F64U16,PF_F32U16,
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PF_F32U32,PF_F64U32:
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bytes:=bytes or (1 shl 16);
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+ else
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+ ;
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end;
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if oppostfix in [PF_S32F32,PF_S32F64,PF_U32F32,PF_U32F64,PF_S16F32,PF_S16F64,PF_U16F32,PF_U16F64] then
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@@ -4335,6 +4380,8 @@ implementation
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bytes:=bytes or (1 shl 23);
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PF_DB,PF_DBS,PF_DBD,PF_DBX:
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bytes:=bytes or (2 shl 23);
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+ else
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+ ;
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end;
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case oppostfix of
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@@ -4343,6 +4390,8 @@ implementation
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bytes:=bytes or (1 shl 8);
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bytes:=bytes or (1 shl 0); // Offset is odd
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end;
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+ else
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+ ;
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end;
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dp_operation:=(oper[1]^.subreg=R_SUBFD);
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@@ -4634,6 +4683,8 @@ implementation
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bytes:=bytes or ((oper[2]^.val shr 2) and $7F);
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end;
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end;
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+ else
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+ internalerror(2019050926);
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end;
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end;
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#$65: { Thumb load/store }
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@@ -4770,6 +4821,8 @@ implementation
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else
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 8);
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end;
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+ else
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+ internalerror(2019050925);
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end;
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end;
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#$6A: { Thumb: IT }
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@@ -5375,6 +5428,8 @@ implementation
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case oppostfix of
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PF_None,PF_IA,PF_FD: bytes:=bytes or ($1 shl 23);
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PF_DB,PF_EA: bytes:=bytes or ($2 shl 23);
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+ else
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+ message1(asmw_e_invalid_opcode_and_operands, '"Invalid Postfix"');
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end;
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end;
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#$8D: { Thumb-2: BL/BLX }
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@@ -5525,6 +5580,9 @@ implementation
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PF_D: bytes:=bytes or (0 shl 22) or (1 shl 15);
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PF_E: bytes:=bytes or (1 shl 22) or (0 shl 15);
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PF_P: bytes:=bytes or (1 shl 22) or (1 shl 15);
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+ PF_EP: ;
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+ else
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+ message1(asmw_e_invalid_opcode_and_operands, '"Invalid postfix"');
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end;
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end
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else
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@@ -5599,6 +5657,7 @@ implementation
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end;
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case roundingmode of
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+ RM_NONE: ;
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RM_P: bytes:=bytes or (1 shl 5);
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RM_M: bytes:=bytes or (2 shl 5);
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RM_Z: bytes:=bytes or (3 shl 5);
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@@ -5626,6 +5685,7 @@ implementation
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bytes:=bytes or (getsupreg(oper[1]^.reg) shl 12);
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case roundingmode of
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+ RM_NONE: ;
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RM_P: bytes:=bytes or (1 shl 5);
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RM_M: bytes:=bytes or (2 shl 5);
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RM_Z: bytes:=bytes or (3 shl 5);
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@@ -5645,6 +5705,7 @@ implementation
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bytes:=bytes or (getsupreg(oper[1]^.reg) shl 0);
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case roundingmode of
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+ RM_NONE: ;
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RM_P: bytes:=bytes or (1 shl 5);
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RM_M: bytes:=bytes or (2 shl 5);
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RM_Z: bytes:=bytes or (3 shl 5);
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@@ -5674,6 +5735,8 @@ implementation
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|
|
Message(asmw_e_invalid_opcode_and_operands);
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end;
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|
end;
|
|
|
+ else
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|
|
+ Message1(asmw_e_invalid_opcode_and_operands, '"Unsupported opcode"');
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|
end;
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|
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end;
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|
|
#$fe: // No written data
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