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@@ -51,6 +51,18 @@ unit aoptx86;
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depend on the value in AH). }
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function Reg1ReadDependsOnReg2(reg1, reg2: tregister): boolean;
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+ { Replaces all references to AOldReg in a memory reference to ANewReg }
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+ class function ReplaceRegisterInRef(var ref: TReference; const AOldReg, ANewReg: TRegister): Boolean; static;
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+
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+ { Replaces all references to AOldReg in an operand to ANewReg }
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+ class function ReplaceRegisterInOper(const p: taicpu; const OperIdx: Integer; const AOldReg, ANewReg: TRegister): Boolean; static;
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+
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+ { Replaces all references to AOldReg in an instruction to ANewReg,
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+ except where the register is being written }
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+ function ReplaceRegisterInInstruction(const p: taicpu; const AOldReg, ANewReg: TRegister): Boolean;
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+
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+ function DeepMOVOpt(const p_mov: taicpu; const hp: taicpu): Boolean;
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+
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procedure DebugMsg(const s : string; p : tai);inline;
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class function IsExitCode(p : tai) : boolean; static;
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@@ -1506,6 +1518,188 @@ unit aoptx86;
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end;
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+ { Replaces all references to AOldReg in a memory reference to ANewReg }
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+ class function TX86AsmOptimizer.ReplaceRegisterInRef(var ref: TReference; const AOldReg, ANewReg: TRegister): Boolean;
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+ var
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+ OldSupReg: TSuperRegister;
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+ OldSubReg, MemSubReg: TSubRegister;
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+ begin
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+ Result := False;
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+ { For safety reasons, only check for exact register matches }
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+
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+ { Check base register }
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+ if (ref.base = AOldReg) then
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+ begin
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+ ref.base := ANewReg;
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+ Result := True;
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+ end;
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+
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+ { Check index register }
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+ if (ref.index = AOldReg) then
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+ begin
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+ ref.index := ANewReg;
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+ Result := True;
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+ end;
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+ end;
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+
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+
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+ { Replaces all references to AOldReg in an operand to ANewReg }
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+ class function TX86AsmOptimizer.ReplaceRegisterInOper(const p: taicpu; const OperIdx: Integer; const AOldReg, ANewReg: TRegister): Boolean;
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+ var
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+ OldSupReg, NewSupReg: TSuperRegister;
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+ OldSubReg, NewSubReg, MemSubReg: TSubRegister;
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+ OldRegType: TRegisterType;
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+ ThisOper: POper;
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+ begin
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+ ThisOper := p.oper[OperIdx]; { Faster to access overall }
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+ Result := False;
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+
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+ if (AOldReg = NR_NO) or (ANewReg = NR_NO) then
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+ InternalError(2020011801);
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+
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+ OldSupReg := getsupreg(AOldReg);
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+ OldSubReg := getsubreg(AOldReg);
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+ OldRegType := getregtype(AOldReg);
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+ NewSupReg := getsupreg(ANewReg);
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+ NewSubReg := getsubreg(ANewReg);
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+
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+ if OldRegType <> getregtype(ANewReg) then
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+ InternalError(2020011802);
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+
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+ if OldSubReg <> NewSubReg then
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+ InternalError(2020011803);
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+
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+ case ThisOper^.typ of
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+ top_reg:
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+ if (
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+ (ThisOper^.reg = AOldReg) or
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+ (
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+ (OldRegType = R_INTREGISTER) and
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+ (getsupreg(ThisOper^.reg) = OldSupReg) and
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+ (getregtype(ThisOper^.reg) = R_INTREGISTER) and
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+ (
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+ (getsubreg(ThisOper^.reg) <= OldSubReg)
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+{$ifndef x86_64}
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+ and (
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+ { Under i386 and i8086, ESI, EDI, EBP and ESP
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+ don't have an 8-bit representation }
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+ (getsubreg(ThisOper^.reg) >= R_SUBW) or
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+ not (NewSupReg in [RS_ESI, RS_EDI, RS_EBP, RS_ESP])
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+ )
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+{$endif x86_64}
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+ )
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+ )
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+ ) then
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+ begin
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+ ThisOper^.reg := newreg(getregtype(ANewReg), NewSupReg, getsubreg(p.oper[OperIdx]^.reg));;
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+ Result := True;
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+ end;
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+ top_ref:
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+ if ReplaceRegisterInRef(ThisOper^.ref^, AOldReg, ANewReg) then
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+ Result := True;
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+
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+ else
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+ ;
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+ end;
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+ end;
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+
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+
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+ { Replaces all references to AOldReg in an instruction to ANewReg }
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+ function TX86AsmOptimizer.ReplaceRegisterInInstruction(const p: taicpu; const AOldReg, ANewReg: TRegister): Boolean;
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+ const
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+ ReadFlag: array[0..3] of TInsChange = (Ch_Rop1, Ch_Rop2, Ch_Rop3, Ch_Rop4);
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+ var
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+ OperIdx: Integer;
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+ begin
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+ Result := False;
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+
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+ for OperIdx := 0 to p.ops - 1 do
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+ if (ReadFlag[OperIdx] in InsProp[p.Opcode].Ch) and
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+ { The shift and rotate instructions can only use CL }
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+ not (
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+ (OperIdx = 0) and
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+ { This second condition just helps to avoid unnecessarily
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+ calling MatchInstruction for 10 different opcodes }
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+ (p.oper[0]^.reg = NR_CL) and
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+ MatchInstruction(p, [A_RCL, A_RCR, A_ROL, A_ROR, A_SAL, A_SAR, A_SHL, A_SHLD, A_SHR, A_SHRD], [])
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+ ) then
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+ Result := ReplaceRegisterInOper(p, OperIdx, AOldReg, ANewReg) or Result;
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+ end;
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+
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+
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+ function TX86AsmOptimizer.DeepMOVOpt(const p_mov: taicpu; const hp: taicpu): Boolean;
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+ var
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+ CurrentReg, ReplaceReg: TRegister;
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+ SubReg: TSubRegister;
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+ begin
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+ Result := False;
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+
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+ ReplaceReg := taicpu(p_mov).oper[0]^.reg;
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+ CurrentReg := taicpu(p_mov).oper[1]^.reg;
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+
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+ case hp.opcode of
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+ A_FSTSW, A_FNSTSW,
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+ A_IN, A_INS, A_OUT, A_OUTS,
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+ A_CMPS, A_LODS, A_MOVS, A_SCAS, A_STOS:
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+ { These routines have explicit operands, but they are restricted in
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+ what they can be (e.g. IN and OUT can only read from AL, AX or
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+ EAX. }
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+ Exit;
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+
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+ A_IMUL:
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+ begin
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+ { The 1-operand version writes to implicit registers
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+ The 2-operand version reads from the first operator, and reads
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+ from and writes to the second (equivalent to Ch_ROp1, ChRWOp2).
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+ the 3-operand version reads from a register that it doesn't write to
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+ }
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+ case hp.ops of
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+ 1:
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+ if (
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+ (
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+ (hp.opsize = S_B) and (getsupreg(CurrentReg) <> RS_EAX)
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+ ) or
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+ not (getsupreg(CurrentReg) in [RS_EAX, RS_EDX])
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+ ) and ReplaceRegisterInOper(hp, 0, CurrentReg, ReplaceReg) then
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+ begin
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+ Result := True;
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+ DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 1)', hp);
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+ AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
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+ end;
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+ 2:
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+ { Only modify the first parameter }
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+ if ReplaceRegisterInOper(hp, 0, CurrentReg, ReplaceReg) then
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+ begin
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+ Result := True;
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+ DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 2)', hp);
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+ AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
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+ end;
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+ 3:
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+ { Only modify the second parameter }
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+ if ReplaceRegisterInOper(hp, 1, CurrentReg, ReplaceReg) then
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+ begin
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+ Result := True;
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+ DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovIMul2MovIMul 3)', hp);
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+ AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
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+ end;
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+ else
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+ InternalError(2020012901);
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+ end;
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+ end;
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+
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+ else
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+ if (hp.ops > 0) and
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+ ReplaceRegisterInInstruction(hp, CurrentReg, ReplaceReg) then
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+ begin
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+ Result := True;
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+ DebugMsg(SPeepholeOptimization + debug_regname(CurrentReg) + ' = ' + debug_regname(ReplaceReg) + '; changed to minimise pipeline stall (MovXXX2MovXXX)', hp);
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+
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+ AllocRegBetween(ReplaceReg, p_mov, hp, UsedRegs);
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+ end;
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+ end;
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+ end;
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+
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+
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function TX86AsmOptimizer.OptPass1MOV(var p : tai) : boolean;
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var
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hp1, hp2: tai;
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@@ -1536,6 +1730,146 @@ unit aoptx86;
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if not GetNextInstruction_p or (hp1.typ <> ait_instruction) then
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Exit;
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+ { Look for:
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+ mov %reg1,%reg2
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+ ??? %reg2,r/m
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+ Change to:
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+ mov %reg1,%reg2
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+ ??? %reg1,r/m
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+ }
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+ if MatchOpType(taicpu(p), top_reg, top_reg) then
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+ begin
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+ CurrentReg := taicpu(p).oper[1]^.reg;
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+
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+ if RegReadByInstruction(CurrentReg, hp1) and
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+ DeepMOVOpt(taicpu(p), taicpu(hp1)) then
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+ begin
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
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+
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+ if not RegUsedAfterInstruction(CurrentReg, hp1, TmpUsedRegs) and
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+ { Just in case something didn't get modified (e.g. an
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+ implicit register) }
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+ not RegReadByInstruction(CurrentReg, hp1) then
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+ begin
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+ { We can remove the original MOV }
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+ DebugMsg(SPeepholeOptimization + 'Mov2Nop 3 done',p);
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+ Asml.Remove(p);
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+ p.Free;
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+ p := hp1;
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+
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+ { TmpUsedRegs contains the results of "UpdateUsedRegs(tai(p.Next))" already,
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+ so just restore it to UsedRegs instead of calculating it again }
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+ RestoreUsedRegs(TmpUsedRegs);
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+ Result := True;
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+ Exit;
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+ end;
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+
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+ { If we know a MOV instruction has become a null operation, we might as well
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+ get rid of it now to save time. }
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+ if (taicpu(hp1).opcode = A_MOV) and
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+ (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[0]^.reg) and
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+ { Just being a register is enough to confirm it's a null operation }
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+ (taicpu(hp1).oper[0]^.typ = top_reg) then
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+ begin
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+
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+ Result := True;
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+
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+ { Speed-up to reduce a pipeline stall... if we had something like...
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+
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+ movl %eax,%edx
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+ movw %dx,%ax
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+
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+ ... the second instruction would change to movw %ax,%ax, but
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+ given that it is now %ax that's active rather than %eax,
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+ penalties might occur due to a partial register write, so instead,
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+ change it to a MOVZX instruction when optimising for speed.
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+ }
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+ if not (cs_opt_size in current_settings.optimizerswitches) and
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+{$ifdef i8086}
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+ { MOVZX was only introduced on the 386 }
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+ (current_settings.cputype >= cpu_386) and
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+{$endif i8086}
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+ (
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+ (taicpu(hp1).opsize < taicpu(p).opsize)
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+{$ifdef x86_64}
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+ { operations already implicitly set the upper 64 bits to zero }
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+ and not ((taicpu(hp1).opsize = S_L) and (taicpu(p).opsize = S_Q))
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+{$endif x86_64}
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+ ) then
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+ begin
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+ CurrentReg := taicpu(hp1).oper[1]^.reg;
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+
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+ DebugMsg(SPeepholeOptimization + 'Zero-extension to minimise pipeline stall (Mov2Movz)',hp1);
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+ case taicpu(p).opsize of
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+ S_W:
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+ if taicpu(hp1).opsize = S_B then
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+ taicpu(hp1).opsize := S_BW
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+ else
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+ InternalError(2020012911);
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+ S_L{$ifdef x86_64}, S_Q{$endif x86_64}:
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+ case taicpu(hp1).opsize of
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+ S_B:
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+ taicpu(hp1).opsize := S_BL;
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+ S_W:
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+ taicpu(hp1).opsize := S_WL;
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+ else
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+ InternalError(2020012912);
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+ end;
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+ else
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+ InternalError(2020012910);
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+ end;
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+
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+ taicpu(hp1).opcode := A_MOVZX;
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+ taicpu(hp1).oper[1]^.reg := newreg(getregtype(CurrentReg), getsupreg(CurrentReg), R_SUBD)
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+ end
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+ else
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+ begin
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+ GetNextInstruction_p := GetNextInstruction(hp1, hp2);
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+ DebugMsg(SPeepholeOptimization + 'Mov2Nop 4 done',hp1);
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+ asml.remove(hp1);
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+ hp1.free;
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+
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+ { The instruction after what was hp1 is now the immediate next instruction,
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+ so we can continue to make optimisations if it's present }
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+ if not GetNextInstruction_p or (hp2.typ <> ait_instruction) then
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+ Exit;
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+
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+ hp1 := hp2;
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+ end;
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+ end;
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+
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+ end;
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+ end;
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+
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+ { Depending on the DeepMOVOpt above, it may turn out that hp1 completely
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+ overwrites the original destination register. e.g.
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+
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+ movl %reg1d,%reg2d
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+ movslq %reg1d,%reg2q
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+
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+ In this case, we can remove the MOV
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+ }
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+ if (taicpu(p).oper[1]^.typ = top_reg) and
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+ MatchInstruction(hp1, [A_LEA, A_MOV, A_MOVSX, A_MOVZX{$ifdef x86_64}, A_MOVSXD{$endif x86_64}], []) and
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+ { The RegInOp check makes sure that movb r/m,%reg1b; movzbl %reg1b,%reg1l"
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+ and "movl r/m,%reg1; leal $1(%reg1,%reg2),%reg1" etc. are not incorrectly
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+ optimised }
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+ (taicpu(hp1).oper[1]^.typ = top_reg) and
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+ not RegInOp(taicpu(p).oper[1]^.reg, taicpu(hp1).oper[0]^) and
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+ Reg1WriteOverwritesReg2Entirely(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'Mov2Nop 5 done',p);
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+ { take care of the register (de)allocs following p }
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+ UpdateUsedRegs(tai(p.next));
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+ asml.remove(p);
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+ p.free;
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+ p:=hp1;
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+ Result := True;
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+ Exit;
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+ end;
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+
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if (taicpu(hp1).opcode = A_AND) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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MatchOpType(taicpu(hp1),top_const,top_reg) then
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florian