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@@ -1,9 +1,8 @@
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{
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$Id$
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- Copyright (c) 1998-2000 by Florian Klaempfl, Carl Eric Codere
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+ Copyright (c) 1998-2002 by Florian Klaempfl
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- This unit implements an types and classes specific for the
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- MC68000/MC68020
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+ Contains the base types for the PowerPC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@@ -21,74 +20,88 @@
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****************************************************************************
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}
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+{ This Unit contains the base types for the PowerPC
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+}
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unit cpubase;
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- interface
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+{$i fpcdefs.inc}
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- uses
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- cobjects,aasm,globtype;
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+interface
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- const
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- { if real fpu is used }
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- { otherwise maps to }
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- { s32real. }
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- extended_size = 12;
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+uses
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+ strings,cutils,cclasses,aasmbase,cpuinfo,cginfo;
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+
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+
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+{*****************************************************************************
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+ Assembler Opcodes
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+*****************************************************************************}
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type
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{ warning: CPU32 opcodes are not fully compatible with the MC68020. }
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{ 68000 only opcodes }
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- tasmop = (A_ABCD,
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- A_ADD,A_ADDA,A_ADDI,A_ADDQ,A_ADDX,A_AND,A_ANDI,
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- A_ASL,A_ASR,A_BCC,A_BCS,A_BEQ,A_BGE,A_BGT,A_BHI,
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- A_BLE,A_BLS,A_BLT,A_BMI,A_BNE,A_BPL,A_BVC,A_BVS,
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- A_BCHG,A_BCLR,A_BRA,A_BSET,A_BSR,A_BTST,A_CHK,
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- A_CLR,A_CMP,A_CMPA,A_CMPI,A_CMPM,A_DBCC,A_DBCS,A_DBEQ,A_DBGE,
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- A_DBGT,A_DBHI,A_DBLE,A_DBLS,A_DBLT,A_DBMI,A_DBNE,A_DBRA,
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- A_DBPL,A_DBT,A_DBVC,A_DBVS,A_DBF,A_DIVS,A_DIVU,
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- A_EOR,A_EORI,A_EXG,A_ILLEGAL,A_EXT,A_JMP,A_JSR,
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- A_LEA,A_LINK,A_LSL,A_LSR,A_MOVE,A_MOVEA,A_MOVEI,A_MOVEQ,
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- A_MOVEM,A_MOVEP,A_MULS,A_MULU,A_NBCD,A_NEG,A_NEGX,
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- A_NOP,A_NOT,A_OR,A_ORI,A_PEA,A_ROL,A_ROR,A_ROXL,
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- A_ROXR,A_RTR,A_RTS,A_SBCD,A_SCC,A_SCS,A_SEQ,A_SGE,
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- A_SGT,A_SHI,A_SLE,A_SLS,A_SLT,A_SMI,A_SNE,
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- A_SPL,A_ST,A_SVC,A_SVS,A_SF,A_SUB,A_SUBA,A_SUBI,A_SUBQ,
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- A_SUBX,A_SWAP,A_TAS,A_TRAP,A_TRAPV,A_TST,A_UNLK,
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- A_RTE,A_RESET,A_STOP,
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- { MC68010 instructions }
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- A_BKPT,A_MOVEC,A_MOVES,A_RTD,
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- { MC68020 instructions }
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- A_BFCHG,A_BFCLR,A_BFEXTS,A_BFEXTU,A_BFFFO,
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- A_BFINS,A_BFSET,A_BFTST,A_CALLM,A_CAS,A_CAS2,
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- A_CHK2,A_CMP2,A_DIVSL,A_DIVUL,A_EXTB,A_PACK,A_RTM,
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- A_TRAPCC,A_TRACS,A_TRAPEQ,A_TRAPF,A_TRAPGE,A_TRAPGT,
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- A_TRAPHI,A_TRAPLE,A_TRAPLS,A_TRAPLT,A_TRAPMI,A_TRAPNE,
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- A_TRAPPL,A_TRAPT,A_TRAPVC,A_TRAPVS,A_UNPK,
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- { FPU Processor instructions - directly supported only. }
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- { IEEE aware and misc. condition codes not supported }
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- A_FABS,A_FADD,
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- A_FBEQ,A_FBNE,A_FBNGT,A_FBGT,A_FBGE,A_FBNGE,
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- A_FBLT,A_FBNLT,A_FBLE,A_FBGL,A_FBNGL,A_FBGLE,A_FBNGLE,
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- A_FDBEQ,A_FDBNE,A_FDBGT,A_FDBNGT,A_FDBGE,A_FDBNGE,
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- A_FDBLT,A_FDBNLT,A_FDBLE,A_FDBGL,A_FDBNGL,A_FDBGLE,A_FBDNGLE,
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- A_FSEQ,A_FSNE,A_FSGT,A_FSNGT,A_FSGE,A_FSNGE,
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- A_FSLT,A_FSNLT,A_FSLE,A_FSGL,A_FSNGL,A_FSGLE,A_FSNGLE,
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- A_FCMP,A_FDIV,A_FMOVE,A_FMOVEM,
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- A_FMUL,A_FNEG,A_FNOP,A_FSQRT,A_FSUB,A_FSGLDIV,
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- A_FSFLMUL,A_FTST,
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- A_FTRAPEQ,A_FTRAPNE,A_FTRAPGT,A_FTRAPNGT,A_FTRAPGE,A_FTRAPNGE,
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- A_FTRAPLT,A_FTRAPNLT,A_FTRAPLE,A_FTRAPGL,A_FTRAPNGL,A_FTRAPGLE,A_FTRAPNGLE,
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- { Protected instructions }
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- A_CPRESTORE,A_CPSAVE,
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- { FPU Unit protected instructions }
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- { and 68030/68851 common MMU instructions }
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- { (this may include 68040 MMU instructions) }
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- A_FRESTORE,A_FSAVE,A_PFLUSH,A_PFLUSHA,A_PLOAD,A_PMOVE,A_PTEST,
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- { Useful for assembly langage output }
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- A_LABEL,A_NONE);
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-
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- { enumeration for registers, don't change the }
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- { order of this table }
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- { Registers which can and will be used by the compiler }
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+ tasmop = (a_abcd,
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+ a_add,a_adda,a_addi,a_addq,a_addx,a_and,a_andi,
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+ a_asl,a_asr,a_bcc,a_bcs,a_beq,a_bge,a_bgt,a_bhi,
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+ a_ble,a_bls,a_blt,a_bmi,a_bne,a_bpl,a_bvc,a_bvs,
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+ a_bchg,a_bclr,a_bra,a_bset,a_bsr,a_btst,a_chk,
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+ a_clr,a_cmp,a_cmpa,a_cmpi,a_cmpm,a_dbcc,a_dbcs,a_dbeq,a_dbge,
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+ a_dbgt,a_dbhi,a_dble,a_dbls,a_dblt,a_dbmi,a_dbne,a_dbra,
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+ a_dbpl,a_dbt,a_dbvc,a_dbvs,a_dbf,a_divs,a_divu,
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+ a_eor,a_eori,a_exg,a_illegal,a_ext,a_jmp,a_jsr,
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+ a_lea,a_link,a_lsl,a_lsr,a_move,a_movea,a_movei,a_moveq,
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+ a_movem,a_movep,a_muls,a_mulu,a_nbcd,a_neg,a_negx,
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+ a_nop,a_not,a_or,a_ori,a_pea,a_rol,a_ror,a_roxl,
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+ a_roxr,a_rtr,a_rts,a_sbcd,a_scc,a_scs,a_seq,a_sge,
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+ a_sgt,a_shi,a_sle,a_sls,a_slt,a_smi,a_sne,
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+ a_spl,a_st,a_svc,a_svs,a_sf,a_sub,a_suba,a_subi,a_subq,
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+ a_subx,a_swap,a_tas,a_trap,a_trapv,a_tst,a_unlk,
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+ a_rte,a_reset,a_stop,
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+ { mc68010 instructions }
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+ a_bkpt,a_movec,a_moves,a_rtd,
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+ { mc68020 instructions }
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+ a_bfchg,a_bfclr,a_bfexts,a_bfextu,a_bfffo,
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+ a_bfins,a_bfset,a_bftst,a_callm,a_cas,a_cas2,
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+ a_chk2,a_cmp2,a_divsl,a_divul,a_extb,a_pack,a_rtm,
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+ a_trapcc,a_tracs,a_trapeq,a_trapf,a_trapge,a_trapgt,
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+ a_traphi,a_traple,a_trapls,a_traplt,a_trapmi,a_trapne,
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+ a_trappl,a_trapt,a_trapvc,a_trapvs,a_unpk,
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+ { fpu processor instructions - directly supported only. }
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+ { ieee aware and misc. condition codes not supported }
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+ a_fabs,a_fadd,
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+ a_fbeq,a_fbne,a_fbngt,a_fbgt,a_fbge,a_fbnge,
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+ a_fblt,a_fbnlt,a_fble,a_fbgl,a_fbngl,a_fbgle,a_fbngle,
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+ a_fdbeq,a_fdbne,a_fdbgt,a_fdbngt,a_fdbge,a_fdbnge,
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+ a_fdblt,a_fdbnlt,a_fdble,a_fdbgl,a_fdbngl,a_fdbgle,a_fbdngle,
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+ a_fseq,a_fsne,a_fsgt,a_fsngt,a_fsge,a_fsnge,
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+ a_fslt,a_fsnlt,a_fsle,a_fsgl,a_fsngl,a_fsgle,a_fsngle,
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+ a_fcmp,a_fdiv,a_fmove,a_fmovem,
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+ a_fmul,a_fneg,a_fnop,a_fsqrt,a_fsub,a_fsgldiv,
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+ a_fsflmul,a_ftst,
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+ a_ftrapeq,a_ftrapne,a_ftrapgt,a_ftrapngt,a_ftrapge,a_ftrapnge,
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+ a_ftraplt,a_ftrapnlt,a_ftraple,a_ftrapgl,a_ftrapngl,a_ftrapgle,a_ftrapngle,
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+ { protected instructions }
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+ a_cprestore,a_cpsave,
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+ { fpu unit protected instructions }
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+ { and 68030/68851 common mmu instructions }
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+ { (this may include 68040 mmu instructions) }
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+ a_frestore,a_fsave,a_pflush,a_pflusha,a_pload,a_pmove,a_ptest,
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+ { useful for assembly langage output }
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+ a_label,a_none);
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+
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+ {# This should define the array of instructions as string }
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+ op2strtable=array[tasmop] of string[8];
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+
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+ Const
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+ {# First value of opcode enumeration }
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+ firstop = low(tasmop);
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+ {# Last value of opcode enumeration }
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+ lastop = high(tasmop);
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+
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+{*****************************************************************************
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+ Registers
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+*****************************************************************************}
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+
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+ type
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tregister = (
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R_NO,R_D0,R_D1,R_D2,R_D3,R_D4,R_D5,R_D6,R_D7,
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R_A0,R_A1,R_A2,R_A3,R_A4,R_A5,R_A6,R_SP,
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@@ -100,1530 +113,519 @@ unit cpubase;
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{ other - not used in reg2str }
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R_DEFAULT_SEG);
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- { S_NO = No Size of operand }
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- { S_B = Byte size operand }
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- { S_W = Word size operand }
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- { S_L = DWord size operand }
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- { USED FOR conversions in x86}
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- { S_BW = Byte to word }
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- { S_BL = Byte to long }
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- { S_WL = Word to long }
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- { Floating point types }
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- { S_FS = single type (32 bit) }
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- { S_FL = double/64bit integer }
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- { S_FX = Extended type }
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- { S_IS = integer on 16 bits }
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- { S_IL = integer on 32 bits }
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- { S_IQ = integer on 64 bits }
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- topsize = (S_NO,S_B,S_W,S_L,S_BW,S_BL,S_WL,
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- S_FS,S_FL,S_FX,S_IS,S_IL,S_IQ);
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-
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- plocation = ^tlocation;
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-
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- { information about the location of an operand }
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- { LOC_FPU FPU registers = Dn if emulation }
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- { LOC_REGISTER in a processor register }
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- { LOC_MEM in the memory }
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- { LOC_REFERENCE like LOC_MEM, but lvalue }
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- { LOC_JUMP nur bool'sche Resultate, Sprung zu false- oder }
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- { truelabel }
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- { LOC_FLAGS nur bool'sche Rsultate, Flags sind gesetzt }
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- { LOC_CREGISTER register which shouldn't be modified }
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- { LOC_INVALID added for tracking problems}
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-
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- tloc = (LOC_INVALID,LOC_FPU,LOC_REGISTER,LOC_MEM,LOC_REFERENCE,LOC_JUMP,
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- LOC_FLAGS,LOC_CREGISTER);
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-
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- tregisterlist = set of tregister;
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-
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- { F_E = Equal
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- F_NE = Not Equal
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- F_G = Greater then
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- F_L = Less then
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- F_GE = Greater or equal then
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- F_LE = Less or equal then
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- F_C = Carry
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- F_NC = Not Carry
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- F_A = Above
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- F_AE = Above or Equal
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- F_B = Below
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- F_BE = Below or Equal
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- other flags:
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- FL_xxx = floating type flags .
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-
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- }
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- tresflags = (F_E,F_NE,F_G,F_L,F_GE,F_LE,F_C,F_NC,
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- F_A,F_AE,F_B,F_BE);
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- { floating type flags used by FBCC are auotmatically converted }
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- { to standard condition codes }
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-{ FL_E,FL_NE,FL_A,FL_AE,FL_B,FL_BE);}
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-
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- preference = ^treference;
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-
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- { direction of address register : }
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- { (An) (An)+ -(An) }
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- tdirection = (dir_none,dir_inc,dir_dec);
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-
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- treference = record
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- base,segment,index : tregister;
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- offset : longint;
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- symbol : pstring;
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- { indexed increment and decrement mode }
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- { (An)+ and -(An) }
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- direction : tdirection;
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- { a constant is also a treference, this makes the code generator }
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- { easier }
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- isintvalue : boolean;
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- scalefactor : byte;
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- end;
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-
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- tlocation = record
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- case loc : tloc of
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- { segment in reference at the same place as in loc_register }
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- LOC_REGISTER,LOC_CREGISTER : (register,segment : tregister);
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- LOC_MEM,LOC_REFERENCE : (reference : treference);
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- LOC_FPU : (fpureg:tregister);
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- LOC_JUMP : ();
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- LOC_FLAGS : (resflags : tresflags);
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- LOC_INVALID : ();
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- end;
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-
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- pcsymbol = ^tcsymbol;
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-
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- tcsymbol = record
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- symbol : pchar;
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- offset : longint;
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- end;
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-
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- const
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- {----------------------------------------------------------------------}
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- { F_E = Equal }
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- { F_NE = Not Equal }
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- { F_G = Greater then }
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- { F_L = Less then }
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- { F_GE = Greater or equal then }
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- { F_LE = Less or equal then }
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- { F_C = Carry = C }
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- { F_NC = Not Carry = not C }
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- { F_A = Above = not C and not Z }
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- { F_AE = Above or Equal = not C }
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- { F_B = Below = C }
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- { F_BE = Below or Equal = C or Z }
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- { FL_E = Floating point equal = Z }
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- { FL_NE = Floating point Not equal = not Z }
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- { FL_A = Floating point above = }
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- { FL_AE = Floating point above or equal = }
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- { FL_B = Floating point below = }
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- { FL_BE = Floating point below or equal = }
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-
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- { THE ORDER OF THIS TABLE SHOULD NOT BE CHANGED! }
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- flag_2_jmp: array[F_E..F_BE] of tasmop =
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- (A_BEQ,A_BNE,A_BGT,A_BLT,A_BGE,A_BLE,A_BCS,A_BCC,
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- A_BHI,A_BCC,A_BCS,A_BLS);
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- { floating point jumps - CURRENTLY NOT USED }
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-{ A_FBEQ,A_FBNE,A_FBGT,A_FBGE,A_FBLT,A_FBLE); }
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-
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- { don't change the order of this table, it is related to }
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- { the flags table. }
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-
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- flag_2_set: array[F_E..F_BE] of tasmop =
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- (A_SEQ,A_SNE,A_SGT,A_SLT,A_SGE,A_SLE,A_SCS,A_SCC,
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- A_SHI,A_SCC,A_SCS,A_SLS);
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-
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-
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- { operand types }
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- top_none = 0;
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- top_reg = 1;
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- top_ref = 2;
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- top_reglist = 5;
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-
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- { a constant can be also written as treference }
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- top_const = 3;
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-
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- { this is for calls }
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- top_symbol = 4;
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-
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- {This constant is an alias for the stack pointer, as it's name may
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- differ from processor to processor.}
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- stack_pointer_reg = R_SP;
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-
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- frame_pointer_reg = R_A6;
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-
|
|
|
- {This constant is an alias for the accumulator, as it's name may
|
|
|
- differ from processor to processor.}
|
|
|
- accumulator = R_D0;
|
|
|
-
|
|
|
- type
|
|
|
-
|
|
|
- pai_labeled = ^tai_labeled;
|
|
|
-
|
|
|
- tai_labeled = object(tai)
|
|
|
- _operator : tasmop;
|
|
|
- _op1: tregister;
|
|
|
- lab : pasmlabel;
|
|
|
- constructor init(op : tasmop; l : pasmlabel);
|
|
|
- constructor init_reg(op: tasmop; l : pasmlabel; reg: tregister);
|
|
|
- destructor done;virtual;
|
|
|
- end;
|
|
|
-
|
|
|
- paicpu = ^taicpu;
|
|
|
-
|
|
|
- taicpu = object(tai)
|
|
|
- { this isn't a proper style, but not very memory expensive }
|
|
|
- op1,op2,op3 : pointer;
|
|
|
- _operator : tasmop;
|
|
|
- op1t,op2t,op3t : byte;
|
|
|
- size : topsize;
|
|
|
- reglist: set of tregister;
|
|
|
- constructor op_none(op : tasmop;_size : topsize);
|
|
|
-
|
|
|
- constructor op_reg(op : tasmop;_size : topsize;_op1 : tregister);
|
|
|
- constructor op_const(op : tasmop;_size : topsize;_op1 : longint);
|
|
|
- constructor op_ref(op : tasmop;_size : topsize;_op1 : preference);
|
|
|
- constructor op_loc(op : tasmop;_size : topsize;_op1 : tlocation);
|
|
|
-
|
|
|
- constructor op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
|
|
|
- constructor op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;_op2 : preference);
|
|
|
- constructor op_reg_loc(op : tasmop;_size : topsize;_op1 : tregister;_op2 : tlocation);
|
|
|
- constructor op_loc_reg(op : tasmop;_size : topsize;_op1 : tlocation;_op2 : tregister);
|
|
|
-
|
|
|
- constructor op_const_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister);
|
|
|
- { this combination is needed by ENTER }
|
|
|
- constructor op_const_const(op : tasmop;_size : topsize;_op1,_op2 : longint);
|
|
|
- constructor op_const_ref(op : tasmop;_size : topsize;_op1 : longint;_op2 : preference);
|
|
|
- constructor op_const_loc(op : tasmop;_size : topsize;_op1 : longint;_op2 : tlocation);
|
|
|
-
|
|
|
- constructor op_ref_reg(op : tasmop;_size : topsize;_op1 : preference;_op2 : tregister);
|
|
|
- { this is only allowed if _op1 is an int value (_op1^.isintvalue=true) }
|
|
|
- constructor op_ref_ref(op : tasmop;_size : topsize;_op1,_op2 : preference);
|
|
|
- {
|
|
|
- constructor op_ref_loc(op : tasmop;_size : topsize;_op1 : preference;_op2 : tlcation);}
|
|
|
-
|
|
|
- constructor op_const_reg_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister;_op3 : tregister);
|
|
|
-
|
|
|
- { used by MC68020 mul/div }
|
|
|
- constructor op_reg_reg_Reg(op: tasmop;_size: topsize;_op1: tregister; _op2: tregister; _op3: tregister);
|
|
|
-
|
|
|
- { used by link }
|
|
|
- constructor op_reg_const(op: tasmop; _size: topsize; _op1: tregister; _op2: longint);
|
|
|
- { this is for CALL etc. }
|
|
|
- { symbol is replaced by the address of symbol }
|
|
|
- { so op_csymbol(A_PUSH,S_L,strnew('P')); generates }
|
|
|
- { an instruction which pushes the address of P }
|
|
|
- { to the stack }
|
|
|
- constructor op_csymbol(op : tasmop;_size : topsize;_op1 : pcsymbol);
|
|
|
- constructor op_csymbol_reg(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : tregister);
|
|
|
- constructor op_csymbol_ref(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : preference);
|
|
|
- constructor op_csymbol_loc(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : tlocation);
|
|
|
-
|
|
|
- constructor op_ref_reglist(op: tasmop; _size : topsize; _op1: preference;_op2: tregisterlist);
|
|
|
- constructor op_reglist_ref(op: tasmop; _size : topsize; _op1: tregisterlist; _op2: preference);
|
|
|
-
|
|
|
- destructor done;virtual;
|
|
|
- end;
|
|
|
+ {# Set type definition for registers }
|
|
|
+ tregisterset = set of tregister;
|
|
|
|
|
|
- const
|
|
|
- maxvarregs = 5;
|
|
|
- maxfpuvarregs = 8;
|
|
|
- varregs : array[1..maxvarregs] of tregister =
|
|
|
- (R_D2,R_D3,R_D4,R_D5,R_D7);
|
|
|
- fpuvarregs : array[1..maxfpuvarregs] of tregister =
|
|
|
- (R_FP0,R_FP1,R_FP2,R_FP3,R_FP4,R_FP5,R_FP6,
|
|
|
- R_FP7);
|
|
|
-
|
|
|
-
|
|
|
- { resets all values of ref to defaults }
|
|
|
- procedure reset_reference(var ref : treference);
|
|
|
-
|
|
|
- { set mostly used values of a new reference }
|
|
|
- function new_reference(base : tregister;offset : longint) : preference;
|
|
|
-
|
|
|
- { same as reset_reference, but symbol is disposed }
|
|
|
- { use this only for already used references }
|
|
|
- procedure clear_reference(var ref : treference);
|
|
|
-
|
|
|
- procedure disposereference(var r : preference);
|
|
|
-
|
|
|
- function newreference(const r : treference) : preference;
|
|
|
-
|
|
|
- { generates an help record for constants }
|
|
|
- function newcsymbol(const s : string;l : longint) : pcsymbol;
|
|
|
-
|
|
|
- const
|
|
|
- ao_unknown = $0;
|
|
|
- { 8 bit reg }
|
|
|
- ao_reg8 = $1;
|
|
|
- { 16 bit reg }
|
|
|
- ao_reg16 = $2;
|
|
|
- { 32 bit reg }
|
|
|
- ao_reg32 = $4;
|
|
|
- ao_reg = (ao_reg8 or ao_reg16 or ao_reg32);
|
|
|
-
|
|
|
-
|
|
|
- { for push/pop operands }
|
|
|
- ao_wordreg = (ao_reg16 or ao_reg32);
|
|
|
- ao_imm8 = $8; { 8 bit immediate }
|
|
|
- ao_imm8S = $10; { 8 bit immediate sign extended }
|
|
|
- ao_imm16 = $20; { 16 bit immediate }
|
|
|
- ao_imm32 = $40; { 32 bit immediate }
|
|
|
- ao_imm1 = $80; { 1 bit immediate }
|
|
|
-
|
|
|
- { for unknown expressions }
|
|
|
- ao_immunknown = ao_imm32;
|
|
|
-
|
|
|
- { gen'l immediate }
|
|
|
- ao_imm = (ao_imm8 or ao_imm8S or ao_imm16 or ao_imm32);
|
|
|
- ao_disp8 = $200; { 8 bit displacement (for jumps) }
|
|
|
- ao_disp16 = $400; { 16 bit displacement }
|
|
|
- ao_disp32 = $800; { 32 bit displacement }
|
|
|
-
|
|
|
- { general displacement }
|
|
|
- ao_disp = (ao_disp8 or ao_disp16 or ao_disp32);
|
|
|
-
|
|
|
- { for unknown size displacements }
|
|
|
- ao_dispunknown = ao_disp32;
|
|
|
- ao_mem8 = $1000;
|
|
|
- ao_mem16 = $2000;
|
|
|
- ao_mem32 = $4000;
|
|
|
- ao_baseindex = $8000;
|
|
|
-
|
|
|
- { general mem }
|
|
|
- ao_mem = (ao_disp or ao_mem8 or ao_mem16 or ao_mem32 or ao_baseindex);
|
|
|
- ao_wordmem = (ao_mem16 or ao_mem32 or ao_disp or ao_baseindex);
|
|
|
- ao_bytemem = (ao_mem8 or ao_disp or ao_baseindex);
|
|
|
-
|
|
|
- ao_control = $40000; { Control register }
|
|
|
- ao_debug = $80000; { Debug register }
|
|
|
- ao_test = $100000; { Test register }
|
|
|
- ao_floatreg = $200000; { Float register }
|
|
|
-
|
|
|
-
|
|
|
- ao_jumpabsolute = $4000000;
|
|
|
- ao_abs8 = $08000000;
|
|
|
- ao_abs16 = $10000000;
|
|
|
- ao_abs32 = $20000000;
|
|
|
- ao_abs = (ao_abs8 or ao_abs16 or ao_abs32);
|
|
|
-
|
|
|
- ao_none = $ff;
|
|
|
-
|
|
|
- const
|
|
|
- AB_DN = 1;
|
|
|
- AB_AN = 2;
|
|
|
- AB_INDAN = 3;
|
|
|
- AB_INDPP = 4;
|
|
|
- AB_MMIND = 5;
|
|
|
- AB_OFFAN = 6;
|
|
|
- AB_OFFIDX = 7;
|
|
|
- AB_ABSW = 8;
|
|
|
- AB_ABSL = 9;
|
|
|
- AB_OFFPC = 10;
|
|
|
- AB_OFFIDXPC =11;
|
|
|
- AB_IMM =12;
|
|
|
- AB_REGS =13; {* movem *}
|
|
|
- AB_BBRANCH =14;
|
|
|
- AB_WBRANCH =15;
|
|
|
- AB_CCR =16;
|
|
|
- AB_SR =17;
|
|
|
- AB_USP =18;
|
|
|
- AB_MULDREGS =19;
|
|
|
- AB_MULDREGU =20;
|
|
|
-
|
|
|
- AF_DN =(1 SHL AB_DN);
|
|
|
- AF_AN =(1 SHL AB_AN);
|
|
|
- AF_INDAN = (1 SHL AB_INDAN);
|
|
|
- AF_INDPP = (1 SHL AB_INDPP);
|
|
|
- AF_MMIND = (1 SHL AB_MMIND);
|
|
|
- AF_OFFAN = (1 SHL AB_OFFAN);
|
|
|
- AF_OFFIDX = (1 SHL AB_OFFIDX);
|
|
|
- AF_ABSW = (1 SHL AB_ABSW);
|
|
|
- AF_ABSL = (1 SHL AB_ABSL);
|
|
|
- AF_OFFPC = (1 SHL AB_OFFPC);
|
|
|
- AF_OFFIDXPC= (1 SHL AB_OFFIDXPC);
|
|
|
- AF_IMM =(1 SHL AB_IMM);
|
|
|
- AF_REGS = (1 SHL AB_REGS);
|
|
|
- AF_BBRANCH = (1 SHL AB_BBRANCH);
|
|
|
- AF_WBRANCH = (1 SHL AB_WBRANCH);
|
|
|
- AF_CCR =(1 SHL AB_CCR);
|
|
|
- AF_SR =(1 SHL AB_SR);
|
|
|
- AF_USP =(1 SHL AB_USP);
|
|
|
- AF_MULDREGS= (1 SHL AB_MULDREGS);
|
|
|
- AF_MULDREGU= (1 SHL AB_MULDREGU);
|
|
|
-
|
|
|
- AF_ALL = AF_DN OR AF_AN OR AF_INDAN OR AF_INDPP OR AF_MMIND OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR
|
|
|
- AF_ABSL OR AF_OFFPC OR AF_OFFIDXPC OR AF_IMM;
|
|
|
- AF_ALLNA = AF_DN OR AF_INDAN OR AF_INDPP OR AF_MMIND OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR AF_ABSL
|
|
|
- OR AF_OFFPC OR AF_OFFIDXPC OR AF_IMM;
|
|
|
-
|
|
|
- AF_ALT = AF_DN OR AF_AN OR AF_INDAN OR AF_INDPP OR AF_MMIND OR AF_OFFAN OR
|
|
|
- AF_OFFIDX OR AF_ABSW OR AF_ABSL;
|
|
|
-
|
|
|
- AF_ALTNA = AF_DN OR AF_INDAN OR AF_INDPP OR AF_MMIND OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR AF_ABSL;
|
|
|
- AF_ALTM = AF_INDAN OR AF_INDPP OR AF_MMIND OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR AF_ABSL;
|
|
|
- AF_CTL = AF_INDAN OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR AF_ABSL OR AF_OFFPC OR AF_OFFIDXPC;
|
|
|
- AF_CTLNPC = AF_INDAN OR AF_OFFAN OR AF_OFFIDX OR AF_ABSW OR AF_ABSL OR AF_OFFIDXPC;
|
|
|
-
|
|
|
-
|
|
|
-{ S_WL (S_W|S_L)
|
|
|
- S_BW (S_B|S_W)}
|
|
|
- const
|
|
|
- S_ALL = [S_B] + [S_W] + [S_L];
|
|
|
-{#define S_ALL (S_B|S_W|S_L)}
|
|
|
-
|
|
|
-
|
|
|
- type
|
|
|
- ttemplate = record
|
|
|
- i : tasmop;
|
|
|
- oc : longint;
|
|
|
- ops : byte;
|
|
|
- size: set of topsize;
|
|
|
- o1,o2: longint;
|
|
|
- end;
|
|
|
-
|
|
|
- tins_cache = array[A_ABCD..A_UNLK] of longint;
|
|
|
+ { A type to store register locations for 64 Bit values. }
|
|
|
+ tregister64 = packed record
|
|
|
+ reglo,reghi : tregister;
|
|
|
+ end;
|
|
|
|
|
|
- var
|
|
|
- ins_cache : tins_cache;
|
|
|
+ { alias for compact code }
|
|
|
+ treg64 = tregister64;
|
|
|
|
|
|
- const
|
|
|
- it : array[0..188] of ttemplate = (
|
|
|
-
|
|
|
- ( i:A_ABCD; oc: $C100; ops:2;size: [S_B]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ABCD; oc: $C108; ops:2;size: [S_B]; o1:AF_MMIND; o2:AF_MMIND ),
|
|
|
- ( i:A_ADD; oc: $D000; ops:2;size: S_ALL; o1:AF_ALL; o2:AF_DN ),
|
|
|
- ( i:A_ADD; oc: $D100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_ADD; oc: $D0C0; ops:2;size: [S_W]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_ADD; oc: $D1C0; ops:2;size: [S_L]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_ADD; oc: $0600; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_ADDQ; oc: $5000; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALT ),
|
|
|
- ( i:A_ADDX; oc: $D100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ADDX; oc: $D108; ops:2;size: S_ALL; o1:AF_MMIND; o2:AF_MMIND ),
|
|
|
- ( i:A_AND; oc: $C000; ops:2;size: S_ALL; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_AND; oc: $C100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_AND; oc: $0200; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_AND; oc: $023C; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_CCR ),
|
|
|
- ( i:A_AND; oc: $027C; ops:2;size: [S_W]; o1:AF_IMM; o2:AF_SR ),
|
|
|
- ( i:A_ASL; oc: $E120; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ASL; oc: $E100; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ASL; oc: $E1C0; ops:1;size: [S_W]; o1:0; o2:AF_ALTM ),
|
|
|
- ( i:A_ASR; oc: $E020; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ASR; oc: $E000; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ASR; oc: $E0C0; ops:1;size: [S_W]; o1:0; o2:AF_ALTM ),
|
|
|
-
|
|
|
- ( i:A_BCC; oc: $6400; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BCS; oc: $6500; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BEQ; oc: $6700; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BGE; oc: $6C00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BGT; oc: $6E00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BHI; oc: $6200; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BLE; oc: $6F00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BLS; oc: $6300; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BLT; oc: $6D00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BMI; oc: $6B00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BNE; oc: $6600; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BPL; oc: $6A00; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BVC; oc: $6800; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
- ( i:A_BVS; oc: $6900; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2:0 ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_BCHG; oc: $0140; ops:2;size: [S_B]; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_BCHG; oc: $0140; ops:2;size: [S_L]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_BCHG; oc: $0840; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_ALTM ),
|
|
|
- ( i:A_BCHG; oc: $0840; ops:2;size: [S_L]; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_BCLR; oc: $0180; ops:2;size: [S_B]; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_BCLR; oc: $0180; ops:2;size: [S_L]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_BCLR; oc: $0880; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_ALTM ),
|
|
|
- ( i:A_BCLR; oc: $0880; ops:2;size: [S_L]; o1:AF_IMM; o2:AF_DN ),
|
|
|
-
|
|
|
- ( i:A_BRA; oc: $6000; ops:1;size: [S_NO]; o1:AF_WBRANCH;o2:0 ),
|
|
|
-
|
|
|
- ( i:A_BSET; oc: $01C0; ops:2;size: [S_B]; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_BSET; oc: $01C0; ops:2;size: [S_L]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_BSET; oc: $08C0; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_ALTM ),
|
|
|
- ( i:A_BSET; oc: $08C0; ops:2;size: [S_L]; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_BTST; oc: $0100; ops:2;size: [S_B]; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_BTST; oc: $0100; ops:2;size: [S_L]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_BTST; oc: $0800; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_ALTM ),
|
|
|
- ( i:A_BTST; oc: $0800; ops:2;size: [S_L]; o1:AF_IMM; o2:AF_DN ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_CHK; oc: $4180; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_CLR; oc: $4200; ops:1;size: S_ALL; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_CMP; oc: $B000; ops:2;size: S_ALL; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_CMP; oc: $B000; ops:2;size: [S_WL]; o1:AF_AN; o2:AF_DN ),
|
|
|
- ( i:A_CMP; oc: $B0C0; ops:2;size: [S_W]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_CMP; oc: $B1C0; ops:2;size: [S_L]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_CMP; oc: $0C00; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_CMP; oc: $B108; ops:2;size: S_ALL; o1:AF_INDPP; o2:AF_INDPP ),
|
|
|
-
|
|
|
- ( i:A_DBCC; oc: $54C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBCS; oc: $55C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBEQ; oc: $57C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBF; oc: $51C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBGE; oc: $5CC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBGT; oc: $5EC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBHI; oc: $52C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBLE; oc: $5FC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBLS; oc: $53C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBLT; oc: $5DC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBMI; oc: $5BC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBNE; oc: $56C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBPL; oc: $5AC8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBT; oc: $50C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBVC; oc: $58C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
- ( i:A_DBVS; oc: $59C8; ops:2;size: [S_NO]; o1:AF_DN; o2:AF_WBRANCH ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_DIVS; oc: $81C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_DIVS; oc: $4C40; ops:2;size: [S_L]; o1:AF_ALLNA; o2:AF_DN OR AF_MULDREGS), {* 020 *}
|
|
|
- ( i:A_DIVU; oc: $80C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_DIVU; oc: $4C40; ops:2;size: [S_L]; o1:AF_ALLNA; o2:AF_DN OR AF_MULDREGU), {* 020 *}
|
|
|
-
|
|
|
-
|
|
|
- ( i:A_EOR; oc: $B100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_ALTNA ),
|
|
|
- ( i:A_EOR; oc: $0A00; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_EOR; oc: $0A3C; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_CCR ),
|
|
|
- ( i:A_EOR; oc: $0A7C; ops:2;size: [S_W]; o1:AF_IMM; o2:AF_SR ),
|
|
|
- ( i:A_EXG; oc: $C140; ops:2;size: [S_L]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_EXG; oc: $C148; ops:2;size: [S_L]; o1:AF_AN; o2:AF_AN ),
|
|
|
- ( i:A_EXG; oc: $C188; ops:2;size: [S_L]; o1:AF_DN; o2:AF_AN ),
|
|
|
- ( i:A_EXG; oc: $C188; ops:2;size: [S_L]; o1:AF_AN; o2:AF_DN ),
|
|
|
- ( i:A_EXT; oc: $4880; ops:1;size: [S_W]; o1:AF_DN; o2:0 ),
|
|
|
- ( i:A_EXT; oc: $48C0; ops:1;size: [S_L]; o1:AF_DN; o2:0 ),
|
|
|
- { MC68020 }
|
|
|
- ( i:A_EXTB; oc: $49C0; ops:1;size: [S_L]; o1:AF_DN; o2:0 ),
|
|
|
- ( i:A_ILLEGAL;oc: $4AFC;ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
-
|
|
|
-
|
|
|
- {*
|
|
|
- * note: BSR/BSR/JSR ordering must remain as it is (passc.c optimizations)
|
|
|
- *}
|
|
|
- ( i:A_JMP; oc: $4EC0; ops:1;size: [S_NO]; o1:AF_CTL; o2:0 ),
|
|
|
- ( i:A_BSR; oc: $6100; ops:1;size: [S_NO]; o1:AF_WBRANCH; o2: 0 ),
|
|
|
- ( i:A_JSR; oc: $4E80; ops:1;size: [S_NO]; o1:AF_CTL; o2:0 ),
|
|
|
-
|
|
|
- ( i:A_LEA; oc: $41C0; ops:2;size: [S_L]; o1:AF_CTL; o2:AF_AN ),
|
|
|
- ( i:A_LINK; oc: $4E50; ops:2;size: [S_W]; o1:AF_AN; o2:AF_IMM ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_LSL; oc: $E128; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_LSL; oc: $E108; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_LSL; oc: $E3C0; ops:1;size: [S_W]; o1:0; o2:AF_ALTM ),
|
|
|
- ( i:A_LSR; oc: $E028; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_LSR; oc: $E008; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_LSR; oc: $E2C0; ops:1;size: [S_W]; o1:0; o2:AF_ALTM ),
|
|
|
-
|
|
|
- ( i:A_MOVE; oc: $2000; ops:2;size: [S_L]; o1:AF_ALLNA; o2:AF_ALTNA ),
|
|
|
- ( i:A_MOVE; oc: $3000; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_ALTNA ),
|
|
|
- ( i:A_MOVE; oc: $1000; ops:2;size: [S_B]; o1:AF_ALLNA; o2:AF_ALTNA ),
|
|
|
- ( i:A_MOVE; oc: $2000; ops:2;size: [S_L]; o1:AF_AN; o2:AF_ALTNA ),
|
|
|
- ( i:A_MOVE; oc: $3000; ops:2;size: [S_W]; o1:AF_AN; o2:AF_ALTNA ),
|
|
|
-
|
|
|
- {* 68010
|
|
|
- *( 'MOVE'; i:A_MOVE; oc: $42C0; -1; -1; 0; 3; -1; size: [S_W]; o1:AF_CCR; o1:AF_ALTNA ),
|
|
|
- *}
|
|
|
-
|
|
|
- ( i:A_MOVE; oc: $44C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_CCR ),
|
|
|
- ( i:A_MOVE; oc: $46C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_SR ),
|
|
|
- ( i:A_MOVE; oc: $40C0; ops:2;size: [S_W]; o1:AF_SR; o2:AF_ALTNA ),
|
|
|
- ( i:A_MOVE; oc: $3040; ops:2;size: [S_W]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_MOVE; oc: $2040; ops:2;size: [S_L]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_MOVE; oc: $4E68; ops:2;size: [S_L]; o1:AF_USP; o2:AF_AN ),
|
|
|
- ( i:A_MOVE; oc: $4E60; ops:2;size: [S_L]; o1:AF_AN; o2:AF_USP ),
|
|
|
- {* MOVEC 68010 *}
|
|
|
- ( i:A_MOVEM;oc: $48C0; ops:8;size: [S_L]; o1:AF_REGS; o2:AF_CTL OR AF_MMIND ),
|
|
|
- ( i:A_MOVEM;oc: $4880; ops:8;size: [S_W]; o1:AF_REGS; o2:AF_CTL OR AF_MMIND ),
|
|
|
- ( i:A_MOVEM;oc: $4CC0; ops:8;size: [S_L]; o1:AF_CTL OR AF_INDPP; o2:AF_REGS ),
|
|
|
- ( i:A_MOVEM;oc: $4C80; ops:8;size: [S_W]; o1:AF_CTL OR AF_INDPP; o2:AF_REGS ),
|
|
|
- ( i:A_MOVEP;oc: $0188; ops:2;size: [S_W]; o1:AF_DN; o2:AF_OFFAN ),
|
|
|
- ( i:A_MOVEP;oc: $01C8; ops:2;size: [S_L]; o1:AF_DN; o2:AF_OFFAN ),
|
|
|
- ( i:A_MOVEP;oc: $0108; ops:2;size: [S_W]; o1:AF_OFFAN; o2:AF_DN ),
|
|
|
- ( i:A_MOVEP;oc: $0148; ops:2;size: [S_L]; o1:AF_OFFAN; o2:AF_DN ),
|
|
|
- {* MOVES 68010 *}
|
|
|
- ( i:A_MOVEQ;oc: $7000; ops:2;size: [S_L]; o1:AF_IMM; o2:AF_DN ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_MULS; oc: $C1C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_MULS; oc: $4C00; ops:2;size: [S_L]; o1:AF_ALLNA; o2:AF_DN OR AF_MULDREGS), {* 020 *}
|
|
|
- ( i:A_MULU; oc: $C0C0; ops:2;size: [S_W]; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_MULU; oc: $4C00; ops:2;size: [S_L]; o1:AF_ALLNA; o2:AF_DN OR AF_MULDREGU), {* 020 *}
|
|
|
- ( i:A_NBCD; oc: $4800; ops:1;size: [S_B]; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_NEG; oc: $4400; ops:1;size: S_ALL; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_NEGX; oc: $4000; ops:1;size: S_ALL; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_NOP; oc: $4E71; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
- ( i:A_NOT; oc: $4600; ops:1;size: S_ALL; o1:AF_ALTNA; o2:0 ),
|
|
|
-
|
|
|
- ( i:A_OR; oc: $8000; ops:2;size: S_ALL; o1:AF_ALLNA; o2:AF_DN ),
|
|
|
- ( i:A_OR; oc: $8100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_ALTNA ),
|
|
|
- ( i:A_OR; oc: $0000; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_OR; oc: $003C; ops:2;size: [S_B]; o1:AF_IMM; o2:AF_CCR ),
|
|
|
- ( i:A_OR; oc: $007C; ops:2;size: [S_W]; o1:AF_IMM; o2:AF_SR ),
|
|
|
- ( i:A_PEA; oc: $4840; ops:1;size: [S_L]; o1:AF_CTL; o2:0 ),
|
|
|
- ( i:A_RESET;oc: $4E70; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_ROL; oc: $E138; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ROL; oc: $E118; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ROL; oc: $E7C0; ops:1;size: [S_W]; o1:AF_ALTM; o2:0 ),
|
|
|
- ( i:A_ROR; oc: $E038; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ROR; oc: $E018; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ROR; oc: $E6C0; ops:1;size: [S_W]; o1:AF_ALTM; o2:0 ),
|
|
|
-
|
|
|
- ( i:A_ROXL; oc: $E130; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ROXL; oc: $E110; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ROXL; oc: $E5C0; ops:1;size: [S_W]; o1:AF_ALTM; o2:0 ),
|
|
|
- ( i:A_ROXR; oc: $E030; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_ROXR; oc: $E010; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_DN ),
|
|
|
- ( i:A_ROXR; oc: $E4C0; ops:1;size: [S_W]; o1:AF_ALTM; o2:0 ),
|
|
|
-
|
|
|
- {* RTD 68010 *}
|
|
|
- ( i:A_RTE; oc: $4E73; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
- ( i:A_RTR; oc: $4E77; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
- ( i:A_RTS; oc: $4E75; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
- ( i:A_SBCD; oc: $8100; ops:2;size: [S_B]; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_SBCD; oc: $8108; ops:2;size: [S_B]; o1:AF_MMIND; o2:AF_MMIND ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- {* SCC note; even though they are in the same group since all have the
|
|
|
- * same note if one isn't accepted none of the others will be either
|
|
|
- *}
|
|
|
-
|
|
|
- ( i:A_SCC; oc: $54C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SCS; oc: $55C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SEQ; oc: $57C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SF; oc: $51C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SGE; oc: $5CC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SGT; oc: $5EC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SHI; oc: $52C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SLE; oc: $5FC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SLS; oc: $53C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SLT; oc: $5DC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SMI; oc: $5BC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SNE; oc: $56C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SPL; oc: $5AC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_ST; oc: $50C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SVC; oc: $58C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
- ( i:A_SVS; oc: $59C0; ops:1;size: [S_B]; o1:AF_ALTNA; o2: 0 ),
|
|
|
-
|
|
|
- {* opcode Temp Rs EAs Rd EAd Siz Sizes SModes DModes Spec# *}
|
|
|
-
|
|
|
- ( i:A_STOP; oc: $4E72; ops:0; size: [S_W]; o1:AF_IMM; o2: 0 ),
|
|
|
-
|
|
|
- ( i:A_SUB; oc: $9000; ops:2;size: S_ALL; o1:AF_ALL; o2:AF_DN ),
|
|
|
- ( i:A_SUB; oc: $9100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_ALTM ),
|
|
|
- ( i:A_SUB; oc: $90C0; ops:2;size: [S_W]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_SUB; oc: $91C0; ops:2;size: [S_L]; o1:AF_ALL; o2:AF_AN ),
|
|
|
- ( i:A_SUB; oc: $0400; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALTNA ),
|
|
|
- ( i:A_SUBQ; oc: $5100; ops:2;size: S_ALL; o1:AF_IMM; o2:AF_ALT ),
|
|
|
- ( i:A_SUBX; oc: $9100; ops:2;size: S_ALL; o1:AF_DN; o2:AF_DN ),
|
|
|
- ( i:A_SUBX; oc: $9108; ops:2;size: S_ALL; o1:AF_MMIND; o2:AF_MMIND ),
|
|
|
-
|
|
|
- ( i:A_SWAP; oc: $4840; ops:1;size: [S_W]; o1:AF_DN; o2:0 ),
|
|
|
- ( i:A_TAS; oc: $4AC0; ops:1;size: [S_B]; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_TRAP; oc: $4E40; ops:1;size: [S_NO]; o1:AF_IMM; o2:0 ),
|
|
|
- ( i:A_TRAPV;oc: $4E76; ops:0;size: [S_NO]; o1:0; o2:0 ),
|
|
|
- ( i:A_TST; oc: $4A00; ops:1;size: S_ALL; o1:AF_ALTNA; o2:0 ),
|
|
|
- ( i:A_UNLK; oc: $4E58; ops:1;size: [S_NO]; o1:AF_AN; o2:0 ),
|
|
|
- ( i:A_NONE)
|
|
|
- );
|
|
|
-
|
|
|
-{****************************************************************************
|
|
|
- Assembler Mnemoics
|
|
|
-****************************************************************************}
|
|
|
-
|
|
|
- const
|
|
|
- firstop = A_ABCD;
|
|
|
- lastop = A_LABEL;
|
|
|
-
|
|
|
- mot_op2str : array[firstop..lastop] of string[10] =
|
|
|
- { 68000 only instructions }
|
|
|
- ('abcd','add', 'adda','addi','addq','addx','and','andi',
|
|
|
- 'asl','asr','bcc','bcs','beq','bge','bgt','bhi',
|
|
|
- 'ble','bls','blt','bmi','bne','bpl','bvc','bvs',
|
|
|
- 'bchg','bclr','bra','bset','bsr','btst','chk',
|
|
|
- 'clr','cmp','cmpa','cmpi','cmpm','dbcc','dbcs','dbeq','dbge',
|
|
|
- 'dbgt','dbhi','dble','dbls','dblt','dbmi','dbne','dbra',
|
|
|
- 'dbpl','dbt','dbvc','dbvs','dbf','divs','divu',
|
|
|
- 'eor','eori','exg','illegal','ext','jmp','jsr',
|
|
|
- 'lea','link','lsl','lsr','move','movea','movei','moveq',
|
|
|
- 'movem','movep','muls','mulu','nbcd','neg','negx',
|
|
|
- 'nop','not','or','ori','pea','rol','ror','roxl',
|
|
|
- 'roxr','rtr','rts','sbcd','scc','scs','seq','sge',
|
|
|
- 'sgt','shi','sle','sls','slt','smi','sne',
|
|
|
- 'spl','st','svc','svs','sf','sub','suba','subi','subq',
|
|
|
- 'subx','swap','tas','trap','trapv','tst','unlk',
|
|
|
- 'rte','reset','stop',
|
|
|
- { MC68010 instructions }
|
|
|
- 'bkpt','movec','moves','rtd',
|
|
|
- { MC68020 instructions }
|
|
|
- 'bfchg','bfclr','bfexts','bfextu','bfffo',
|
|
|
- 'bfins','bfset','bftst','callm','cas','cas2',
|
|
|
- 'chk2','cmp2','divsl','divul','extb','pack','rtm',
|
|
|
- 'trapcc','tracs','trapeq','trapf','trapge','trapgt',
|
|
|
- 'traphi','traple','trapls','traplt','trapmi','trapne',
|
|
|
- 'trappl','trapt','trapvc','trapvs','unpk',
|
|
|
- { FPU Processor instructions - directly supported only. }
|
|
|
- { IEEE aware and misc. condition codes not supported }
|
|
|
- 'fabs','fadd',
|
|
|
- 'fbeq','fbne','fbngt','fbgt','fbge','fbnge',
|
|
|
- 'fblt','fbnlt','fble','fbgl','fbngl','fbgle','fbngle',
|
|
|
- 'fdbeq','fdbne','fdbgt','fdbngt','fdbge','fdnbge',
|
|
|
- 'fdblt','fdbnlt','fdble','fdbgl','fdbngl','fdbgle','fbdngle',
|
|
|
- 'fseq','fsne','fsgt','fsngt','fsge','fsnge',
|
|
|
- 'fslt','fsnlt','fsle','fsgl','fsngl','fsgle','fsngle',
|
|
|
- 'fcmp','fdiv','fmove','fmovem',
|
|
|
- 'fmul','fneg','fnop','fsqrt','fsub','fsgldiv',
|
|
|
- 'fsflmul','ftst',
|
|
|
- 'ftrapeq','ftrapne','ftrapgt','ftrapngt','ftrapge','ftrapnge',
|
|
|
- 'ftraplt','ftrapnlt','ftraple','ftrapgl','ftrapngl','ftrapgle',
|
|
|
- 'ftrapngle',
|
|
|
- { Useful for assembly langage output }
|
|
|
- { Protected instructions }
|
|
|
- 'cprestore','cpsave',
|
|
|
- { FPU Unit protected instructions }
|
|
|
- { and 68030/68851 common MMU instructions }
|
|
|
- { (this may include 68040 MMU instructions) }
|
|
|
- 'frestore','fsave','pflush','pflusha','pload','pmove','ptest',
|
|
|
- { Useful for assembly langage output }
|
|
|
- '');
|
|
|
-
|
|
|
- mot_opsize2str : array[topsize] of string[2] =
|
|
|
- ('','.b','.w','.l','.b','.b','.w',
|
|
|
- '.s','.d','.x','.s','.l','.q');
|
|
|
- { I don't know about S_IS, S_IL and S_IQ for m68k
|
|
|
- so I guessed, I am not even sure it can happen !!
|
|
|
- (PM) }
|
|
|
-
|
|
|
- mot_reg2str : array[R_NO..R_FPSR] of string[6] =
|
|
|
- ('', 'd0','d1','d2','d3','d4','d5','d6','d7',
|
|
|
- 'a0','a1','a2','a3','a4','a5','a6','sp',
|
|
|
- '-(sp)','(sp)+',
|
|
|
- 'ccr','fp0','fp1','fp2','fp3','fp4','fp5',
|
|
|
- 'fp6','fp7','fpcr','sr','ssp','dfc',
|
|
|
- 'sfc','vbr','fpsr');
|
|
|
+ {# Type definition for the array of string of register nnames }
|
|
|
+ reg2strtable = array[tregister] of string[5];
|
|
|
|
|
|
- gas_opsize2str : array[topsize] of string[2] =
|
|
|
- ('','.b','.w','.l','.b','.b','.w',
|
|
|
- '.s','.d','.x','.s','.l','.q');
|
|
|
+ Const
|
|
|
+ {# First register in the tregister enumeration }
|
|
|
+ firstreg = low(tregister);
|
|
|
+ {# Last register in the tregister enumeration }
|
|
|
+ lastreg = high(tregister);
|
|
|
|
|
|
- gas_reg2str : array[R_NO..R_FPSR] of string[6] =
|
|
|
+(*
|
|
|
+ gas_reg2str : reg2strtable =
|
|
|
+ ('', '%d0','%d1','%d2','%d3','%d4','%d5','%d6','%d7',
|
|
|
+ '%a0','%a1','%a2','%a3','%a4','%a5','%a6','%sp',
|
|
|
+ '-(%sp)','(%sp)+',
|
|
|
+ '%ccr','%fp0','%fp1','%fp2','%fp3','%fp4','%fp5',
|
|
|
+ '%fp6','%fp7','%fpcr','%sr','%ssp','%dfc',
|
|
|
+ '%sfc','%vbr','%fpsr');
|
|
|
+*)
|
|
|
+ std_reg2str : reg2strtable =
|
|
|
('', 'd0','d1','d2','d3','d4','d5','d6','d7',
|
|
|
'a0','a1','a2','a3','a4','a5','a6','sp',
|
|
|
'-(sp)','(sp)+',
|
|
|
'ccr','fp0','fp1','fp2','fp3','fp4','fp5',
|
|
|
'fp6','fp7','fpcr','sr','ssp','dfc',
|
|
|
'sfc','vbr','fpsr');
|
|
|
-
|
|
|
- mit_opsize2str : array[topsize] of string[2] =
|
|
|
- ('','b','w','l','b','b','w',
|
|
|
- 's','d','x','s','l','q');
|
|
|
-
|
|
|
- mit_reg2str : array[R_NO..R_FPSR] of string[6] =
|
|
|
+
|
|
|
+ mit_reg2str : reg2strtable =
|
|
|
('', 'd0','d1','d2','d3','d4','d5','d6','d7',
|
|
|
'a0','a1','a2','a3','a4','a5','a6','sp',
|
|
|
'sp@-','sp@+',
|
|
|
'ccr','fp0','fp1','fp2','fp3','fp4','fp5',
|
|
|
'fp6','fp7','fpcr','sr','ssp','dfc',
|
|
|
'sfc','vbr','fpsr');
|
|
|
-
|
|
|
- gasPalmOS_reg2str : array[R_NO..R_FPSR] of string[6] =
|
|
|
- ('', '%d0','%d1','%d2','%d3','%d4','%d5','%d6','%d7',
|
|
|
- '%a0','%a1','%a2','%a3','%a4','%a5','%a6','%sp',
|
|
|
- '-(%sp)','(%sp)+',
|
|
|
- '%ccr','%fp0','%fp1','%fp2','%fp3','%fp4','%fp5',
|
|
|
- '%fp6','%fp7','%fpcr','%sr','%ssp','%dfc',
|
|
|
- '%sfc','%vbr','%fpsr');
|
|
|
-
|
|
|
+
|
|
|
|
|
|
{*****************************************************************************
|
|
|
- Init/Done
|
|
|
+ Conditions
|
|
|
*****************************************************************************}
|
|
|
|
|
|
- procedure InitCpu;
|
|
|
- procedure DoneCpu;
|
|
|
-
|
|
|
- implementation
|
|
|
-
|
|
|
- uses
|
|
|
- strings,globals,verbose;
|
|
|
-
|
|
|
-
|
|
|
- procedure disposereference(var r : preference);
|
|
|
+ type
|
|
|
+ TAsmCondFlag = (C_None { unconditional jumps },
|
|
|
+ { conditions when not using ctr decrement etc }
|
|
|
+ C_LT,C_LE,C_EQ,C_GE,C_GT,C_NL,C_NE,C_NG,C_SO,C_NS,C_UN,C_NU,
|
|
|
+ { conditions when using ctr decrement etc }
|
|
|
+ C_T,C_F,C_DNZ,C_DNZT,C_DNZF,C_DZ,C_DZT,C_DZF);
|
|
|
|
|
|
- begin
|
|
|
- if assigned(r^.symbol) then
|
|
|
- stringdispose(r^.symbol);
|
|
|
- dispose(r);
|
|
|
- r:=nil;
|
|
|
- end;
|
|
|
-
|
|
|
- function newreference(const r : treference) : preference;
|
|
|
+ const
|
|
|
+ { these are in the XER, but when moved to CR_x they correspond with the }
|
|
|
+ { bits below (still needs to be verified!!!) }
|
|
|
+ C_OV = C_EQ;
|
|
|
+ C_CA = C_GT;
|
|
|
|
|
|
- var
|
|
|
- p : preference;
|
|
|
+ type
|
|
|
+ TAsmCond = packed record
|
|
|
+ case simple: boolean of
|
|
|
+ false: (BO, BI: byte);
|
|
|
+ true: (
|
|
|
+ cond: TAsmCondFlag;
|
|
|
+ case byte of
|
|
|
+ 0: ();
|
|
|
+ { specifies in which part of the cr the bit has to be }
|
|
|
+ { tested for blt,bgt,beq,..,bnu }
|
|
|
+ 1: (cr: R_CR0..R_CR7);
|
|
|
+ { specifies the bit to test for bt,bf,bdz,..,bdzf }
|
|
|
+ 2: (crbit: byte)
|
|
|
+ );
|
|
|
+ end;
|
|
|
|
|
|
- begin
|
|
|
- new(p);
|
|
|
- p^:=r;
|
|
|
- if assigned(r.symbol) then
|
|
|
- p^.symbol:=stringdup(r.symbol^);
|
|
|
- newreference:=p;
|
|
|
- end;
|
|
|
+ const
|
|
|
+ AsmCondFlag2BO: Array[C_T..C_DZF] of Byte =
|
|
|
+ (12,4,16,8,0,18,10,2);
|
|
|
|
|
|
- procedure reset_reference(var ref : treference);
|
|
|
+ AsmCondFlag2BI: Array[C_LT..C_NU] of Byte =
|
|
|
+ (0,1,2,0,1,0,2,1,3,3,3,3);
|
|
|
|
|
|
- begin
|
|
|
- with ref do
|
|
|
- begin
|
|
|
- index:=R_NO;
|
|
|
- base:=R_NO;
|
|
|
- segment:=R_DEFAULT_SEG;
|
|
|
- offset:=0;
|
|
|
- scalefactor:=1;
|
|
|
- isintvalue:=false;
|
|
|
- symbol:=nil;
|
|
|
- direction := dir_none;
|
|
|
- end;
|
|
|
- end;
|
|
|
+ AsmCondFlagTF: Array[TAsmCondFlag] of Boolean =
|
|
|
+ (false,true,false,true,false,true,false,false,false,true,false,true,false,
|
|
|
+ true,false,false,true,false,false,true,false);
|
|
|
|
|
|
- function new_reference(base : tregister;offset : longint) : preference;
|
|
|
+ AsmCondFlag2Str: Array[TAsmCondFlag] of string[4] = ({cf_none}'',
|
|
|
+ { conditions when not using ctr decrement etc}
|
|
|
+ 'lt','le','eq','ge','gt','nl','ne','ng','so','ns','un','nu',
|
|
|
+ 't','f','dnz','dzt','dnzf','dz','dzt','dzf');
|
|
|
|
|
|
- var
|
|
|
- r : preference;
|
|
|
- begin
|
|
|
- new(r);
|
|
|
- reset_reference(r^);
|
|
|
- r^.base:=base;
|
|
|
- r^.offset:=offset;
|
|
|
- new_reference:=r;
|
|
|
- end;
|
|
|
+ const
|
|
|
+ CondAsmOps=3;
|
|
|
+ CondAsmOp:array[0..CondAsmOps-1] of TasmOp=(
|
|
|
+ A_BC, A_TW, A_TWI
|
|
|
+ );
|
|
|
|
|
|
- procedure clear_reference(var ref : treference);
|
|
|
+{*****************************************************************************
|
|
|
+ Flags
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- stringdispose(ref.symbol);
|
|
|
- reset_reference(ref);
|
|
|
+ type
|
|
|
+ TResFlagsEnum = (F_EQ,F_NE,F_LT,F_LE,F_GT,F_GE,F_SO,F_FX,F_FEX,F_VX,F_OX);
|
|
|
+ TResFlags = record
|
|
|
+ cr: R_CR0..R_CR7;
|
|
|
+ flag: TResFlagsEnum;
|
|
|
end;
|
|
|
|
|
|
- function newcsymbol(const s : string;l : longint) : pcsymbol;
|
|
|
+ (*
|
|
|
+ const
|
|
|
+ { arrays for boolean location conversions }
|
|
|
|
|
|
- var
|
|
|
- p : pcsymbol;
|
|
|
+ flag_2_cond : array[TResFlags] of TAsmCond =
|
|
|
+ (C_E,C_NE,C_LT,C_LE,C_GT,C_GE,???????????????);
|
|
|
+ *)
|
|
|
|
|
|
- begin
|
|
|
- new(p);
|
|
|
- p^.symbol:=strpnew(s);
|
|
|
- p^.offset:=l;
|
|
|
- newcsymbol:=p;
|
|
|
- end;
|
|
|
+{*****************************************************************************
|
|
|
+ Reference
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- procedure disposecsymbol(p : pcsymbol);
|
|
|
+ type
|
|
|
+ trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
|
|
|
+
|
|
|
+ { direction of address register : }
|
|
|
+ { (An) (An)+ -(An) }
|
|
|
+ tdirection = (dir_none,dir_inc,dir_dec);
|
|
|
+
|
|
|
|
|
|
- begin
|
|
|
- strdispose(p^.symbol);
|
|
|
- dispose(p);
|
|
|
+ { reference record }
|
|
|
+ preference = ^treference;
|
|
|
+ treference = packed record
|
|
|
+ segment,
|
|
|
+ base,
|
|
|
+ index : tregister;
|
|
|
+ scalefactor : byte;
|
|
|
+ offset : longint;
|
|
|
+ symbol : tasmsymbol;
|
|
|
+ offsetfixup : longint;
|
|
|
+ options : trefoptions;
|
|
|
+ { indexed increment and decrement mode }
|
|
|
+ { (An)+ and -(An) }
|
|
|
+ direction : tdirection;
|
|
|
+ end;
|
|
|
+
|
|
|
+ { reference record }
|
|
|
+ pparareference = ^tparareference;
|
|
|
+ tparareference = packed record
|
|
|
+ index : tregister;
|
|
|
+ offset : aword;
|
|
|
end;
|
|
|
|
|
|
-{****************************************************************************
|
|
|
- Taicpu
|
|
|
- ****************************************************************************}
|
|
|
+{*****************************************************************************
|
|
|
+ Operands
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- constructor taicpu.op_none(op : tasmop;_size : topsize);
|
|
|
+ { Types of operand }
|
|
|
+ toptype=(top_none,top_reg,top_ref,top_const,top_symbol);
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_none;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
-
|
|
|
- { the following isn't required ! }
|
|
|
- op1:=nil;
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
+ toper=record
|
|
|
+ ot : longint;
|
|
|
+ case typ : toptype of
|
|
|
+ top_none : ();
|
|
|
+ top_reg : (reg:tregister);
|
|
|
+ top_ref : (ref:preference);
|
|
|
+ top_const : (val:aword);
|
|
|
+ top_symbol : (sym:tasmsymbol;symofs:longint);
|
|
|
end;
|
|
|
|
|
|
- constructor taicpu.op_reg(op : tasmop;_size : topsize;_op1 : tregister);
|
|
|
+{*****************************************************************************
|
|
|
+ Generic Location
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_reg;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
+ type
|
|
|
+ TLoc=(
|
|
|
+ LOC_INVALID, { added for tracking problems}
|
|
|
+ LOC_CONSTANT, { constant value }
|
|
|
+ LOC_JUMP, { boolean results only, jump to false or true label }
|
|
|
+ LOC_FLAGS, { boolean results only, flags are set }
|
|
|
+ LOC_CREFERENCE, { in memory constant value reference (cannot change) }
|
|
|
+ LOC_REFERENCE, { in memory value }
|
|
|
+ LOC_REGISTER, { in a processor register }
|
|
|
+ LOC_CREGISTER, { Constant register which shouldn't be modified }
|
|
|
+ LOC_FPUREGISTER, { FPU stack }
|
|
|
+ LOC_CFPUREGISTER, { if it is a FPU register variable on the fpu stack }
|
|
|
+ LOC_MMXREGISTER, { MMX register }
|
|
|
+ LOC_CMMXREGISTER, { MMX register variable }
|
|
|
+ );
|
|
|
+
|
|
|
+ { tparamlocation describes where a parameter for a procedure is stored.
|
|
|
+ References are given from the caller's point of view. The usual
|
|
|
+ TLocation isn't used, because contains a lot of unnessary fields.
|
|
|
+ }
|
|
|
+ tparalocation = packed record
|
|
|
+ loc : TLoc;
|
|
|
+ sp_fixup : longint;
|
|
|
+ case TLoc of
|
|
|
+ LOC_REFERENCE : (reference : tparareference);
|
|
|
+ { segment in reference at the same place as in loc_register }
|
|
|
+ LOC_REGISTER,LOC_CREGISTER : (
|
|
|
+ case longint of
|
|
|
+ 1 : (register,registerhigh : tregister);
|
|
|
+ { overlay a registerlow }
|
|
|
+ 2 : (registerlow : tregister);
|
|
|
+ { overlay a 64 Bit register type }
|
|
|
+ 3 : (reg64 : tregister64);
|
|
|
+ 4 : (register64 : tregister64);
|
|
|
+ );
|
|
|
+ { it's only for better handling }
|
|
|
+ LOC_MMXREGISTER,LOC_CMMXREGISTER : (mmxreg : tregister);
|
|
|
+ end;
|
|
|
+
|
|
|
+ tlocation = packed record
|
|
|
+ loc : TLoc;
|
|
|
+ size : TCGSize;
|
|
|
+ case TLoc of
|
|
|
+ LOC_FLAGS : (resflags : tresflags);
|
|
|
+ LOC_CONSTANT : (
|
|
|
+ case longint of
|
|
|
+ 1 : (value : AWord);
|
|
|
+ 2 : (valuelow, valuehigh:AWord);
|
|
|
+ { overlay a complete 64 Bit value }
|
|
|
+ 3 : (valueqword : qword);
|
|
|
+ );
|
|
|
+ LOC_CREFERENCE,
|
|
|
+ LOC_REFERENCE : (reference : treference);
|
|
|
+ { segment in reference at the same place as in loc_register }
|
|
|
+ LOC_REGISTER,LOC_CREGISTER : (
|
|
|
+ case longint of
|
|
|
+ 1 : (register,registerhigh,segment : tregister);
|
|
|
+ { overlay a registerlow }
|
|
|
+ 2 : (registerlow : tregister);
|
|
|
+ { overlay a 64 Bit register type }
|
|
|
+ 3 : (reg64 : tregister64);
|
|
|
+ 4 : (register64 : tregister64);
|
|
|
+ );
|
|
|
+ { it's only for better handling }
|
|
|
+ LOC_MMXREGISTER,LOC_CMMXREGISTER : (mmxreg : tregister);
|
|
|
end;
|
|
|
|
|
|
- constructor taicpu.op_const(op : tasmop;_size : topsize;_op1 : longint);
|
|
|
-
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
- constructor taicpu.op_ref(op : tasmop;_size : topsize;_op1 : preference);
|
|
|
-
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- if _op1^.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1^.offset);
|
|
|
- disposereference(_op1);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(_op1);
|
|
|
- end;
|
|
|
-
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+{*****************************************************************************
|
|
|
+ Operand
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- constructor taicpu.op_loc(op : tasmop;_size : topsize;_op1 : tlocation);
|
|
|
+ type
|
|
|
+ toptype=(top_none,top_reg,top_ref,top_const,top_symbol,top_bool);
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- if (_op1.loc=loc_register) or (_op1.loc=loc_cregister) then
|
|
|
- begin
|
|
|
- op1t:=top_reg;
|
|
|
- op1:=pointer(_op1.register);
|
|
|
- end
|
|
|
- else
|
|
|
- if _op1.reference.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1.reference.offset);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(newreference(_op1.reference));
|
|
|
- end;
|
|
|
-
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
+ toper=record
|
|
|
+ ot : longint;
|
|
|
+ case typ : toptype of
|
|
|
+ top_none : ();
|
|
|
+ top_reg : (reg:tregister);
|
|
|
+ top_ref : (ref:^treference);
|
|
|
+ top_const : (val:aword);
|
|
|
+ top_symbol : (sym:tasmsymbol;symofs:longint);
|
|
|
+ top_bool : (b: boolean);
|
|
|
end;
|
|
|
|
|
|
- constructor taicpu.op_reg_reg(op : tasmop;_size : topsize;_op1,_op2 : tregister);
|
|
|
-
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_reg;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+{*****************************************************************************
|
|
|
+ Operand Sizes
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- constructor taicpu.op_reg_ref(op : tasmop;_size : topsize;_op1 : tregister;_op2 : preference);
|
|
|
+ { S_NO = No Size of operand }
|
|
|
+ { S_B = 8-bit size operand }
|
|
|
+ { S_W = 16-bit size operand }
|
|
|
+ { S_L = 32-bit size operand }
|
|
|
+ { Floating point types }
|
|
|
+ { S_FS = single type (32 bit) }
|
|
|
+ { S_FD = double/64bit integer }
|
|
|
+ { S_FX = Extended type }
|
|
|
+ topsize = (S_NO,S_B,S_W,S_L,S_FS,S_FD,S_FX);
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if _op2^.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2^.offset);
|
|
|
- disposereference(_op2);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(_op2);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+{*****************************************************************************
|
|
|
+ Constants
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- constructor taicpu.op_reg_loc(op : tasmop;_size : topsize;_op1 : tregister;_op2 : tlocation);
|
|
|
+ const
|
|
|
+ max_operands = 5;
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if (_op2.loc=loc_register) or (_op2.loc=loc_cregister) then
|
|
|
- begin
|
|
|
- op2t:=top_reg;
|
|
|
- op2:=pointer(_op2.register);
|
|
|
- end
|
|
|
- else
|
|
|
- if _op2.reference.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2.reference.offset);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(newreference(_op2.reference));
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ lvaluelocations = [LOC_REFERENCE, LOC_CREGISTER, LOC_CFPUREGISTER,
|
|
|
+ LOC_CMMREGISTER];
|
|
|
|
|
|
- constructor taicpu.op_loc_reg(op : tasmop;_size : topsize;_op1 : tlocation;_op2 : tregister);
|
|
|
+ {# Constant defining possibly all registers which might require saving }
|
|
|
+ ALL_REGISTERS = [R_D1..R_FPCR];
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- if (_op1.loc=loc_register) or (_op1.loc=loc_cregister) then
|
|
|
- begin
|
|
|
- op1t:=top_reg;
|
|
|
- op1:=pointer(_op1.register);
|
|
|
- end
|
|
|
- else
|
|
|
- if _op1.reference.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1.reference.offset);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(newreference(_op1.reference));
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ general_registers = [R_D0..R_D7];
|
|
|
|
|
|
- constructor taicpu.op_const_reg_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister;_op3 : tregister);
|
|
|
+ {# low and high of the available maximum width integer general purpose }
|
|
|
+ { registers }
|
|
|
+ LoGPReg = R_D0;
|
|
|
+ HiGPReg = R_D7;
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_reg;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
- op3:=pointer(_op3);
|
|
|
- end;
|
|
|
+ {# low and high of every possible width general purpose register (same as }
|
|
|
+ { above on most architctures apart from the 80x86) }
|
|
|
+ LoReg = LoGPReg;
|
|
|
+ HiReg = HighGPReg;
|
|
|
|
|
|
- constructor taicpu.op_reg_const(op: tasmop; _size: topsize; _op1: tregister; _op2: longint);
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ := ait_instruction;
|
|
|
- _operator := op;
|
|
|
- op1t := top_reg;
|
|
|
- op2t := top_const;
|
|
|
- op3t := top_none;
|
|
|
- op1 := pointer(_op1);
|
|
|
- op2 := pointer(_op2);
|
|
|
- size := _size;
|
|
|
- end;
|
|
|
+ { Table of registers which can be allocated by the code generator
|
|
|
+ internally, when generating the code.
|
|
|
+
|
|
|
+ legend:
|
|
|
+ xxxregs = set of all possibly used registers of that type in the code
|
|
|
+ generator
|
|
|
+ usableregsxxx = set of all 32bit components of registers that can be
|
|
|
+ possible allocated to a regvar or using getregisterxxx (this
|
|
|
+ excludes registers which can be only used for parameter
|
|
|
+ passing on ABI's that define this)
|
|
|
+ c_countusableregsxxx = amount of registers in the usableregsxxx set }
|
|
|
+
|
|
|
+ maxintregs = 8;
|
|
|
+ intregs = [R_D0..R_D7];
|
|
|
+ usableregsint = [R_D2..R_D7];
|
|
|
+ c_countusableregsint = 6;
|
|
|
+
|
|
|
+ maxfpuregs = 8;
|
|
|
+ fpuregs = [R_FP0..R_FP7];
|
|
|
+ usableregsfpu = [R_FP2..R_FP7];
|
|
|
+ c_countusableregsfpu = 6;
|
|
|
+
|
|
|
+ mmregs = [];
|
|
|
+ usableregsmm = [];
|
|
|
+ c_countusableregsmm = 0;
|
|
|
+
|
|
|
+ maxaddrregs = 8;
|
|
|
+ addrregs = [R_A0..R_SP];
|
|
|
+ usableregsaddr = [R_A2..R_A4];
|
|
|
+ c_countusableregsaddr = 3;
|
|
|
+
|
|
|
|
|
|
+ { The first register in the usableregsint array }
|
|
|
+ firstsaveintreg = R_D2;
|
|
|
+ { The last register in the usableregsint array }
|
|
|
+ lastsaveintreg = R_D7;
|
|
|
+ { The first register in the usableregsfpu array }
|
|
|
+ firstsavefpureg = R_FP2;
|
|
|
+ { The last register in the usableregsfpu array }
|
|
|
+ lastsavefpureg = R_FP7;
|
|
|
+
|
|
|
+ { these constants are m68k specific }
|
|
|
+ { The first register in the usableregsaddr array }
|
|
|
+ firstsaveaddrreg = R_A2;
|
|
|
+ { The last register in the usableregsaddr array }
|
|
|
+ lastsaveaddrreg = R_A4;
|
|
|
+
|
|
|
+ firstsavemmreg = R_NO;
|
|
|
+ lastsavemmreg = R_NO;
|
|
|
+
|
|
|
+ {
|
|
|
+ Defines the maxinum number of integer registers which can be used as variable registers
|
|
|
+ }
|
|
|
+ maxvarregs = 6;
|
|
|
+ { Array of integer registers which can be used as variable registers }
|
|
|
+ varregs : Array [1..maxvarregs] of Tregister =
|
|
|
+ (R_D2,R_D3,R_D4,R_D5,R_D6,R_D7);
|
|
|
+
|
|
|
+ {
|
|
|
+ Defines the maxinum number of float registers which can be used as variable registers
|
|
|
+ }
|
|
|
+ maxfpuvarregs = 6;
|
|
|
+ { Array of float registers which can be used as variable registers }
|
|
|
+ fpuvarregs : Array [1..maxfpuvarregs] of Tregister =
|
|
|
+ (R_FP2,R_FP3,R_FP4,R_FP5,R_FP6,R_FP7);
|
|
|
+
|
|
|
+ {
|
|
|
+ Defines the number of integer registers which are used in the ABI to pass parameters
|
|
|
+ (might be empty on systems which use the stack to pass parameters)
|
|
|
+ }
|
|
|
+ max_param_regs_int = 0;
|
|
|
+ {param_regs_int: Array[1..max_param_regs_int] of tregister =
|
|
|
+ (R_3,R_4,R_5,R_6,R_7,R_8,R_9,R_10);}
|
|
|
+
|
|
|
+ {
|
|
|
+ Defines the number of float registers which are used in the ABI to pass parameters
|
|
|
+ (might be empty on systems which use the stack to pass parameters)
|
|
|
+ }
|
|
|
+ max_param_regs_fpu = 0;
|
|
|
+ {param_regs_fpu: Array[1..max_param_regs_fpu] of tregister =
|
|
|
+ (R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13);}
|
|
|
+
|
|
|
+ {
|
|
|
+ Defines the number of mmx registers which are used in the ABI to pass parameters
|
|
|
+ (might be empty on systems which use the stack to pass parameters)
|
|
|
+ }
|
|
|
+ max_param_regs_mm = 0;
|
|
|
+ {param_regs_mm: Array[1..max_param_regs_mm] of tregister =
|
|
|
+ (R_M1,R_M2,R_M3,R_M4,R_M5,R_M6,R_M7,R_M8,R_M9,R_M10,R_M11,R_M12,R_M13);}
|
|
|
+
|
|
|
+ {# Registers which are defined as scratch integer and no need to save across
|
|
|
+ routine calls or in assembler blocks.
|
|
|
+ }
|
|
|
+ max_scratch_regs = 2;
|
|
|
+ scratch_regs: Array[1..max_scratch_regs] of TRegister = (R_D0,R_D1);
|
|
|
|
|
|
- constructor taicpu.op_reg_reg_reg(op : tasmop;_size : topsize;_op1 : tregister;_op2 : tregister;_op3 : tregister);
|
|
|
+{*****************************************************************************
|
|
|
+ Default generic sizes
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_reg;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_reg;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
- op3:=pointer(_op3);
|
|
|
- end;
|
|
|
+ {# Defines the default address size for a processor, }
|
|
|
+ OS_ADDR = OS_32;
|
|
|
+ {# the natural int size for a processor, }
|
|
|
+ OS_INT = OS_32;
|
|
|
+ {# the maximum float size for a processor, }
|
|
|
+ OS_FLOAT = OS_F64;
|
|
|
+ {# the size of a vector register for a processor }
|
|
|
+ OS_VECTOR = OS_M128;
|
|
|
|
|
|
- constructor taicpu.op_const_reg(op : tasmop;_size : topsize;_op1 : longint;_op2 : tregister);
|
|
|
+{*****************************************************************************
|
|
|
+ Generic Register names
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ {# Stack pointer register }
|
|
|
+ stack_pointer_reg = R_SP;
|
|
|
+ {# Frame pointer register }
|
|
|
+ frame_pointer_reg = R_A6;
|
|
|
+ {# Self pointer register : contains the instance address of an
|
|
|
+ object or class. }
|
|
|
+ self_pointer_reg = R_A5;
|
|
|
+ {# Register for addressing absolute data in a position independant way,
|
|
|
+ such as in PIC code. The exact meaning is ABI specific }
|
|
|
+ pic_offset_reg = R_A5;
|
|
|
+ {# Results are returned in this register (32-bit values) }
|
|
|
+ accumulator = R_D0;
|
|
|
+ {# Hi-Results are returned in this register (64-bit value high register) }
|
|
|
+ accumulatorhigh = R_D1;
|
|
|
+ { Floating point results will be placed into this register }
|
|
|
+ FPU_RESULT_REG = R_FP0;
|
|
|
+ mmresultreg = R_N0;
|
|
|
|
|
|
- constructor taicpu.op_const_const(op : tasmop;_size : topsize;_op1,_op2 : longint);
|
|
|
+{*****************************************************************************
|
|
|
+ GCC /ABI linking information
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op2t:=top_const;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ {# Registers which must be saved when calling a routine declared as
|
|
|
+ cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
|
|
|
+ saved should be the ones as defined in the target ABI and / or GCC.
|
|
|
|
|
|
- constructor taicpu.op_const_ref(op : tasmop;_size : topsize;_op1 : longint;_op2 : preference);
|
|
|
+ This value can be deduced from CALLED_USED_REGISTERS array in the
|
|
|
+ GCC source.
|
|
|
+ }
|
|
|
+ std_saved_registers = [R_D2..R_D7,R_A2..R_A5];
|
|
|
+ {# Required parameter alignment when calling a routine declared as
|
|
|
+ stdcall and cdecl. The alignment value should be the one defined
|
|
|
+ by GCC or the target ABI.
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if _op2^.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2^.offset);
|
|
|
- disposereference(_op2);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(_op2);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ The value of this constant is equal to the constant
|
|
|
+ PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
|
|
|
+ }
|
|
|
+ std_param_align = 4; { for 32-bit version only }
|
|
|
|
|
|
- constructor taicpu.op_const_loc(op : tasmop;_size : topsize;_op1 : longint;_op2 : tlocation);
|
|
|
+{*****************************************************************************
|
|
|
+ CPU Dependent Constants
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_const;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if (_op2.loc=loc_register) or (_op2.loc=loc_cregister) then
|
|
|
- begin
|
|
|
- op2t:=top_reg;
|
|
|
- op2:=pointer(_op2.register);
|
|
|
- end
|
|
|
- else
|
|
|
- if _op2.reference.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2.reference.offset);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(newreference(_op2.reference));
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
|
|
|
- constructor taicpu.op_ref_reg(op : tasmop;_size : topsize;_op1 : preference;_op2 : tregister);
|
|
|
+{*****************************************************************************
|
|
|
+ Helpers
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- if _op1^.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1^.offset);
|
|
|
- disposereference(_op1);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(_op1);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ function is_calljmp(o:tasmop):boolean;
|
|
|
|
|
|
- constructor taicpu.op_ref_ref(op : tasmop;_size : topsize;_op1,_op2 : preference);
|
|
|
+ procedure inverse_flags(var r : TResFlags);
|
|
|
+ procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
|
|
|
+ function flags_to_cond(const f: TResFlags) : TAsmCond;
|
|
|
+ procedure create_cond_imm(BO,BI:byte;var r : TAsmCond);
|
|
|
+ procedure create_cond_norm(cond: TAsmCondFlag; cr: byte;var r : TasmCond);
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
-
|
|
|
- if _op1^.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1^.offset);
|
|
|
- disposereference(_op1);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(_op1);
|
|
|
- end;
|
|
|
-
|
|
|
- if _op2^.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2^.offset);
|
|
|
- disposereference(_op2);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(_op2);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
|
|
|
- constructor taicpu.op_csymbol(op : tasmop;_size : topsize;_op1 : pcsymbol);
|
|
|
+implementation
|
|
|
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- if (op=A_JSR) and
|
|
|
- (use_esp_stackframe) then
|
|
|
- Message(cg_e_stackframe_with_esp);
|
|
|
- op1t:=top_symbol;
|
|
|
- op2t:=top_none;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- op2:=nil;
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
+ uses
|
|
|
+ verbose;
|
|
|
|
|
|
- constructor taicpu.op_csymbol_reg(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : tregister);
|
|
|
+{*****************************************************************************
|
|
|
+ Helpers
|
|
|
+*****************************************************************************}
|
|
|
|
|
|
+ function is_calljmp(o:tasmop):boolean;
|
|
|
begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_symbol;
|
|
|
- op2t:=top_reg;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
- op2:=pointer(_op2);
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
end;
|
|
|
|
|
|
- constructor taicpu.op_csymbol_ref(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : preference);
|
|
|
|
|
|
+ procedure inverse_flags(var r: TResFlags);
|
|
|
begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_symbol;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if _op2^.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2^.offset);
|
|
|
- disposereference(_op2);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(_op2);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
end;
|
|
|
|
|
|
- constructor taicpu.op_csymbol_loc(op : tasmop;_size : topsize;_op1 : pcsymbol;_op2 : tlocation);
|
|
|
|
|
|
+ procedure inverse_cond(const c: TAsmCond;var r : TAsmCond);
|
|
|
begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op1t:=top_symbol;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- op1:=pointer(_op1);
|
|
|
-
|
|
|
- if (_op2.loc=loc_register) or (_op2.loc=loc_cregister) then
|
|
|
- begin
|
|
|
- op2t:=top_reg;
|
|
|
- op2:=pointer(_op2.register);
|
|
|
- end
|
|
|
- else
|
|
|
- if _op2.reference.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2.reference.offset);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(newreference(_op2.reference));
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
end;
|
|
|
|
|
|
- destructor taicpu.done;
|
|
|
|
|
|
- begin
|
|
|
- if op1t=top_symbol then
|
|
|
- disposecsymbol(pcsymbol(op1))
|
|
|
- else if op1t=top_ref then
|
|
|
+ function flags_to_cond(const f: TResFlags) : TAsmCond;
|
|
|
begin
|
|
|
- clear_reference(preference(op1)^);
|
|
|
- dispose(preference(op1));
|
|
|
- end;
|
|
|
- if op2t=top_symbol then
|
|
|
- disposecsymbol(pcsymbol(op2))
|
|
|
- else if op2t=top_ref then
|
|
|
- begin
|
|
|
- clear_reference(preference(op2)^);
|
|
|
- dispose(preference(op2));
|
|
|
- end;
|
|
|
- if op3t=top_symbol then
|
|
|
- disposecsymbol(pcsymbol(op3))
|
|
|
- else if op3t = top_ref then
|
|
|
- begin
|
|
|
- clear_reference(preference(op3)^);
|
|
|
- dispose(preference(op3));
|
|
|
- end;
|
|
|
- inherited done;
|
|
|
- end;
|
|
|
-
|
|
|
-
|
|
|
- constructor taicpu.op_ref_reglist(op: tasmop; _size : topsize; _op1: preference;_op2: tregisterlist);
|
|
|
- Begin
|
|
|
- Inherited Init;
|
|
|
- typ:=ait_instruction;
|
|
|
- _operator:=op;
|
|
|
- op2t:=top_reglist;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
- reglist := _op2;
|
|
|
-
|
|
|
- if _op1^.isintvalue then
|
|
|
- begin
|
|
|
- op1t:=top_const;
|
|
|
- op1:=pointer(_op1^.offset);
|
|
|
- disposereference(_op1);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op1t:=top_ref;
|
|
|
- op1:=pointer(_op1);
|
|
|
- end;
|
|
|
-
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
-
|
|
|
-
|
|
|
- constructor taicpu.op_reglist_ref(op: tasmop; _size : topsize; _op1: tregisterlist; _op2: preference);
|
|
|
- Begin
|
|
|
- Inherited Init;
|
|
|
- typ:=ait_instruction;
|
|
|
-
|
|
|
- _operator:=op;
|
|
|
- reglist:=_op1;
|
|
|
-
|
|
|
- op1t:=top_reglist;
|
|
|
- op3t:=top_none;
|
|
|
- size:=_size;
|
|
|
-
|
|
|
- if _op2^.isintvalue then
|
|
|
- begin
|
|
|
- op2t:=top_const;
|
|
|
- op2:=pointer(_op2^.offset);
|
|
|
- disposereference(_op2);
|
|
|
- end
|
|
|
- else
|
|
|
- begin
|
|
|
- op2t:=top_ref;
|
|
|
- op2:=pointer(_op2);
|
|
|
- end;
|
|
|
- op3:=nil;
|
|
|
- end;
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
-{****************************************************************************
|
|
|
- TAI_LABELED
|
|
|
- ****************************************************************************}
|
|
|
-
|
|
|
- constructor tai_labeled.init(op : tasmop; l : pasmlabel);
|
|
|
-
|
|
|
- begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_labeled_instruction;
|
|
|
- _operator:=op;
|
|
|
- _op1:=R_NO;
|
|
|
- lab:=l;
|
|
|
- inc(lab^.refs);
|
|
|
end;
|
|
|
|
|
|
- constructor tai_labeled.init_reg(op : tasmop; l : pasmlabel; reg: tregister);
|
|
|
|
|
|
+ procedure create_cond_imm(BO,BI:byte;var r : TAsmCond);
|
|
|
begin
|
|
|
- inherited init;
|
|
|
- typ:=ait_labeled_instruction;
|
|
|
- _op1:=reg;
|
|
|
- _operator:=op;
|
|
|
- lab:=l;
|
|
|
- inc(lab^.refs);
|
|
|
end;
|
|
|
|
|
|
- destructor tai_labeled.done;
|
|
|
|
|
|
+ procedure create_cond_norm(cond: TAsmCondFlag; cr: byte;var r : TasmCond);
|
|
|
begin
|
|
|
- dec(lab^.refs);
|
|
|
- inherited done;
|
|
|
end;
|
|
|
-{*****************************************************************************
|
|
|
- Init/Done
|
|
|
-*****************************************************************************}
|
|
|
|
|
|
- procedure InitCpu;
|
|
|
- begin
|
|
|
- end;
|
|
|
-
|
|
|
- procedure DoneCpu;
|
|
|
- begin
|
|
|
- end;
|
|
|
-
|
|
|
end.
|
|
|
{
|
|
|
$Log$
|
|
|
- Revision 1.2 2002-04-20 21:40:48 carl
|
|
|
- * renamed some constants
|
|
|
-
|
|
|
- Revision 1.1 2000/07/13 06:30:05 michael
|
|
|
- + Initial import
|
|
|
-
|
|
|
- Revision 1.2 2000/01/07 01:14:50 peter
|
|
|
- * updated copyright to 2000
|
|
|
-
|
|
|
- Revision 1.1 1999/09/16 23:05:57 florian
|
|
|
- * m68k compiler is again compilable (only gas writer, no assembler reader)
|
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-
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- Revision 1.12 1999/08/19 13:02:08 pierre
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- + label faillabel added for _FAIL support
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-
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- Revision 1.11 1999/06/22 16:24:42 pierre
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- * local browser stuff corrected
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-
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- Revision 1.10 1998/10/29 11:35:45 florian
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- * some dll support for win32
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- * fixed assembler writing for PalmOS
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-
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- Revision 1.9 1998/10/14 08:47:18 pierre
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- * bugs in secondfuncret for result in subprocedures removed
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-
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- Revision 1.8 1998/10/13 16:50:15 pierre
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- * undid some changes of Peter that made the compiler wrong
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- for m68k (I had to reinsert some ifdefs)
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- * removed several memory leaks under m68k
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- * removed the meory leaks for assembler readers
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- * cross compiling shoud work again better
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- ( crosscompiling sysamiga works
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- but as68k still complain about some code !)
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-
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- Revision 1.7 1998/08/31 12:26:27 peter
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- * m68k and palmos updates from surebugfixes
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-
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- Revision 1.6 1998/08/21 14:08:44 pierre
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- + TEST_FUNCRET now default (old code removed)
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- works also for m68k (at least compiles)
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-
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- Revision 1.5 1998/06/04 23:51:45 peter
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- * m68k compiles
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- + .def file creation moved to gendef.pas so it could also be used
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- for win32
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-
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- Revision 1.4 1998/05/23 01:21:10 peter
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- + aktasmmode, aktoptprocessor, aktoutputformat
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- + smartlink per module $SMARTLINK-/+ (like MMX) and moved to aktswitches
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- + $LIBNAME to set the library name where the unit will be put in
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- * splitted cgi386 a bit (codeseg to large for bp7)
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- * nasm, tasm works again. nasm moved to ag386nsm.pas
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-
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- Revision 1.3 1998/05/11 13:07:54 peter
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- + $ifdef NEWPPU for the new ppuformat
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- + $define GDB not longer required
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- * removed all warnings and stripped some log comments
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- * no findfirst/findnext anymore to remove smartlink *.o files
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-
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- Revision 1.2 1998/04/29 10:33:54 pierre
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- + added some code for ansistring (not complete nor working yet)
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- * corrected operator overloading
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- * corrected nasm output
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- + started inline procedures
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- + added starstarn : use ** for exponentiation (^ gave problems)
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- + started UseTokenInfo cond to get accurate positions
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+ Revision 1.3 2002-07-29 17:51:32 carl
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+ + restart m68k support
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+
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+
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}
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