* fixed LsrAnd2Lsr test by replacing the existing buggy check with comparing

    the outcome of the original and the optimised sequence and seeing whether
    it's same + test

git-svn-id: trunk@25776 -

.gitattributes

@@ -10754,6 +10754,7 @@ tests/test/library/ttdlltest.pp svneol=native#text/plain
 tests/test/library/ulib2a.pp svneol=native#text/plain
 tests/test/library/ulib2b.pp svneol=native#text/plain
 tests/test/opt/README.txt svneol=native#text/plain
+tests/test/opt/tarmsa1.pp svneol=native#text/plain
 tests/test/opt/tarmshift.pp svneol=native#text/plain
 tests/test/opt/tcaseopt1.pp svneol=native#text/plain
 tests/test/opt/tcmov.pp svneol=native#text/plain

compiler/arm/aoptcpu.pas

@@ -947,15 +947,10 @@ Implementation
                            (taicpu(hp1).ops=3) and
                            MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[1]^) and
                            (taicpu(hp1).oper[2]^.typ = top_const) and
-                           { Check if the AND actually would only mask out bits beeing already zero because of the shift
-                             For LSR #25 and an AndConst of 255 that whould go like this:
-                             255 and ((2 shl (32-25))-1)
-                             which results in 127, which is one less a power-of-2, meaning all lower bits are set.
-
-                             LSR #25 and AndConst of 254:
-                             254 and ((2 shl (32-25))-1) = 126 -> lowest bit is clear, so we can't remove it.
+                           { Check if the AND actually would only mask out bits being already zero because of the shift
                            }
-                           ispowerof2((taicpu(hp1).oper[2]^.val and ((2 shl (32-taicpu(p).oper[2]^.shifterop^.shiftimm))-1))+1) then
+                           ((($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm) and taicpu(hp1).oper[2]^.val) =
+                             ($ffffffff shr taicpu(p).oper[2]^.shifterop^.shiftimm)) then
                            begin
                              DebugMsg('Peephole LsrAnd2Lsr done', hp1);
                              taicpu(p).oper[0]^.reg:=taicpu(hp1).oper[0]^.reg;

tests/test/opt/tarmsa1.pp

@@ -0,0 +1,15 @@
+{ %opt=-O2 }
+procedure test;
+var
+  a, b: cardinal;
+begin
+  a:=$ffffffff;
+  b:=(a shr 24) and $3f;
+  if b<>$3f then
+    halt(1);
+end;
+
+begin
+  test;
+end.
+