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@@ -829,15 +829,17 @@ const
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testbit := ((ord(f.cr)-ord(R_CR0)) * 4);
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case f.flag of
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F_EQ,F_NE:
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- bitvalue := f.flag = F_EQ;
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+ begin
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+ inc(testbit,2);
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+ bitvalue := f.flag = F_EQ;
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+ end;
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F_LT,F_GE:
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begin
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- inc(testbit);
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bitvalue := f.flag = F_LT;
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end;
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F_GT,F_LE:
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begin
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- inc(testbit,2);
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+ inc(testbit);
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bitvalue := f.flag = F_GT;
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end;
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else
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@@ -847,7 +849,7 @@ const
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list.concat(taicpu.op_reg(A_MFCR,reg));
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{ we will move the bit that has to be tested to bit 0 by rotating }
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{ left }
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- testbit := (32 - testbit) and 31;
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+ testbit := (testbit + 1) and 31;
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{ extract bit }
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list.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWINM,reg,reg,testbit,31,31));
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@@ -2353,7 +2355,10 @@ begin
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end.
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{
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$Log$
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- Revision 1.83 2003-04-26 15:25:29 florian
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+ Revision 1.84 2003-04-26 16:08:41 jonas
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+ * fixed g_flags2reg
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+
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+ Revision 1.83 2003/04/26 15:25:29 florian
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* fixed cmp_reg_reg_reg, cmp operands were emitted in the wrong order
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Revision 1.82 2003/04/25 20:55:34 florian
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