* enabled internal sar support for sparc and mips as well

git-svn-id: trunk@14867 -

compiler/options.pas

@@ -2420,9 +2420,10 @@ begin
 {$endif}
 
 { these cpus have an inline sar implementaion }
-{$if defined(x86) or defined(arm) or defined(powerpc) or defined(powerpc64)}
+{ currently, all supported CPUs have an internal sar implementation }
+{ $if defined(x86) or defined(arm) or defined(powerpc) or defined(powerpc64) or defined(sparc)}
   def_system_macro('FPC_HAS_INTERNAL_SAR');
-{$endif}
+{ $endif}
 
 {$ifdef powerpc64}
   def_system_macro('FPC_HAS_LWSYNC');

rtl/inc/systemh.inc

@@ -717,9 +717,10 @@ function RolQWord(Const AValue : QWord;Dist : Byte): QWord;{$ifdef SYSTEMINLINE}
 {$define FPC_HAS_INTERNAL_SAR_WORD}
 {$endif defined(cpux86_64) or defined(cpui386)}
 
-{$if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64)}
+{ currently, all supported CPUs have an internal 32 bit sar implementation }
+{ $if defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64)}
 {$define FPC_HAS_INTERNAL_SAR_DWORD}
-{$endif defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64)}
+{ $endif defined(cpux86_64) or defined(cpui386) or defined(arm) or defined(powerpc) or defined(powerpc64)}
 
 {$if defined(cpux86_64) or defined(powerpc64)}
 {$define FPC_HAS_INTERNAL_SAR_QWORD}