Added some APSR register bitmask definitions.

Fixed a bunch of instruction encodings by comparing bulks of handwritten tests to binutils assembled versions.
Fixed emission of regsets of S and D registers above 15.
Fixed assembler reader for RRX shiftmode.
There can be a size postfix after a condition code in UAL assembler syntax. This has been added to the assembler reader.

git-svn-id: branches/laksen/armiw@29277 -

compiler/arm/aasmcpu.pas

@@ -2035,7 +2035,7 @@ implementation
         { update condition flags
           or floating point single }
       if (oppostfix=PF_S) and
-        not(p^.code[0] in [#$04..#$0B,#$14..#$16,#$29,#$30]) then
+        not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30]) then
         begin
           Matches:=0;
           exit;
@@ -2228,6 +2228,7 @@ implementation
         var
           r : byte;
           imm : dword;
+          count : integer;
         begin
           case oper[op]^.typ of
             top_const:
@@ -2238,11 +2239,18 @@ implementation
                 else
                   begin
                     { calc rotate and adjust imm }
+                    count:=0;
                     r:=0;
                     imm:=dword(oper[op]^.val);
                     repeat
                       imm:=RolDWord(imm, 2);
-                      inc(r)
+                      inc(r);
+                      inc(count);
+                      if count > 32 then
+                        begin
+                          message1(asmw_e_invalid_opcode_and_operands, 'invalid shifter imm');
+                          exit;
+                        end;
                     until (imm and $ff)=imm;
                     bytes:=bytes or (r shl 8) or imm;
                   end;
@@ -2468,6 +2476,49 @@ implementation
               { always set S bit }
               bytes:=bytes or (1 shl 20);
             end;
+          #$10: // MRS
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              { set destination }
+              bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+
+              case oper[1]^.reg of
+                NR_APSR,NR_CPSR:;
+              else
+                Message(asmw_e_invalid_opcode_and_operands);
+              end;
+            end;
+          #$12,#$13: // MSR
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              { set destination }
+
+              if oper[0]^.typ=top_specialreg then
+                begin
+                  if oper[0]^.specialreg<>NR_CPSR then
+                    Message1(asmw_e_invalid_opcode_and_operands, 'Can only use CPSR in this form');
+
+                  if srF in oper[0]^.specialflags then
+                    bytes:=bytes or (2 shl 18);
+                  if srS in oper[0]^.specialflags then
+                    bytes:=bytes or (1 shl 18);
+                end
+              else
+                case oper[0]^.reg of
+                  NR_APSR_nzcvq: bytes:=bytes or (2 shl 18);
+                  NR_APSR_g: bytes:=bytes or (1 shl 18);
+                  NR_APSR_nzcvqg: bytes:=bytes or (3 shl 18);
+                else
+                  Message1(asmw_e_invalid_opcode_and_operands, 'Invalid combination APSR bits used');
+                end;
+
+              setshifterop(1);
+            end;
           #$14: // MUL/MLA r1,r2,r3
             begin
               { set instruction code }
@@ -2492,7 +2543,7 @@ implementation
               if ops>3 then
                 bytes:=bytes or getsupreg(oper[3]^.reg) shl 12
               else
-                bytes:=bytes or ($F shl 12);
+                bytes:=bytes or ord(insentry^.code[4]) shl 12;
 
               if oppostfix in [PF_R,PF_X] then
                 bytes:=bytes or (1 shl 5);
@@ -2505,8 +2556,18 @@ implementation
               bytes:=bytes or ord(insentry^.code[3]) shl 4;
               { set regs }
               bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
-              bytes:=bytes or getsupreg(oper[1]^.reg) shl 16;
-              bytes:=bytes or getsupreg(oper[2]^.reg);
+
+              if (ops=3) and (opcode=A_PKHTB) then
+                begin
+                  bytes:=bytes or getsupreg(oper[1]^.reg);
+                  bytes:=bytes or getsupreg(oper[2]^.reg) shl 16;
+                end
+              else
+                begin
+                  bytes:=bytes or getsupreg(oper[1]^.reg) shl 16;
+                  bytes:=bytes or getsupreg(oper[2]^.reg);
+                end;
+
               if ops=4 then
                 begin
                   if oper[3]^.typ=top_shifterop then
@@ -2731,6 +2792,50 @@ implementation
               bytes:=bytes or getsupreg(oper[3]^.reg) shl 16;
               bytes:=bytes or getcoprocreg(oper[4]^.reg);
             end;
+          #$1E: // LDRHT/STRHT
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+              { set Rn and Rd }
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+
+              refoper:=oper[1];
+
+              bytes:=bytes or getsupreg(refoper^.ref^.base) shl 16;
+              if getregtype(refoper^.ref^.index)=R_INVALIDREGISTER then
+                begin
+                  bytes:=bytes or (1 shl 22);
+                  { set offset }
+                  offset:=0;
+                  currsym:=objdata.symbolref(refoper^.ref^.symbol);
+                  if assigned(currsym) then
+                    offset:=currsym.offset-insoffset-8;
+                  offset:=offset+refoper^.ref^.offset;
+                  if offset>=0 then
+                    begin
+                      { set U flag }
+                      bytes:=bytes or (1 shl 23);
+                      bytes:=bytes or (offset and $F);
+                      bytes:=bytes or ((offset and $F0) shl 4);
+                    end
+                  else
+                    begin
+                      offset:=-offset;
+                      bytes:=bytes or (offset and $F);
+                      bytes:=bytes or ((offset and $F0) shl 4);
+                    end;
+                end
+              else
+                begin
+                  { set U flag }
+                  if refoper^.ref^.signindex>=0 then
+                    bytes:=bytes or (1 shl 23);
+                  bytes:=bytes or getsupreg(refoper^.ref^.index);
+                end;
+            end;
           #$22: // LDRH/STRH
             begin
               { set instruction code }
@@ -2915,7 +3020,10 @@ implementation
               bytes:=bytes or ord(insentry^.code[4]);
               { set opers }
               bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
-              bytes:=bytes or ((oper[1]^.val and $1F) shl 16);
+              if opcode in [A_SSAT, A_SSAT16] then
+                bytes:=bytes or (((oper[1]^.val-1) and $1F) shl 16)
+              else
+                bytes:=bytes or ((oper[1]^.val and $1F) shl 16);
               bytes:=bytes or getsupreg(oper[2]^.reg);
 
               if (ops>3) and
@@ -3201,6 +3309,8 @@ implementation
                     Rd:=getmmreg(oper[0]^.reg);
                     Rm:=getmmreg(oper[1]^.reg);
 
+                    bytes:=bytes or (1 shl 8);
+
                     bytes:=bytes or ((Rd and $F) shl 12);
                     bytes:=bytes or (((Rd and $10) shr 4) shl 22);
 
@@ -3476,7 +3586,7 @@ implementation
                 begin
                   if oper[0]^.typ=top_ref then
                     begin
-                      Rn:=getsupreg(oper[0]^.ref^.base);
+                      Rn:=getsupreg(oper[0]^.ref^.index);
 
                       if oper[0]^.ref^.addressmode<>AM_OFFSET then
                         begin

compiler/arm/agarmgas.pas

@@ -208,7 +208,7 @@ unit agarmgas;
       var
         hs : string;
         first : boolean;
-        r : tsuperregister;
+        r, rs : tsuperregister;
       begin
         case o.typ of
           top_reg:
@@ -230,14 +230,44 @@ unit agarmgas;
             begin
               getopstr:='{';
               first:=true;
-              for r:=RS_R0 to RS_R15 do
-                if r in o.regset^ then
-                  begin
-                    if not(first) then
-                      getopstr:=getopstr+',';
-                    getopstr:=getopstr+gas_regname(newreg(o.regtyp,r,o.subreg));
-                    first:=false;
-                  end;
+              if R_SUBFS=o.subreg then
+                begin
+                  for r:=0 to 31 do // S0 to S31
+                    if r in o.regset^ then
+                      begin
+                        if not(first) then
+                          getopstr:=getopstr+',';
+                        if odd(r) then
+                          rs:=(r shr 1)+RS_S1
+                        else
+                          rs:=(r shr 1)+RS_S0;
+                        getopstr:=getopstr+gas_regname(newreg(o.regtyp,rs,o.subreg));
+                        first:=false;
+                      end;
+                end
+              else if R_SUBFD=o.subreg then
+                begin
+                  for r:=0 to 31 do
+                    if r in o.regset^ then
+                      begin
+                        if not(first) then
+                          getopstr:=getopstr+',';
+                        rs:=r+RS_D0;
+                        getopstr:=getopstr+gas_regname(newreg(o.regtyp,rs,o.subreg));
+                        first:=false;
+                      end;
+                end
+              else
+                begin
+                  for r:=RS_R0 to RS_R15 do
+                    if r in o.regset^ then
+                      begin
+                        if not(first) then
+                          getopstr:=getopstr+',';
+                        getopstr:=getopstr+gas_regname(newreg(o.regtyp,r,o.subreg));
+                        first:=false;
+                      end;
+                end;
               getopstr:=getopstr+'}';
               if o.usermode then
                 getopstr:=getopstr+'^';

compiler/arm/armins.dat

@@ -98,8 +98,8 @@ reg32,reg32,immshifter      \7\x2\x80                     ARM32,ARMv4
 [ADFcc]
 
 [ADRcc]
-reg32,immshifter            \x33\x2\x0F                   ARM32,ARMv4
-reg32,imm32                 \x33\x2\x0F                   ARM32,ARMv4
+;reg32,immshifter            \x33\x2\x0F                   ARM32,ARMv4
+;reg32,imm32                 \x33\x2\x0F                   ARM32,ARMv4
 reg32,memam2                \x33\x2\x0F                   ARM32,ARMv4
 
 [ANDcc]
@@ -108,9 +108,8 @@ reg32,reg32,reg32,shifterop \x6\x0\x00                    ARM32,ARMv4
 reg32,reg32,immshifter      \x7\x2\x00                    ARM32,ARMv4
 
 [Bcc]
+imm24                       \x1\x0A                       ARM32,ARMv4
 mem32                       \x1\x0A                       ARM32,ARMv4
-imm                         \x1\x0A                       ARM32,ARMv4
-immshifter                  \x1\x0A                       ARM32,ARMv4
 
 [BICcc]
 reg32,reg32,reg32           \x6\x1\xC0                    ARM32,ARMv4
@@ -118,14 +117,12 @@ reg32,reg32,reg32,shifterop \x6\x1\xC0                    ARM32,ARMv4
 reg32,reg32,immshifter      \x7\x3\xC0                    ARM32,ARMv4
 
 [BLcc]
+imm24                    \x1\x0B                        ARM32,ARMv4
 mem32                    \x1\x0B                        ARM32,ARMv4
-imm                      \x1\x0B                        ARM32,ARMv4
-immshifter               \x1\x0B                        ARM32,ARMv4
 
 [BLX]
+imm24                    \x28\xB                       ARM32,ARMv5T
 mem32                    \x28\xB                       ARM32,ARMv5T
-imm                      \x28\xB                       ARM32,ARMv5T
-immshifter               \x28\xB                       ARM32,ARMv5T
 reg32                    \3\x01\x2F\xFF\x30            ARM32,ARMv5T
 
 [BKPTcc]
@@ -240,12 +237,11 @@ reg32,reg32,shifterop  \xA\x1\xA0                       ARM32,ARMv4
 reg32,immshifter       \xB\x1\xA0                       ARM32,ARMv4
 
 [MRScc]
-reg32,reg32         \x10\x01\x0F                        ARM32,ARMv4
+reg32,regf          \x10\x01\x0F                        ARM32,ARMv4
 
 [MSRcc]
-reg32,reg32         \x11\x01\x29\xF0                    ARM32,ARMv4
 regf,reg32          \x12\x01\x28\xF0                    ARM32,ARMv4
-regf,imm            \x13\x03\x28\xF0                    ARM32,ARMv4
+regf,immshifter     \x13\x03\x28\xF0                    ARM32,ARMv4
 
 [MULcc]
 reg32,reg32,reg32      \x14\x00\x00\x90          ARM32,ARMv4
@@ -388,7 +384,7 @@ reg32,reg32,reg32          \x1A\x01\x60\x05                    ARM32,ARMv5TE
 reg32,reg32,reg32          \x1A\x01\x20\x05                    ARM32,ARMv5TE
 
 [SMLABBcc]
-reg32,reg32,reg32,reg32     \x15\x01\x40\x8                     ARM32,ARMv5TE
+reg32,reg32,reg32,reg32     \x15\x01\x00\x8                     ARM32,ARMv5TE
 
 [SMLABTcc]
 reg32,reg32,reg32,reg32     \x15\x01\x00\xC                     ARM32,ARMv5TE
@@ -436,16 +432,16 @@ vreg,memam2             \x45\xD\x10\xA             ARM32,VFPv2
 vreg,memam2             \x45\xD\x0\xA              ARM32,VFPv2
 
 [SMULBBcc]
-reg32,reg32,reg32           \x15\x01\x60\x8                     ARM32,ARMv5TE
+reg32,reg32,reg32           \x15\x01\x60\x8\x0                  ARM32,ARMv5TE
 
 [SMULBTcc]
-reg32,reg32,reg32           \x15\x01\x60\xC                     ARM32,ARMv5TE
+reg32,reg32,reg32           \x15\x01\x60\xC\x0                  ARM32,ARMv5TE
 
 [SMULTBcc]
-reg32,reg32,reg32           \x15\x01\x60\xA                     ARM32,ARMv5TE
+reg32,reg32,reg32           \x15\x01\x60\xA\x0                  ARM32,ARMv5TE
 
 [SMULTTcc]
-reg32,reg32,reg32           \x15\x01\x60\xE                     ARM32,ARMv5TE
+reg32,reg32,reg32           \x15\x01\x60\xE\x0                  ARM32,ARMv5TE
 
 [SMULWBcc]
 reg32,reg32,reg32           \x14\x1\x20\xA0                     ARM32,ARMv5TE
@@ -457,22 +453,22 @@ reg32,reg32,reg32           \x14\x1\x20\xE0                     ARM32,ARMv5TE
 reg32,reg32,memam2        \x19\x0\x0\x0\xF0           ARM32,ARMv4
 
 [LDRHTcc]
-reg32,memam2              \x19\x0\x20\x0\xB0           ARM32,ARMv4
+reg32,memam2              \x19\x0\x30\x0\xB0           ARM32,ARMv4
 
 [STRHTcc]
-reg32,memam2              \x19\x0\x20\x0\xB0           ARM32,ARMv4
+reg32,memam2              \x1E\x0\x20\x0\xB0           ARM32,ARMv4
 
 [LDRSBTcc]
-reg32,memam2              \x19\x0\x30\x0\xD0           ARM32,ARMv4
+reg32,memam2              \x1E\x0\x30\x0\xD0           ARM32,ARMv4
 
 [STRSBTcc]
-reg32,memam2              \x19\x0\x30\x0\xD0           ARM32,ARMv4
+reg32,memam2              \x1E\x0\x30\x0\xD0           ARM32,ARMv4
 
 [LDRSHTcc]
-reg32,memam2              \x19\x0\x30\x0\xF0           ARM32,ARMv4
+reg32,memam2              \x1E\x0\x30\x0\xF0           ARM32,ARMv4
 
 [STRSHTcc]
-reg32,memam2              \x19\x0\x30\x0\xF0           ARM32,ARMv4
+reg32,memam2              \x1E\x0\x30\x0\xF0           ARM32,ARMv4
 
 [FSTDcc]
 
@@ -519,7 +515,7 @@ reg32,reg32,reg32           \x16\x6\x80\x1                     ARM32,ARMv6
 reg32,reg32,reg32,shifterop \x16\x6\x80\x1                     ARM32,ARMv6
 
 [PKHTBcc]
-reg32,reg32,reg32           \x16\x6\x80\x5                     ARM32,ARMv6
+reg32,reg32,reg32           \x16\x6\x80\x1                     ARM32,ARMv6
 reg32,reg32,reg32,shifterop \x16\x6\x80\x5                     ARM32,ARMv6
 
 [PLI]
@@ -539,7 +535,7 @@ reg32,reg32,reg32          \x16\x06\x20\xF7                    ARM32,ARMv6
 reg32,reg32,reg32          \x16\x06\x20\xFF                    ARM32,ARMv6
 
 [RBITcc]
-reg32,reg32                \x32\x6\xBF\xF\x30                  ARM32,ARMv6T2
+reg32,reg32                \x32\x6\xFF\xF\x30                  ARM32,ARMv6T2
 
 [REVcc]
 reg32,reg32                \x32\x6\xBF\xF\x30                  ARM32,ARMv6
@@ -566,7 +562,7 @@ reg32,reg32,immshifter,immshifter \x2D\x7\xA0\x0\x50           ARM32,ARMv6T2
 reg32,reg32,reg32          \x16\x06\x80\xFB                    ARM32,ARMv6
 
 [SETEND]
-imm                        \x2B\xF1\x01\x0\x0                  ARM32,ARMv6
+immshifter                 \x2B\xF1\x01\x0\x0                  ARM32,ARMv6
 
 [SEVcc]
 void                       \x2F\x3\x20\xF0\x4                  ARM32,ARMv6K
@@ -630,13 +626,13 @@ reg32,reg32,reg32,reg32    \x15\x7\x50\x1                      ARM32,ARMv6
 reg32,reg32,reg32,reg32    \x15\x7\x50\xD                      ARM32,ARMv6
 
 [SMMULcc]
-reg32,reg32,reg32          \x15\x7\x50\x1                      ARM32,ARMv6
+reg32,reg32,reg32          \x15\x7\x50\x1\xF                   ARM32,ARMv6
 
 [SMUADcc]
-reg32,reg32,reg32          \x15\x7\x00\x1                      ARM32,ARMv6
+reg32,reg32,reg32          \x15\x7\x00\x1\xF                   ARM32,ARMv6
 
 [SMUSDcc]
-reg32,reg32,reg32          \x15\x7\x00\x5                      ARM32,ARMv6
+reg32,reg32,reg32          \x15\x7\x00\x5\xF                   ARM32,ARMv6
 
 [SRScc]
 
@@ -645,7 +641,7 @@ reg32,immshifter,reg32            \x2A\x6\xA0\x0\x10                  ARM32,ARMv
 reg32,immshifter,reg32,shifterop  \x2A\x6\xA0\x0\x10                  ARM32,ARMv6
 
 [SSAT16cc]
-reg32,immshifter,reg32            \x2A\x6\xA0\x0\x30                  ARM32,ARMv6
+reg32,immshifter,reg32            \x2A\x6\xA0\xF\x30                  ARM32,ARMv6
 
 [SSAXcc]
 reg32,reg32,reg32          \x16\x06\x10\xF5                    ARM32,ARMv6
@@ -753,7 +749,7 @@ reg32,reg32,reg32          \x16\x06\x60\xF7                    ARM32,ARMv6
 reg32,reg32,reg32          \x16\x06\x60\xFF                    ARM32,ARMv6
 
 [USAD8cc]
-reg32,reg32,reg32          \x15\x07\x80\x01                    ARM32,ARMv6
+reg32,reg32,reg32          \x15\x07\x80\x01\xF                 ARM32,ARMv6
 
 [USADA8cc]
 reg32,reg32,reg32,reg32    \x15\x07\x80\x01                    ARM32,ARMv6
@@ -763,10 +759,10 @@ reg32,immshifter,reg32            \x2A\x6\xE0\x0\x10                  ARM32,ARMv
 reg32,immshifter,reg32,shifterop  \x2A\x6\xE0\x0\x10                  ARM32,ARMv6
 
 [USAT16cc]
-reg32,immshifter,reg32            \x2A\x6\xE0\x0\x30                  ARM32,ARMv6
+reg32,immshifter,reg32            \x2A\x6\xE0\xF\x30                  ARM32,ARMv6
 
 [USAXcc]
-reg32,reg32,reg32          \x16\x06\x50\xF6                    ARM32,ARMv6
+reg32,reg32,reg32          \x16\x06\x50\xF5                    ARM32,ARMv6
 
 [USUB16cc]
 reg32,reg32,reg32          \x16\x06\x50\xF7                    ARM32,ARMv6
@@ -905,7 +901,7 @@ void                          \x2F\x3\x20\xF0\x1               ARM32,ARMv6K
 ; Thumb-2
 
 [POP]
-reglist		                  \x26\x80		               ARM32,ARMv4
+reglist		                  \x26\x8B		               ARM32,ARMv4
 
 [PUSH]
 reglist		                  \x26\x80		               ARM32,ARMv4

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-339;
+333;

compiler/arm/armreg.dat

@@ -150,3 +150,6 @@ FPSID,$05,$00,$23,fpsid,0,0
 MVFR1,$05,$00,$24,mvfr1,0,0
 MVFR0,$05,$00,$25,mvfr0,0,0
 FPEXC,$05,$00,$26,fpexc,0,0
+APSR_nzcvq,$05,$00,$27,apsr_nzcvq,0,0
+APSR_g,$05,$00,$28,apsr_g,0,0
+APSR_nzcvqg,$05,$00,$29,apsr_nzcvqg,0,0

compiler/arm/armtab.inc

@@ -49,20 +49,6 @@
     code    : #7#2#128;
     flags   : if_arm32 or if_armv4
   ),
-  (
-    opcode  : A_ADR;
-    ops     : 2;
-    optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
-    code    : #51#2#15;
-    flags   : if_arm32 or if_armv4
-  ),
-  (
-    opcode  : A_ADR;
-    ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none);
-    code    : #51#2#15;
-    flags   : if_arm32 or if_armv4
-  ),
   (
     opcode  : A_ADR;
     ops     : 2;
@@ -94,21 +80,14 @@
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate24,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#10;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
-    code    : #1#10;
-    flags   : if_arm32 or if_armv4
-  ),
-  (
-    opcode  : A_B;
-    ops     : 1;
-    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#10;
     flags   : if_arm32 or if_armv4
   ),
@@ -136,42 +115,28 @@
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
-    code    : #1#11;
-    flags   : if_arm32 or if_armv4
-  ),
-  (
-    opcode  : A_BL;
-    ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate24,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#11;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #1#11;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_BLX;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_immediate24,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #40#11;
     flags   : if_arm32 or if_armv5t
   ),
   (
     opcode  : A_BLX;
     ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
-    code    : #40#11;
-    flags   : if_arm32 or if_armv5t
-  ),
-  (
-    opcode  : A_BLX;
-    ops     : 1;
-    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #40#11;
     flags   : if_arm32 or if_armv5t
   ),
@@ -500,17 +465,10 @@
   (
     opcode  : A_MRS;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_reg32,ot_regf,ot_none,ot_none,ot_none,ot_none);
     code    : #16#1#15;
     flags   : if_arm32 or if_armv4
   ),
-  (
-    opcode  : A_MSR;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
-    code    : #17#1#41#240;
-    flags   : if_arm32 or if_armv4
-  ),
   (
     opcode  : A_MSR;
     ops     : 2;
@@ -521,7 +479,7 @@
   (
     opcode  : A_MSR;
     ops     : 2;
-    optypes : (ot_regf,ot_immediate,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_regf,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
     code    : #19#3#40#240;
     flags   : if_arm32 or if_armv4
   ),
@@ -991,7 +949,7 @@
     opcode  : A_SMLABB;
     ops     : 4;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #21#1#64#8;
+    code    : #21#1#0#8;
     flags   : if_arm32 or if_armv5te
   ),
   (
@@ -1103,28 +1061,28 @@
     opcode  : A_SMULBB;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#1#96#8;
+    code    : #21#1#96#8#0;
     flags   : if_arm32 or if_armv5te
   ),
   (
     opcode  : A_SMULBT;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#1#96#12;
+    code    : #21#1#96#12#0;
     flags   : if_arm32 or if_armv5te
   ),
   (
     opcode  : A_SMULTB;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#1#96#10;
+    code    : #21#1#96#10#0;
     flags   : if_arm32 or if_armv5te
   ),
   (
     opcode  : A_SMULTT;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#1#96#14;
+    code    : #21#1#96#14#0;
     flags   : if_arm32 or if_armv5te
   ),
   (
@@ -1152,42 +1110,42 @@
     opcode  : A_LDRHT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#32#0#176;
+    code    : #25#0#48#0#176;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STRHT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#32#0#176;
+    code    : #30#0#32#0#176;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSBT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#48#0#208;
+    code    : #30#0#48#0#208;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STRSBT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#48#0#208;
+    code    : #30#0#48#0#208;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_LDRSHT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#48#0#240;
+    code    : #30#0#48#0#240;
     flags   : if_arm32 or if_armv4
   ),
   (
     opcode  : A_STRSHT;
     ops     : 2;
     optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
-    code    : #25#0#48#0#240;
+    code    : #30#0#48#0#240;
     flags   : if_arm32 or if_armv4
   ),
   (
@@ -1306,7 +1264,7 @@
     opcode  : A_PKHTB;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #22#6#128#5;
+    code    : #22#6#128#1;
     flags   : if_arm32 or if_armv6
   ),
   (
@@ -1369,7 +1327,7 @@
     opcode  : A_RBIT;
     ops     : 2;
     optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
-    code    : #50#6#191#15#48;
+    code    : #50#6#255#15#48;
     flags   : if_arm32 or if_armv6t2
   ),
   (
@@ -1431,7 +1389,7 @@
   (
     opcode  : A_SETEND;
     ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,ot_none,ot_none,ot_none);
+    optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #43#241#1#0#0;
     flags   : if_arm32 or if_armv6
   ),
@@ -1600,21 +1558,21 @@
     opcode  : A_SMMUL;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#7#80#1;
+    code    : #21#7#80#1#15;
     flags   : if_arm32 or if_armv6
   ),
   (
     opcode  : A_SMUAD;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#7#0#1;
+    code    : #21#7#0#1#15;
     flags   : if_arm32 or if_armv6
   ),
   (
     opcode  : A_SMUSD;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#7#0#5;
+    code    : #21#7#0#5#15;
     flags   : if_arm32 or if_armv6
   ),
   (
@@ -1635,7 +1593,7 @@
     opcode  : A_SSAT16;
     ops     : 3;
     optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #42#6#160#0#48;
+    code    : #42#6#160#15#48;
     flags   : if_arm32 or if_armv6
   ),
   (
@@ -1943,7 +1901,7 @@
     opcode  : A_USAD8;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #21#7#128#1;
+    code    : #21#7#128#1#15;
     flags   : if_arm32 or if_armv6
   ),
   (
@@ -1971,14 +1929,14 @@
     opcode  : A_USAT16;
     ops     : 3;
     optypes : (ot_reg32,ot_immediateshifter,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #42#6#224#0#48;
+    code    : #42#6#224#15#48;
     flags   : if_arm32 or if_armv6
   ),
   (
     opcode  : A_USAX;
     ops     : 3;
     optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
-    code    : #22#6#80#246;
+    code    : #22#6#80#245;
     flags   : if_arm32 or if_armv6
   ),
   (
@@ -2020,7 +1978,7 @@
     opcode  : A_POP;
     ops     : 1;
     optypes : (ot_reglist,ot_none,ot_none,ot_none,ot_none,ot_none);
-    code    : #38#128;
+    code    : #38#139;
     flags   : if_arm32 or if_armv4
   ),
   (

compiler/arm/raarmgas.pas

@@ -551,7 +551,7 @@ Unit raarmgas;
             else if (actasmpattern='ROR') then
               handlepara(SM_ROR)
             else if (actasmpattern='RRX') then
-              handlepara(SM_ROR)
+              handlepara(SM_RRX)
             else
               result:=false;
           end
@@ -1179,7 +1179,9 @@ Unit raarmgas;
                   ((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA,A_UMAAL,A_MLS,
                                                            A_SMLABB,A_SMLABT,A_SMLATB,A_SMLATT,A_SMMLA,A_SMMLS,A_SMLAD,A_SMLALD,A_SMLSD,
                                                            A_SMLALBB,A_SMLALBT,A_SMLALTB,A_SMLALTT,A_SMLSLD,
-                                                           A_MRC,A_MCR,A_MCRR,A_MRRC,A_STREXD,A_STRD,
+                                                           A_MRC,A_MCR,A_MCRR,A_MRRC,A_MRC2,A_MCR2,A_MCRR2,A_MRRC2,
+                                                           A_STREXD,A_STRD,
+                                                           A_USADA8,
                                                            A_VMOV,
                                                            A_SBFX,A_UBFX,A_BFI])) then
                   begin
@@ -1328,6 +1330,23 @@ Unit raarmgas;
                           end;
                       end;
                   end;
+                { check for postfix }
+                if (length(hs)>0) and (actoppostfix=PF_None) then
+                  begin
+                    for j:=low(postfixsorted) to high(postfixsorted) do
+                      begin
+                        if copy(hs,1,length(postfix2strsorted[j]))=postfix2strsorted[j] then
+                          begin
+                            if not ((length(hs)-length(postfix2strsorted[j])) = 0) then
+                              continue;
+
+                            actoppostfix:=postfixsorted[j];
+                            { strip postfix }
+                            delete(hs,1,length(postfix2strsorted[j]));
+                            break;
+                          end;
+                      end;
+                  end;
               end
             else
               begin

compiler/arm/rarmcon.inc

@@ -127,3 +127,6 @@ NR_FPSID = tregister($05000023);
 NR_MVFR1 = tregister($05000024);
 NR_MVFR0 = tregister($05000025);
 NR_FPEXC = tregister($05000026);
+NR_APSR_nzcvq = tregister($05000027);
+NR_APSR_g = tregister($05000028);
+NR_APSR_nzcvqg = tregister($05000029);

compiler/arm/rarmdwa.inc

@@ -126,4 +126,7 @@
 0,
 0,
 0,
+0,
+0,
+0,
 0

compiler/arm/rarmnor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armreg.dat }
-128
+131

compiler/arm/rarmnum.inc

@@ -126,4 +126,7 @@ tregister($05000022),
 tregister($05000023),
 tregister($05000024),
 tregister($05000025),
-tregister($05000026)
+tregister($05000026),
+tregister($05000027),
+tregister($05000028),
+tregister($05000029)

compiler/arm/rarmrni.inc

@@ -126,4 +126,7 @@
 124,
 125,
 126,
-127
+127,
+128,
+129,
+130

compiler/arm/rarmsri.inc

@@ -1,7 +1,10 @@
 { don't edit, this file is generated from armreg.dat }
 0,
 110,
+129,
 92,
+128,
+130,
 120,
 121,
 123,

compiler/arm/rarmsta.inc

@@ -126,4 +126,7 @@
 0,
 0,
 0,
+0,
+0,
+0,
 0

compiler/arm/rarmstd.inc

@@ -126,4 +126,7 @@
 'fpsid',
 'mvfr1',
 'mvfr0',
-'fpexc'
+'fpexc',
+'apsr_nzcvq',
+'apsr_g',
+'apsr_nzcvqg'

compiler/arm/rarmsup.inc

@@ -127,3 +127,6 @@ RS_FPSID = $23;
 RS_MVFR1 = $24;
 RS_MVFR0 = $25;
 RS_FPEXC = $26;
+RS_APSR_nzcvq = $27;
+RS_APSR_g = $28;
+RS_APSR_nzcvqg = $29;