* adapted tcgtypeconvnode.second_int_to_int() to work with high level cpu

    targets, and removed the (buggy) LLVM-specific version

git-svn-id: trunk@33980 -

compiler/llvm/nllvmcnv.pas

@@ -37,7 +37,7 @@ interface
           function first_int_to_real: tnode; override;
           function first_int_to_bool: tnode; override;
           function first_nil_to_methodprocvar: tnode; override;
-          procedure second_int_to_int;override;
+         { procedure second_int_to_int;override; }
          { procedure second_string_to_string;override; }
          { procedure second_cstring_to_pchar;override; }
          { procedure second_string_to_chararray;override; }
@@ -114,32 +114,6 @@ function tllvmtypeconvnode.first_nil_to_methodprocvar: tnode;
   end;
 
 
-procedure tllvmtypeconvnode.second_int_to_int;
-  var
-    fromsize, tosize: tcgint;
-    hreg: tregister;
-  begin
-    if not(nf_explicit in flags) then
-      hlcg.g_rangecheck(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef);
-    fromsize:=left.resultdef.size;
-    tosize:=resultdef.size;
-    location_copy(location,left.location);
-    if not(left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) or
-       ((fromsize<>tosize) and
-        not is_void(left.resultdef)) then
-      begin
-        hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,left.location.loc=LOC_CREGISTER);
-      end
-    else if left.resultdef<>resultdef then
-      begin
-        { just typecast the pointer type }
-        hreg:=hlcg.getaddressregister(current_asmdata.CurrAsmList,cpointerdef.getreusable(resultdef));
-        hlcg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.resultdef,cpointerdef.getreusable(resultdef),left.location.reference,hreg);
-        hlcg.reference_reset_base(location.reference,cpointerdef.getreusable(resultdef),hreg,0,location.reference.alignment);
-      end;
-  end;
-
-
 procedure tllvmtypeconvnode.second_pointer_to_array;
   var
     hreg: tregister;

compiler/ncgcnv.pas

@@ -108,6 +108,7 @@ interface
             if (location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) and
                (ressize<leftsize) then
               begin
+                hlcg.g_ptrtypecast_ref(current_asmdata.CurrAsmList,cpointerdef.getreusable(left.resultdef),cpointerdef.getreusable(resultdef),location.reference);
                 location.size:=newsize;
                 if (target_info.endian = ENDIAN_BIG) then
                   begin
@@ -115,7 +116,7 @@ interface
                     location.reference.alignment:=newalignment(location.reference.alignment,leftsize-ressize);
                   end;
               end
-{$if not defined(cpu16bitalu) and not defined(cpu8bitalu) and not defined(m68k)}
+{$if not defined(cpu16bitalu) and not defined(cpu8bitalu) and not defined(m68k) and not defined(cpuhighleveltarget)}
             { FIXME: reg_cgsize incorrectly identifies m68k as "without subregisters" }
             { On targets without 8/16 bit register components, 8/16-bit operations
               always adjust high bits of result, see 'maybeadjustresult' method in
@@ -149,7 +150,14 @@ interface
                 location.register := cg.getintregister(current_asmdata.CurrAsmList,newsize);
                 location.loc := LOC_REGISTER;
                 hlcg.a_load_reg_reg(current_asmdata.CurrAsmList,left.resultdef,resultdef,left.location.register,location.register);
-              end;
+              end
+            else if location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
+              hlcg.g_ptrtypecast_ref(current_asmdata.CurrAsmList,cpointerdef.getreusable(left.resultdef),cpointerdef.getreusable(resultdef),location.reference)
+{$ifdef cpuhighleveltarget}
+            { high level targets require the types to be correct in all cases }
+            else if left.resultdef<>resultdef then
+              hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,false);
+{$endif cpuhighleveltarget}
           end;
       end;