+ Add new LastCommonAsmOp constant to arm and aarch64 CPU targets.

  * Uses this new constant to define TCommonAsmOps set type.
  + Use this constant in armgen/aoptarm MatchInstruction function,
    to avoid a range check error when compiling with -CriotR with optimization.

git-svn-id: trunk@47137 -

compiler/aarch64/cpubase.pas

@@ -48,9 +48,6 @@ unit cpubase;
     type
       TAsmOp= {$i a64op.inc}
 
-      { See comment for this type in arm/cpubase.pas }
-      TCommonAsmOps = Set of A_NONE..A_MOV;
-
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];
 
@@ -59,6 +56,13 @@ unit cpubase;
       firstop = low(tasmop);
       { Last value of opcode enumeration  }
       lastop  = high(tasmop);
+      { Last value of opcode for TCommonAsmOps set below  }
+      LastCommonAsmOp = A_MOV;
+
+    type
+      { See comment for this type in arm/cpubase.pas }
+      TCommonAsmOps = Set of A_None .. LastCommonAsmOp;
+
 
 {*****************************************************************************
                                   Registers

compiler/arm/cpubase.pas

@@ -44,10 +44,6 @@ unit cpubase;
 
     type
       TAsmOp= {$i armop.inc}
-      {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
-       But FPC currently can't handle more than 256 elements in a set.}
-      TCommonAsmOps = Set of A_None .. A_UADD16;
-
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];
 
@@ -56,6 +52,14 @@ unit cpubase;
       firstop = low(tasmop);
       { Last value of opcode enumeration  }
       lastop  = high(tasmop);
+      { Last value of opcode for TCommonAsmOps set below  }
+      LastCommonAsmOp = A_UADD16;
+
+
+    type
+      {This is a bit of a hack, because there are more than 256 ARM Assembly Ops
+       But FPC currently can't handle more than 256 elements in a set.}
+      TCommonAsmOps = Set of A_None .. LastCommonAsmOp;
 
 {*****************************************************************************
                                   Registers

compiler/armgen/aoptarm.pas

@@ -87,7 +87,7 @@ Implementation
     begin
       result :=
         (instr.typ = ait_instruction) and
-        ((op = []) or ((ord(taicpu(instr).opcode)<256) and (taicpu(instr).opcode in op))) and
+        ((op = []) or ((taicpu(instr).opcode<=LastCommonAsmOp) and (taicpu(instr).opcode in op))) and
         ((cond = []) or (taicpu(instr).condition in cond)) and
         ((postfix = []) or (taicpu(instr).oppostfix in postfix));
     end;