* Xtensa: patch by Christo Crause to handle the sign extension architecture option, resolves #36885

git-svn-id: trunk@44689 -

compiler/xtensa/cgcpu.pas

@@ -179,14 +179,26 @@ implementation
                   list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,8));
                 OS_S8:
                   begin
-                    list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7));
+                    if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+                      list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,7))
+                    else
+                      begin
+                        list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,24));
+                        list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,24));
+                      end;
                     if tosize=OS_16 then
                       list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg2,0,16));
                   end;
                 OS_16:
                   list.concat(taicpu.op_reg_reg_const_const(A_EXTUI,reg2,reg1,0,16));
                 OS_S16:
-                  list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15));
+                  if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+                    list.concat(taicpu.op_reg_reg_const(A_SEXT,reg2,reg1,15))
+                  else
+                    begin
+                      list.concat(taicpu.op_reg_reg_const(A_SLLI,reg2,reg1,16));
+                      list.concat(taicpu.op_reg_reg_const(A_SRAI,reg2,reg2,16));
+                    end;
                 else
                   conv_done:=false;
               end;
@@ -270,7 +282,13 @@ implementation
         list.concat(taicpu.op_reg_ref(op,reg,href));
 
         if (fromsize=OS_S8) and not(tosize in [OS_S8,OS_8]) then
-          list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7));
+          if CPUXTENSA_HAS_SEXT in cpu_capabilities[current_settings.cputype] then
+            list.concat(taicpu.op_reg_reg_const(A_SEXT,reg,reg,7))
+          else
+            begin
+              list.concat(taicpu.op_reg_reg_const(A_SLLI,reg,reg,24));
+              list.concat(taicpu.op_reg_reg_const(A_SRAI,reg,reg,24));
+            end;
         if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
           a_load_reg_reg(list,fromsize,tosize,reg,reg);
       end;

compiler/xtensa/cpuinfo.pas

@@ -135,7 +135,8 @@ Const
  type
    tcpuflags =
       (
-        CPUXTENSA_REGWINDOW
+        CPUXTENSA_REGWINDOW,
+        CPUXTENSA_HAS_SEXT
       );
 
    tfpuflags =
@@ -149,7 +150,7 @@ Const
      (
        { cpu_none     } [],
        { cpu_lx106    } [],
-       { cpu_lx6      } [CPUXTENSA_REGWINDOW]
+       { cpu_lx6      } [CPUXTENSA_REGWINDOW, CPUXTENSA_HAS_SEXT]
      );
 
    fpu_capabilities : array[tfputype] of set of tfpuflags =

compiler/xtensa/xtensaatt.inc

@@ -48,6 +48,7 @@
 'sll',
 'slli',
 'sra',
+'srai',
 'srl',
 'srli',
 'ssi',

compiler/xtensa/xtensaop.inc

@@ -48,6 +48,7 @@ A_SEXT,
 A_SLL,
 A_SLLI,
 A_SRA,
+A_SRAI,
 A_SRL,
 A_SRLI,
 A_SSI,