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m68k: allow vecnode to use word size index registers

git-svn-id: trunk@43044 -
Károly Balogh 5 years ago
parent
commit
435b57bdb1
1 changed files with 12 additions and 3 deletions
  1. 12 3
      compiler/m68k/n68kmem.pas

+ 12 - 3
compiler/m68k/n68kmem.pas

@@ -35,6 +35,7 @@ interface
        t68kvecnode = class(tcgvecnode)
        t68kvecnode = class(tcgvecnode)
           procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
           procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
           procedure update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l:aint); override;
           procedure update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l:aint); override;
+          function valid_index_size(size: tcgsize): boolean; override;
           //procedure pass_generate_code;override;
           //procedure pass_generate_code;override;
        end;
        end;
 
 
@@ -54,6 +55,14 @@ implementation
                              T68KVECNODE
                              T68KVECNODE
 *****************************************************************************}
 *****************************************************************************}
 
 
+     function t68kvecnode.valid_index_size(size: tcgsize): boolean;
+       begin
+         if (CPUM68K_HAS_INDEXWORD in cpu_capabilities[current_settings.cputype]) then
+           result:=tcgsize2signed[size] in [OS_S16,OS_S32]
+         else
+           result:=inherited;
+       end;
+
     { this routine must, like any other routine, not change the contents }
     { this routine must, like any other routine, not change the contents }
     { of base/index registers of references, as these may be regvars.    }
     { of base/index registers of references, as these may be regvars.    }
     { The register allocator can coalesce one LOC_REGISTER being moved   }
     { The register allocator can coalesce one LOC_REGISTER being moved   }
@@ -77,8 +86,8 @@ implementation
                ((CPUM68K_HAS_INDEXSCALE8 in cpu_capabilities[current_settings.cputype]) and (l in [2,4,8]))) then
                ((CPUM68K_HAS_INDEXSCALE8 in cpu_capabilities[current_settings.cputype]) and (l in [2,4,8]))) then
               begin
               begin
                 //current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: mul')));
                 //current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: mul')));
-                hreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
-                cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,maybe_const_reg,hreg);
+                hreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_S32);
+                cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_IMUL,def_cgsize(regsize),l,maybe_const_reg,hreg);
                 maybe_const_reg:=hreg;
                 maybe_const_reg:=hreg;
               end
               end
             else
             else
@@ -95,7 +104,7 @@ implementation
               begin
               begin
                 //current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: copytoa')));
                 //current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: copytoa')));
                 hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
                 hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
-                cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_ADDR,OS_ADDR,maybe_const_reg,hreg);
+                cg.a_load_reg_reg(current_asmdata.CurrAsmList,def_cgsize(regsize),OS_ADDR,maybe_const_reg,hreg);
                 maybe_const_reg:=hreg;
                 maybe_const_reg:=hreg;
               end;
               end;
             location.reference.base:=maybe_const_reg;
             location.reference.base:=maybe_const_reg;