Add most pre-UAL VFP instruction forms.

Add fused mac instructions for VFPv4.

git-svn-id: trunk@30187 -

compiler/arm/aasmcpu.pas

@@ -179,7 +179,7 @@ uses
         ops     : byte;
         optypes : array[0..5] of longint;
         code    : array[0..maxinfolen] of char;
-        flags   : longint;
+        flags   : longword;
       end;
 
       pinsentry=^tinsentry;
@@ -2024,7 +2024,7 @@ implementation
             IF_ARMv4T or IF_ARMv5T or IF_ARMv6T2 or IF_ARMv7M or IF_ARMv7EM
           );
 
-        FPUMasks: array[tfputype] of longint =
+        FPUMasks: array[tfputype] of longword =
           (
             IF_NONE,
             IF_NONE,
@@ -2167,7 +2167,10 @@ implementation
                         ot:=ot or OT_AM2;
 
                       if (ref^.index<>NR_NO) and
-                        (oppostfix in [PF_None,PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
+                        (oppostfix in [PF_None,PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA,
+                                       PF_IAD,PF_DBD,PF_FDD,PF_EAD,
+                                       PF_IAS,PF_DBS,PF_FDS,PF_EAS,
+                                       PF_IAX,PF_DBX,PF_FDX,PF_EAX]) and
                         (
                           (ref^.base=NR_NO) and
                           (ref^.shiftmode=SM_None) and
@@ -2333,7 +2336,7 @@ implementation
         { update condition flags
           or floating point single }
       if (oppostfix=PF_S) and
-        not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30,#$60..#$6B,#$80..#$82,#$A0..#$A2]) then
+        not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30,#$60..#$6B,#$80..#$82,#$A0..#$A2,#$44,#$94,#$42,#$92]) then
         begin
           Matches:=0;
           exit;
@@ -2341,7 +2344,13 @@ implementation
 
       { floating point size }
       if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
-        not(p^.code[0] in [#$A0..#$A2]) then
+        not(p^.code[0] in [
+          // FPA
+          #$A0..#$A2,
+          // old-school VFP
+          #$42,#$92,
+          // vldm/vstm
+          #$44,#$94]) then
         begin
           Matches:=0;
           exit;
@@ -3768,7 +3777,8 @@ implementation
               bytes:=bytes or (ord(insentry^.code[3]) shl 8);
               bytes:=bytes or ord(insentry^.code[4]);
               { set regs }
-              if opcode=A_VMRS then
+              if (opcode=A_VMRS) or
+                 (opcode=A_FMRX) then
                 begin
                   case oper[1]^.reg of
                     NR_FPSID: Rn:=$0;
@@ -3818,6 +3828,12 @@ implementation
                   Rn:=getmmreg(oper[1]^.reg);
                   Rm:=getmmreg(oper[2]^.reg);
                 end
+              else if ops=1 then
+                begin
+                  Rd:=getmmreg(oper[0]^.reg);
+                  Rn:=0;
+                  Rm:=0;
+                end
               else if oper[1]^.typ=top_const then
                 begin
                   Rd:=getmmreg(oper[0]^.reg);
@@ -3831,7 +3847,7 @@ implementation
                   Rm:=getmmreg(oper[1]^.reg);
                 end;
 
-              if oppostfix=PF_F32 then
+              if (oppostfix=PF_F32) or (insentry^.code[5]=#1) then
                 begin
                   D:=rd and $1; Rd:=Rd shr 1;
                   N:=rn and $1; Rn:=Rn shr 1;
@@ -3887,6 +3903,55 @@ implementation
                   bytes:=bytes or (Rd shl 12);
                   bytes:=bytes or (Rm shl 0);
 
+                  bytes:=bytes or (D shl 22);
+                  bytes:=bytes or (M shl 5);
+                end
+              else if (ops=2) and
+                      (oppostfix=PF_None) then
+                begin
+                  d:=0;
+                  case getsubreg(oper[0]^.reg) of
+                    R_SUBNONE:
+                      rd:=getsupreg(oper[0]^.reg);
+                    R_SUBFS:
+                      begin
+                        rd:=getmmreg(oper[0]^.reg);
+
+                        d:=rd and 1;
+                        rd:=rd shr 1;
+                      end;
+                    R_SUBFD:
+                      begin
+                        rd:=getmmreg(oper[0]^.reg);
+
+                        d:=(rd shr 4) and 1;
+                        rd:=rd and $F;
+                      end;
+                  end;
+
+                  m:=0;
+                  case getsubreg(oper[1]^.reg) of
+                    R_SUBNONE:
+                      rm:=getsupreg(oper[1]^.reg);
+                    R_SUBFS:
+                      begin
+                        rm:=getmmreg(oper[1]^.reg);
+
+                        m:=rm and 1;
+                        rm:=rm shr 1;
+                      end;
+                    R_SUBFD:
+                      begin
+                        rm:=getmmreg(oper[1]^.reg);
+
+                        m:=(rm shr 4) and 1;
+                        rm:=rm and $F;
+                      end;
+                  end;
+
+                  bytes:=bytes or (Rd shl 12);
+                  bytes:=bytes or (Rm shl 0);
+
                   bytes:=bytes or (D shl 22);
                   bytes:=bytes or (M shl 5);
                 end
@@ -4034,14 +4099,14 @@ implementation
                           { set W }
                           bytes:=bytes or (1 shl 21);
                         end
-                      else if oppostfix = PF_DB then
+                      else if oppostfix in [PF_DB,PF_DBS,PF_DBD,PF_DBX] then
                         message1(asmw_e_invalid_opcode_and_operands, 'Invalid postfix without writeback');
                     end
                   else
                     begin
                       Rn:=getsupreg(oper[0]^.reg);
 
-                      if oppostfix = PF_DB then
+                      if oppostfix in [PF_DB,PF_DBS,PF_DBD,PF_DBX] then
                         message1(asmw_e_invalid_opcode_and_operands, 'Invalid postfix without writeback');
                     end;
 
@@ -4050,12 +4115,20 @@ implementation
                   { Set PU bits }
                   case oppostfix of
                     PF_None,
-                    PF_IA:
+                    PF_IA,PF_IAS,PF_IAD,PF_IAX:
                       bytes:=bytes or (1 shl 23);
-                    PF_DB:
+                    PF_DB,PF_DBS,PF_DBD,PF_DBX:
                       bytes:=bytes or (2 shl 23);
                   end;
 
+                  case oppostfix of
+                    PF_IAX,PF_DBX,PF_FDX,PF_EAX:
+                      begin
+                        bytes:=bytes or (1 shl 8);
+                        bytes:=bytes or (1 shl 0); // Offset is odd
+                      end;
+                  end;
+
                   dp_operation:=(oper[1]^.subreg=R_SUBFD);
                   if oper[1]^.regset^=[] then
                     message1(asmw_e_invalid_opcode_and_operands, 'Regset cannot be empty');

compiler/arm/armatt.inc

@@ -215,13 +215,13 @@
 'faddd',
 'fadds',
 'fcmpd',
+'fcmps',
 'fcmped',
 'fcmpes',
-'fcmpezd',
-'fcmpezs',
-'fcmps',
 'fcmpzd',
 'fcmpzs',
+'fcmpezd',
+'fcmpezs',
 'fcpyd',
 'fcpys',
 'fcvtds',

compiler/arm/armins.dat

@@ -299,7 +299,6 @@ reg32,reg32         \321\300\1\x11\101            ARM32,ARMv4
 [LDMcc]
 memam4,reglist              \x69\xC8            THUMB,ARMv4T
 reglo,reglist               \x69\xC8            THUMB,ARMv4T
-reg32,reglist		   \x26\x81			ARM7
 
 memam4,reglist              \x8C\xE8\x10\x0\x0  THUMB32,WIDE,ARMv6T2
 reg32,reglist               \x8C\xE8\x10\x0\x0  THUMB32,WIDE,ARMv6T2
@@ -756,14 +755,22 @@ reg32,memam2               \x88\xF9\x10\xE\x0\0                THUMB32,ARMv6T2
 reg32,memam2               \x1E\x0\x30\x0\xD0                  ARM32,ARMv4
 
 [LDRSHTcc]
-reg32,memam2              \x88\xF9\x30\xE\x0\0         THUMB32,ARMv6T2
-reg32,memam2              \x1E\x0\x30\x0\xF0           ARM32,ARMv4
+reg32,memam2              \x88\xF9\x30\xE\x0\0                 THUMB32,ARMv6T2
+reg32,memam2              \x1E\x0\x30\x0\xF0                   ARM32,ARMv4
 
 [FSTDcc]
+vreg,memam2             \x95\xED\x0\xA                         THUMB32,VFPv2
+vreg,memam2             \x45\xD\x0\xA                          ARM32,VFPv2
 
 [FSTMcc]
+memam4,reglist		      \x94\xEC\x00\xA		                  THUMB32,VFPv2
+reg32,reglist		      \x94\xEC\x00\xA		                  THUMB32,VFPv2
+memam4,reglist		      \x44\xC\x00\xA		                     ARM32,VFPv2
+reg32,reglist		      \x44\xC\x00\xA		                     ARM32,VFPv2
 
 [FSTScc]
+vreg,memam2             \x95\xED\x0\xA                         THUMB32,VFPv2
+vreg,memam2             \x45\xD\x0\xA                          ARM32,VFPv2
 
 ; ARMv6
 
@@ -1253,50 +1260,98 @@ void                          \x2F\x3\x20\xF0\x1               ARM32,ARMv6K
 ; vfp instructions
 ;
 [FABSDcc]
+vreg,vreg               \x92\xEE\xB0\xA\xC0\0        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB0\xA\xC0\0         ARM32,VFPv2
 
 [FABSScc]
+vreg,vreg               \x92\xEE\xB0\xA\xC0\1        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB0\xA\xC0\1         ARM32,VFPv2
 
 [FADDDcc]
+vreg,vreg,vreg          \x92\xEE\x30\xA\x0\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x30\xA\x0\0          ARM32,VFPv2
 
 [FADDScc]
+vreg,vreg,vreg          \x92\xEE\x30\xA\x0\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x30\xA\x0\1          ARM32,VFPv2
 
 [FCMPDcc]
+vreg,vreg               \x92\xEE\xB4\xA\x40\0        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB4\xA\x40\0         ARM32,VFPv2
+
+[FCMPScc]
+vreg,vreg               \x92\xEE\xB4\xA\x40\1        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB4\xA\x40\1         ARM32,VFPv2
 
 [FCMPEDcc]
+vreg,vreg               \x92\xEE\xB4\xA\xC0\0        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB4\xA\xC0\0         ARM32,VFPv2
 
 [FCMPEScc]
-
-[FCMPEZDcc]
-
-[FCMPEZScc]
-
-[FCMPScc]
+vreg,vreg               \x92\xEE\xB4\xA\xC0\1        THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB4\xA\xC0\1         ARM32,VFPv2
 
 [FCMPZDcc]
+vreg                    \x92\xEE\xB5\xA\x40\0        THUMB32,VFPv2
+vreg                    \x42\xE\xB5\xA\x40\0         ARM32,VFPv2
 
 [FCMPZScc]
+vreg                    \x92\xEE\xB5\xA\x40\1        THUMB32,VFPv2
+vreg                    \x42\xE\xB5\xA\x40\1         ARM32,VFPv2
+
+[FCMPEZDcc]
+vreg                    \x92\xEE\xB5\xA\xC0\0        THUMB32,VFPv2
+vreg                    \x42\xE\xB5\xA\xC0\0         ARM32,VFPv2
+
+[FCMPEZScc]
+vreg                    \x92\xEE\xB5\xA\xC0\1        THUMB32,VFPv2
+vreg                    \x42\xE\xB5\xA\xC0\1         ARM32,VFPv2
 
 [FCPYDcc]
+vreg,vreg               \x43\xEE\xB0\xB\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB0\xB\x40           ARM32,VFPv2
 
 [FCPYScc]
+vreg,vreg               \x43\xEE\xB0\xA\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB0\xA\x40           ARM32,VFPv2
 
 [FCVTDScc]
+vreg,vreg               \x43\xEE\xB7\xA\xC0          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB7\xA\xC0           ARM32,VFPv2
 
 [FCVTSDcc]
+vreg,vreg               \x43\xEE\xB7\xB\xC0          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB7\xB\xC0           ARM32,VFPv2
 
 [FDIVDcc]
+vreg,vreg,vreg          \x92\xEE\x80\xA\x0\0          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x80\xA\x0\0           ARM32,VFPv2
 
 [FDIVScc]
+vreg,vreg,vreg          \x92\xEE\x80\xA\x0\1          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x80\xA\x0\1           ARM32,VFPv2
 
 [FLDDcc]
+vreg,memam2             \x95\xED\x10\xA               THUMB32,VFPv2
+vreg,memam2             \x45\xD\x10\xA                ARM32,VFPv2
 
 [FLDMcc]
+memam4,reglist		      \x94\xEC\x10\xA		         THUMB32,VFPv2
+reg32,reglist		      \x94\xEC\x10\xA		         THUMB32,VFPv2
+memam4,reglist		      \x44\xC\x10\xA		            ARM32,VFPv2
+reg32,reglist		      \x44\xC\x10\xA		            ARM32,VFPv2
 
 [FLDScc]
+vreg,memam2             \x95\xED\x10\xA               THUMB32,VFPv2
+vreg,memam2             \x45\xD\x10\xA                ARM32,VFPv2
 
 [FMACDcc]
+vreg,vreg,vreg          \x92\xEE\x0\xA\x00\0          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x0\xA\x00\0           ARM32,VFPv2
 
 [FMACScc]
+vreg,vreg,vreg          \x92\xEE\x0\xA\x00\1          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x0\xA\x00\1           ARM32,VFPv2
 
 [FMDHRcc]
 
@@ -1307,62 +1362,122 @@ void                          \x2F\x3\x20\xF0\x1               ARM32,ARMv6K
 [FMRDLcc]
 
 [FMRScc]
+reg32,vreg              \x90\xEE\x10\xA\x10           THUMB32,VFPv2
+reg32,vreg              \x40\xE\x10\xA\x10            ARM32,VFPv2
 
 [FMRXcc]
+reg32,regf              \x91\xEE\xF0\xA\x10           THUMB32,VFPv2
+regf,regf               \x91\xEE\xF0\xA\x10           THUMB32,VFPv2
+reg32,regf              \x41\xE\xF0\xA\x10            ARM32,VFPv2
+regf,regf               \x41\xE\xF0\xA\x10            ARM32,VFPv2
 
 [FMSCDcc]
+vreg,vreg,vreg          \x92\xEE\x10\xA\x00\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x10\xA\x00\0          ARM32,VFPv2
 
 [FMSCScc]
+vreg,vreg,vreg          \x92\xEE\x10\xA\x00\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x10\xA\x00\1          ARM32,VFPv2
 
 [FMSRcc]
+vreg,reg32              \x90\xEE\x00\xA\x10           THUMB32,VFPv2
+vreg,reg32              \x40\xE\x00\xA\x10            ARM32,VFPv2
 
 [FMSTATcc]
+void                    \x80\xEE\xF1\xFA\x10          THUMB32,VFPv2
+void                    \x2F\xE\xF1\xFA\x10           ARM32,VFPv2
 
 [FMULDcc]
+vreg,vreg,vreg          \x92\xEE\x20\xA\x0\0          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x20\xA\x0\0           ARM32,VFPv2
 
 [FMULScc]
+vreg,vreg,vreg          \x92\xEE\x20\xA\x0\1          THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x20\xA\x0\1           ARM32,VFPv2
 
 [FMXRcc]
+regf,reg32              \x91\xEE\xE0\xA\x10           THUMB32,VFPv2
+regf,reg32              \x41\xE\xE0\xA\x10            ARM32,VFPv2
 
 [FNEGDcc]
+vreg,vreg               \x92\xEE\xB1\xA\x40\0         THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB1\xA\x40\0          ARM32,VFPv2
 
 [FNEGScc]
+vreg,vreg               \x92\xEE\xB1\xA\x40\1         THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB1\xA\x40\1          ARM32,VFPv2
 
 [FNMACDcc]
+vreg,vreg,vreg          \x92\xEE\x00\xA\x40\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x00\xA\x40\0          ARM32,VFPv2
 
 [FNMACScc]
+vreg,vreg,vreg          \x92\xEE\x00\xA\x40\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x00\xA\x40\1          ARM32,VFPv2
 
 [FNMSCDcc]
+vreg,vreg,vreg          \x92\xEE\x10\xA\x40\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x10\xA\x40\0          ARM32,VFPv2
 
 [FNMSCScc]
+vreg,vreg,vreg          \x92\xEE\x10\xA\x40\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x10\xA\x40\1          ARM32,VFPv2
 
 [FNMULDcc]
+vreg,vreg,vreg          \x92\xEE\x20\xA\x40\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x20\xA\x40\0          ARM32,VFPv2
 
 [FNMULScc]
+vreg,vreg,vreg          \x92\xEE\x20\xA\x40\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x20\xA\x40\1          ARM32,VFPv2
 
 [FSITODcc]
+vreg,vreg               \x43\xEE\xB8\xB\xC0          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB8\xB\xC0           ARM32,VFPv2
 
 [FSITOScc]
+vreg,vreg               \x43\xEE\xB8\xA\xC0          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB8\xA\xC0           ARM32,VFPv2
 
 [FSQRTDcc]
+vreg,vreg               \x92\xEE\xB1\xA\xC0\0         THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB1\xA\xC0\0          ARM32,VFPv2
 
 [FSQRTScc]
+vreg,vreg               \x92\xEE\xB1\xA\xC0\1         THUMB32,VFPv2
+vreg,vreg               \x42\xE\xB1\xA\xC0\1          ARM32,VFPv2
 
 [FSUBDcc]
+vreg,vreg,vreg          \x92\xEE\x30\xA\x40\0         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x30\xA\x40\0          ARM32,VFPv2
 
 [FSUBScc]
+vreg,vreg,vreg          \x92\xEE\x30\xA\x40\1         THUMB32,VFPv2
+vreg,vreg,vreg          \x42\xE\x30\xA\x40\1          ARM32,VFPv2
 
 [FTOSIDcc]
+vreg,vreg               \x43\xEE\xBD\xB\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xBD\xB\x40           ARM32,VFPv2
 
 [FTOSIScc]
+vreg,vreg               \x43\xEE\xBD\xA\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xBD\xA\x40           ARM32,VFPv2
 
 [FTOUIDcc]
+vreg,vreg               \x43\xEE\xBC\xB\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xBC\xB\x40           ARM32,VFPv2
 
 [FTOUIScc]
+vreg,vreg               \x43\xEE\xBC\xA\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xBC\xA\x40           ARM32,VFPv2
 
 [FUITODcc]
+vreg,vreg               \x43\xEE\xB8\xB\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB8\xB\x40           ARM32,VFPv2
 
 [FUITOScc]
+vreg,vreg               \x43\xEE\xB8\xA\x40          THUMB32,VFPv2
+vreg,vreg               \x43\xE\xB8\xA\x40           ARM32,VFPv2
 
 [FMDRRcc]
 
@@ -1544,9 +1659,20 @@ vreg,vreg,vreg          \x92\xEE\x20\xA\x40         THUMB32,VFPv2
 vreg,vreg,vreg          \x42\xE\x20\xA\x40         ARM32,VFPv2
 
 [VFMA]
+vreg,vreg,vreg          \x92\xEE\xA0\xA\x00          THUMB32,VFPv4
+vreg,vreg,vreg          \x42\xE\xA0\xA\x00          ARM32,VFPv4
+
 [VFMS]
+vreg,vreg,vreg          \x92\xEE\xA0\xA\x40          THUMB32,VFPv4
+vreg,vreg,vreg          \x42\xE\xA0\xA\x40          ARM32,VFPv4
+
 [VFNMA]
+vreg,vreg,vreg          \x92\xEE\x90\xA\x00          THUMB32,VFPv4
+vreg,vreg,vreg          \x42\xE\x90\xA\x00          ARM32,VFPv4
+
 [VFNMS]
+vreg,vreg,vreg          \x92\xEE\x90\xA\x40          THUMB32,VFPv4
+vreg,vreg,vreg          \x42\xE\x90\xA\x40          ARM32,VFPv4
 
 [VNEGcc]
 vreg,vreg               \x92\xEE\xB1\xA\x40         THUMB32,VFPv2

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-828;
+952;

compiler/arm/armop.inc

@@ -215,13 +215,13 @@ A_FABSS,
 A_FADDD,
 A_FADDS,
 A_FCMPD,
+A_FCMPS,
 A_FCMPED,
 A_FCMPES,
-A_FCMPEZD,
-A_FCMPEZS,
-A_FCMPS,
 A_FCMPZD,
 A_FCMPZS,
+A_FCMPEZD,
+A_FCMPEZS,
 A_FCPYD,
 A_FCPYS,
 A_FCVTDS,