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@@ -39,6 +39,7 @@ Interface
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TCpuAsmOptimizer = class(TARMAsmOptimizer)
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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+ function PeepHoleOptPass2Cpu(var p: tai): boolean; override;
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function PostPeepHoleOptsCpu(var p: tai): boolean; override;
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function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;override;
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function InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;override;
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@@ -51,6 +52,8 @@ Interface
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function OptPass1STP(var p: tai): boolean;
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function OptPass1Mov(var p: tai): boolean;
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function OptPass1FMov(var p: tai): Boolean;
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+
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+ function OptPass2LDRSTR(var p: tai): boolean;
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End;
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Implementation
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@@ -526,6 +529,164 @@ Implementation
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end;
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+ function TCpuAsmOptimizer.OptPass2LDRSTR(var p: tai): boolean;
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+ var
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+ hp1, hp1_last: tai;
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+ ThisRegister: TRegister;
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+ OffsetVal, ValidOffset, MinOffset, MaxOffset: asizeint;
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+ TargetOpcode: TAsmOp;
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+ Breakout: Boolean;
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+ begin
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+ Result := False;
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+ ThisRegister := taicpu(p).oper[0]^.reg;
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+
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+ case taicpu(p).opcode of
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+ A_LDR:
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+ TargetOpcode := A_LDP;
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+ A_STR:
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+ TargetOpcode := A_STP;
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+ else
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+ InternalError(2020081501);
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+ end;
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+
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+ { reg appearing in ref invalidates these optimisations }
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+ if (TargetOpcode = A_STP) or not RegInRef(ThisRegister, taicpu(p).oper[1]^.ref^) then
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+ begin
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+ { LDP/STP has a smaller permitted offset range than LDR/STR.
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+
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+ TODO: For a group of out-of-range LDR/STR instructions, can
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+ we declare a temporary register equal to the offset base
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+ address, modify the STR instructions to use that register
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+ and then convert them to STP instructions? Note that STR
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+ generally takes 2 cycles (on top of the memory latency),
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+ while LDP/STP takes 3.
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+ }
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+
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+ if (getsubreg(ThisRegister) = R_SUBQ) then
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+ begin
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+ ValidOffset := 8;
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+ MinOffset := -512;
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+ MaxOffset := 504;
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+ end
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+ else
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+ begin
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+ ValidOffset := 4;
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+ MinOffset := -256;
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+ MaxOffset := 252;
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+ end;
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+
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+ hp1_last := p;
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+
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+ { Look for nearby LDR/STR instructions }
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+ if (taicpu(p).oppostfix = PF_NONE) and
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+ (taicpu(p).oper[1]^.ref^.addressmode = AM_OFFSET) then
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+ { If SkipGetNext is True, GextNextInstruction isn't called }
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+ while GetNextInstruction(hp1_last, hp1) do
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+ begin
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+ if (hp1.typ <> ait_instruction) then
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+ Break;
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+
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+ if (taicpu(hp1).opcode = taicpu(p).opcode) then
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+ begin
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+ Breakout := False;
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+
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+ if (taicpu(hp1).oppostfix = PF_NONE) and
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+ { Registers need to be the same size }
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+ (getsubreg(ThisRegister) = getsubreg(taicpu(hp1).oper[0]^.reg)) and
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+ (
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+ (TargetOpcode = A_STP) or
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+ { LDP x0, x0, [sp, #imm] is undefined behaviour, even
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+ though such an LDR pair should have been optimised
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+ out by now. STP is okay }
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+ (ThisRegister <> taicpu(hp1).oper[0]^.reg)
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+ ) and
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+ (taicpu(hp1).oper[1]^.ref^.addressmode = AM_OFFSET) and
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+ (taicpu(p).oper[1]^.ref^.base = taicpu(hp1).oper[1]^.ref^.base) and
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+ (taicpu(p).oper[1]^.ref^.index = taicpu(hp1).oper[1]^.ref^.index) and
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+ { Make sure the address registers haven't changed }
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+ not RegModifiedBetween(taicpu(hp1).oper[1]^.ref^.base, p, hp1) and
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+ (
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+ (taicpu(hp1).oper[1]^.ref^.index = NR_NO) or
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+ not RegModifiedBetween(taicpu(hp1).oper[1]^.ref^.index, p, hp1)
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+ ) and
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+ { Don't need to check "RegInRef" because the base registers are identical,
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+ and the first one was checked already. [Kit] }
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+ (((TargetOpcode=A_LDP) and not RegUsedBetween(taicpu(hp1).oper[0]^.reg, p, hp1)) or
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+ ((TargetOpcode=A_STP) and not RegModifiedBetween(taicpu(hp1).oper[0]^.reg, p, hp1))) then
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+ begin
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+ { Can we convert these two LDR/STR instructions into a
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+ single LDR/STP? }
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+
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+ OffsetVal := taicpu(hp1).oper[1]^.ref^.offset - taicpu(p).oper[1]^.ref^.offset;
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+ if (OffsetVal = ValidOffset) then
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+ begin
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+ if (taicpu(p).oper[1]^.ref^.offset >= MinOffset) and (taicpu(hp1).oper[1]^.ref^.offset <= MaxOffset) then
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+ begin
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+ { Convert:
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+ LDR/STR reg0, [reg2, #ofs]
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+ ...
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+ LDR/STR reg1. [reg2, #ofs + 8] // 4 if registers are 32-bit
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+ To:
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+ LDP/STP reg0, reg1, [reg2, #ofs]
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+ }
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+ taicpu(p).opcode := TargetOpcode;
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+ if TargetOpcode = A_STP then
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+ DebugMsg('Peephole Optimization: StrStr2Stp', p)
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+ else
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+ DebugMsg('Peephole Optimization: LdrLdr2Ldp', p);
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+ taicpu(p).ops := 3;
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+ taicpu(p).loadref(2, taicpu(p).oper[1]^.ref^);
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+ taicpu(p).loadreg(1, taicpu(hp1).oper[0]^.reg);
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+
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+ asml.Remove(hp1);
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+ hp1.Free;
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+ Result := True;
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+ Exit;
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+ end;
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+ end
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+ else if (OffsetVal = -ValidOffset) then
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+ begin
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+ if (taicpu(hp1).oper[1]^.ref^.offset >= MinOffset) and (taicpu(p).oper[1]^.ref^.offset <= MaxOffset) then
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+ begin
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+ { Convert:
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+ LDR/STR reg0, [reg2, #ofs + 8] // 4 if registers are 32-bit
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+ ...
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+ LDR/STR reg1. [reg2, #ofs]
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+ To:
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+ LDP/STP reg1, reg0, [reg2, #ofs]
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+ }
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+ taicpu(p).opcode := TargetOpcode;
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+ if TargetOpcode = A_STP then
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+ DebugMsg('Peephole Optimization: StrStr2Stp (reverse)', p)
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+ else
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+ DebugMsg('Peephole Optimization: LdrLdr2Ldp (reverse)', p);
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+ taicpu(p).ops := 3;
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+ taicpu(p).loadref(2, taicpu(hp1).oper[1]^.ref^);
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+ taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
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+ taicpu(p).loadreg(0, taicpu(hp1).oper[0]^.reg);
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+
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+ asml.Remove(hp1);
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+ hp1.Free;
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+ Result := True;
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+ Exit;
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+ end;
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+ end;
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+ end;
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+ end
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+ else
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+ Break;
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+
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+ { Don't continue looking for LDR/STR pairs if the address register
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+ gets modified }
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+ if RegModifiedByInstruction(taicpu(p).oper[1]^.ref^.base, hp1) then
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+ Break;
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+
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+ hp1_last := hp1;
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+ end;
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+ end;
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+ end;
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+
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+
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function TCpuAsmOptimizer.OptPostCMP(var p : tai): boolean;
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var
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hp1,hp2: tai;
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@@ -626,6 +787,24 @@ Implementation
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end;
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+ function TCpuAsmOptimizer.PeepHoleOptPass2Cpu(var p: tai): boolean;
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+ var
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+ hp1: tai;
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+ begin
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+ result := false;
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+ if p.typ=ait_instruction then
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+ begin
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+ case taicpu(p).opcode of
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+ A_LDR,
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+ A_STR:
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+ Result:=OptPass2LDRSTR(p);
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+ else
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+ ;
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+ end;
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+ end;
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+ end;
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+
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+
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function TCpuAsmOptimizer.PostPeepHoleOptsCpu(var p: tai): boolean;
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begin
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result := false;
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nickysn