Fix for Mantis #22326

This fixes 64bit shifts on arm with a constant shift value of 0.

The old code would have emitted something like this
mov r0, r0, lsl #32
as 32 is an invalid shift value (and would be wrong anyway) the
assembler declined to assemble the produced source.

The new code will just not emit any code for a shift value of 0.

tests/test/tint642.pp now tests shl/shr 0 on 64 bit values.
tests/webtbs/tw22326.pp is also added as an additional test.

git-svn-id: trunk@21746 -

.gitattributes

@@ -12665,6 +12665,7 @@ tests/webtbs/tw2220.pp svneol=native#text/plain
 tests/webtbs/tw2226.pp svneol=native#text/plain
 tests/webtbs/tw2229.pp svneol=native#text/plain
 tests/webtbs/tw22320.pp svneol=native#text/plain
+tests/webtbs/tw22326.pp svneol=native#text/plain
 tests/webtbs/tw2233.pp svneol=native#text/plain
 tests/webtbs/tw22331.pp svneol=native#text/plain
 tests/webtbs/tw2242.pp svneol=native#text/plain

compiler/arm/narmmat.pas

@@ -463,17 +463,17 @@ implementation
                 location.register64.reglo:=hreg64hi;
               end
             {Shift LESS than 32}
-            else if v < 32 then
+            else if (v < 32) and (v > 1) then
               if nodetype=shln then
                 shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
               else
                 shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
             {More than 32}
-            else
+            else if v > 32 then
               if nodetype=shln then
                 shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
               else
-                shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR)
+                shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR);
           end
         else
           begin

tests/test/tint642.pp

@@ -248,6 +248,8 @@ procedure testshlshrqword;
 
      l1:=16;
      l2:=0;
+     if (q1 shl 0)<>q1 then
+       do_error(1499);
      if (q1 shl 16)<>q3 then
        do_error(1500);
      if (q1 shl 48)<>q0 then
@@ -277,6 +279,8 @@ procedure testshlshrqword;
      if ((q1+q0) shl (l1+l2))<>q3 then
        do_error(1509);
 
+     if (q1 shr 0)<>q1 then
+       do_error(15091);
      if (q1 shr 16)<>q2 then
        do_error(1510);
      if (q1 shr 48)<>q0 then

tests/webtbs/tw22326.pp

@@ -0,0 +1,9 @@
+var
+  q1: QWord;
+begin
+  q1:=$1020304050607080;
+  if (q1 shl 0) <> q1 then
+    halt(1);
+  if (q1 shr 0) <> q1 then
+    halt(2);
+end.