* fix rol/ror instruction usage and spilling on RiscV

compiler/nadd.pas

@@ -1855,6 +1855,9 @@ const
 {$ifdef m68k}
                and (CPUM68K_HAS_ROLROR in cpu_capabilities[current_settings.cputype])
 {$endif m68k}
+{$ifdef riscv}
+               and ([CPURV_HAS_ZBB,CPURV_HAS_ZBKB]*cpu_capabilities[init_settings.cputype]<>[])
+{$endif riscv}
 {$ifndef cpu64bitalu}
                and (ld.typ=orddef) and
                not(torddef(ld).ordtype in [s64bit,u64bit,scurrency])

compiler/riscv/aasmcpu.pas

@@ -521,6 +521,8 @@ uses cutils, cclasses;
           A_ADD,A_SUB,A_SLL,A_SLT,A_SLTU,
           A_XOR,A_OR,A_AND,A_SRL,A_SRA,
 
+          A_ROR,A_ROL,A_RORI,
+
           A_MUL,A_MULH,A_MULHSU,A_MULHU,
           A_DIV,A_DIVU,A_REM,A_REMU,
 
@@ -563,6 +565,8 @@ uses cutils, cclasses;
           A_MULW,
           A_DIVW,A_DIVUW,A_REMW,A_REMUW,
 
+          A_RORIW,A_RORW,A_ROLW,
+
           A_FCVT_L_S,A_FCVT_LU_S,
           A_FCVT_S_L,A_FCVT_S_LU,