- non used constants OT_* removed

* some keywords moved lower case

compiler/sparc/cpubase.pas

@@ -33,105 +33,11 @@ const
   OS_FLOAT=OS_F64;
   {the size of a vector register for a processor}
   OS_VECTOR=OS_M64;
-  {Operand types}
-  OT_NONE      = $00000000;
-  OT_BITS8     = $00000001;  { size, and other attributes, of the operand  }
-  OT_BITS16    = $00000002;
-  OT_BITS32    = $00000004;
-  OT_BITS64    = $00000008;  { FPU only  }
-  OT_BITS80    = $00000010;
-  OT_FAR       = $00000020;  { this means 16:16 or 16:32, like in CALL/JMP }
-  OT_NEAR      = $00000040;
-  OT_SHORT     = $00000080;
-  OT_SIZE_MASK = $000000FF;  { all the size attributes  }
-  OT_NON_SIZE  = LongInt(not OT_SIZE_MASK);
-  OT_SIGNED    = $00000100;  { the operand need to be signed -128-127 }
-  OT_TO        = $00000200;  { operand is followed by a colon  }
-                             { reverse effect in FADD, FSUB &c  }
-  OT_COLON     = $00000400;
-  OT_REGISTER  = $00001000;
-  OT_IMMEDIATE = $00002000;
-  OT_IMM8      = $00002001;
-  OT_IMM16     = $00002002;
-  OT_IMM32     = $00002004;
-  OT_IMM64     = $00002008;
-  OT_IMM80     = $00002010;
-  OT_REGMEM    = $00200000;  { for r/m, ie EA, operands  }
-  OT_REGNORM   = $00201000;  { 'normal' reg, qualifies as EA  }
-  OT_REG8      = $00201001;
-  OT_REG16     = $00201002;
-  OT_REG32     = $00201004;
-  OT_MMXREG    = $00201008;  { MMX registers  }
-  OT_XMMREG    = $00201010;  { Katmai registers  }
-  OT_MEMORY    = $00204000;  { register number in 'basereg'  }
-  OT_MEM8      = $00204001;
-  OT_MEM16     = $00204002;
-  OT_MEM32     = $00204004;
-  OT_MEM64     = $00204008;
-  OT_MEM80     = $00204010;
-  OT_FPUREG    = $01000000;  { floating point stack registers  }
-  OT_FPU0      = $01000800;  { FPU stack register zero  }
-  OT_REG_SMASK = $00070000;  { special register operands: these may be treated differently  }
-                             { a mask for the following  }
-  OT_REG_ACCUM = $00211000;  { accumulator: AL, AX or EAX  }
-  OT_REG_AL    = $00211001;    { REG_ACCUM | BITSxx  }
-  OT_REG_AX    = $00211002;    { ditto  }
-  OT_REG_EAX   = $00211004;    { and again  }
-  OT_REG_COUNT = $00221000;  { counter: CL, CX or ECX  }
-  OT_REG_CL    = $00221001;    { REG_COUNT | BITSxx  }
-  OT_REG_CX    = $00221002;    { ditto  }
-  OT_REG_ECX   = $00221004;    { another one  }
-  OT_REG_DX    = $00241002;
-
-  OT_REG_SREG  = $00081002;  { any segment register  }
-  OT_REG_CS    = $01081002;  { CS  }
-  OT_REG_DESS  = $02081002;  { DS, ES, SS (non-CS 86 registers)  }
-  OT_REG_FSGS  = $04081002;  { FS, GS (386 extENDed registers)  }
-
-  OT_REG_CDT   = $00101004;  { CRn, DRn and TRn  }
-  OT_REG_CREG  = $08101004;  { CRn  }
-  OT_REG_CR4   = $08101404;  { CR4 (Pentium only)  }
-  OT_REG_DREG  = $10101004;  { DRn  }
-  OT_REG_TREG  = $20101004;  { TRn  }
-
-  OT_MEM_OFFS  = $00604000;  { special type of EA  }
-                             { simple [address] offset  }
-  OT_ONENESS   = $00800000;  { special type of immediate operand  }
-                             { so UNITY == IMMEDIATE | ONENESS  }
-  OT_UNITY     = $00802000;  { for shift/rotate instructions  }
-
-{Instruction flags }
-  IF_NONE   = $00000000;
-  IF_SM     = $00000001;        { size match first two operands  }
-  IF_SM2    = $00000002;
-  IF_SB     = $00000004;  { unsized operands can't be non-byte  }
-  IF_SW     = $00000008;  { unsized operands can't be non-word  }
-  IF_SD     = $00000010;  { unsized operands can't be nondword  }
-  IF_AR0    = $00000020;  { SB, SW, SD applies to argument 0  }
-  IF_AR1    = $00000040;  { SB, SW, SD applies to argument 1  }
-  IF_AR2    = $00000060;  { SB, SW, SD applies to argument 2  }
-  IF_ARMASK = $00000060;  { mask for unsized argument spec  }
-  IF_PRIV   = $00000100;  { it's a privileged instruction  }
-  IF_SMM    = $00000200;  { it's only valid in SMM  }
-  IF_PROT   = $00000400;  { it's protected mode only  }
-  IF_UNDOC  = $00001000;  { it's an undocumented instruction  }
-  IF_FPU    = $00002000;  { it's an FPU instruction  }
-  IF_MMX    = $00004000;  { it's an MMX instruction  }
-  IF_3DNOW  = $00008000;  { it's a 3DNow! instruction  }
-  IF_SSE    = $00010000;  { it's a SSE (KNI, MMX2) instruction  }
-  IF_PMASK  = LongInt($FF000000);  { the mask for processor types  }
-  IF_PFMASK = LongInt($F001FF00);  { the mask for disassembly "prefer"  }
-  IF_V7     = $00000000;  { SPARC V7 instruction only (not supported)}
-  IF_V8     = $01000000;  { SPARC V8 instruction (the default)}
-  IF_V9     = $02000000;  { SPARC V9 instruction (not yet supported)}
-  { added flags }
-  IF_PRE    = $40000000;  { it's a prefix instruction }
-  IF_PASS2  = LongInt($80000000);{instruction can change in a second pass?}
-TYPE
+type
 {$WARNING CPU32 opcodes do not fully include the Ultra SPRAC instruction set.}
   { don't change the order of these opcodes! }
   TAsmOp=({$INCLUDE opcode.inc});
-  op2strtable=ARRAY[TAsmOp]OF STRING[11];
+  op2strtable=array[TAsmOp]OF STRING[11];
 CONST
   FirstOp=Low(TAsmOp);
   LastOp=High(TAsmOp);
@@ -139,7 +45,7 @@ CONST
 {*****************************************************************************
                                 Operand Sizes
 *****************************************************************************}
-TYPE
+type
   TOpSize=(S_NO,
            S_B,{Byte}
            S_H,{Half word}
@@ -163,31 +69,31 @@ TYPE
 {*****************************************************************************}
 {                               Conditions                                    }
 {*****************************************************************************}
-TYPE
+type
   TAsmCond=(C_None,
     C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
     C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,
     C_NS,C_NZ,C_O,C_P,C_PE,C_PO,C_S,C_Z
   );
 CONST
-  cond2str:ARRAY[TAsmCond] of string[3]=('',
+  cond2str:array[TAsmCond] of string[3]=('',
     'a','ae','b','be','c','e','g','ge','l','le','na','nae',
     'nb','nbe','nc','ne','ng','nge','nl','nle','no','np',
     'ns','nz','o','p','pe','po','s','z'
   );
-  inverse_cond:ARRAY[TAsmCond] of TAsmCond=(C_None,
+  inverse_cond:array[TAsmCond] of TAsmCond=(C_None,
     C_NA,C_NAE,C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_A,C_AE,
     C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_O,C_P,
     C_S,C_Z,C_NO,C_NP,C_NP,C_P,C_NS,C_NZ
   );
 CONST
   CondAsmOps=3;
-  CondAsmOp:ARRAY[0..CondAsmOps-1] of TAsmOp=(A_FCMPd, A_JMPL, A_FCMPs);
-  CondAsmOpStr:ARRAY[0..CondAsmOps-1] of string[7]=('FCMPd','JMPL','FCMPs');
+  CondAsmOp:array[0..CondAsmOps-1] of TAsmOp=(A_FCMPd, A_JMPL, A_FCMPs);
+  CondAsmOpStr:array[0..CondAsmOps-1] of string[7]=('FCMPd','JMPL','FCMPs');
 {*****************************************************************************}
 {                                 Registers                                   }
 {*****************************************************************************}
-TYPE
+type
   { enumeration for registers, don't change the order }
   { it's used by the register size conversions        }
   TCpuRegister=({$INCLUDE cpuregs.inc});
@@ -395,7 +301,7 @@ const
   R_SUBL=$00;
 
 type
-  reg2strtable=ARRAY[TCpuRegister] OF STRING[7];
+  reg2strtable=array[TCpuRegister] OF STRING[7];
   TCpuReg=array[TCpuRegister]of TRegister;
 const
   std_reg2str:reg2strtable=({$INCLUDE strregs.inc});
@@ -403,7 +309,7 @@ const
 {*****************************************************************************
                                    Flags
 *****************************************************************************}
-TYPE
+type
   TResFlags=(
     F_E,  {Equal}
     F_NE, {Not Equal}
@@ -421,7 +327,7 @@ TYPE
 {*****************************************************************************
                                 Reference
 *****************************************************************************}
-TYPE
+type
   trefoptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
 
   { immediate/reference record }
@@ -463,7 +369,7 @@ TYPE
 {*****************************************************************************
                              Argument Classification
 *****************************************************************************}
-TYPE
+type
   TArgClass = (
      { the following classes should be defined by all processor implemnations }
      AC_NOCLASS,
@@ -478,7 +384,7 @@ TYPE
 {*****************************************************************************
                                Generic Location
 *****************************************************************************}
-TYPE
+type
 {tparamlocation describes where a parameter for a procedure is stored.
 References are given from the caller's point of view. The usual TLocation isn't
 used, because contains a lot of unnessary fields.}
@@ -579,7 +485,7 @@ const
   {# Register indexes for stabs information, when some parameters or variables
   are stored in registers.
   Taken from rs6000.h (DBX_REGISTER_NUMBER) from GCC 3.x source code.}
-  stab_regindex:ARRAY[TCpuRegister]OF ShortInt=({$INCLUDE stabregi.inc});
+  stab_regindex:array[TCpuRegister]OF ShortInt=({$INCLUDE stabregi.inc});
 {*************************** generic register names **************************}
   stack_pointer_reg   = R_O6;
   NR_STACK_POINTER_REG = NR_O6;
@@ -633,7 +539,7 @@ PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.}
 {# Registers which are defined as scratch and no need to save across routine
 calls or in assembler blocks.}
   ScratchRegsCount=8;
-  scratch_regs:ARRAY[1..ScratchRegsCount] OF Tsuperregister=(RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7);
+  scratch_regs:array[1..ScratchRegsCount] OF Tsuperregister=(RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7);
 { low and high of the available maximum width integer general purpose }
 { registers                                                           }
   LoGPReg = R_G0;
@@ -658,17 +564,17 @@ calls or in assembler blocks.}
 *****************************************************************************}
 
 {$ifndef NOAG386BIN}
-TYPE
+type
   tinsentry=packed record
     opcode  : tasmop;
     ops     : byte;
-    optypes : ARRAY[0..2] of LongInt;
-    code    : ARRAY[0..maxinfolen] of char;
+    optypes : array[0..2] of LongInt;
+    code    : array[0..maxinfolen] of char;
     flags   : LongInt;
   END;
   pinsentry=^tinsentry;
 
-  TInsTabCache=ARRAY[TasmOp] of LongInt;
+  TInsTabCache=array[TasmOp] of LongInt;
   PInsTabCache=^TInsTabCache;
 VAR
   InsTabCache : PInsTabCache;
@@ -678,7 +584,7 @@ VAR
 *****************************************************************************}
 const
   maxvarregs=30;
-  VarRegs:ARRAY[1..maxvarregs]OF TCpuRegister=(
+  VarRegs:array[1..maxvarregs]OF TCpuRegister=(
              R_G0,R_G1,R_G2,R_G3,R_G4,R_G5,R_G6,R_G7,
              R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,{R_R14=R_SP}R_O7,
              R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
@@ -691,15 +597,13 @@ const
   max_scratch_regs=8;
 
 
-FUNCTION is_calljmp(o:tasmop):boolean;
-FUNCTION flags_to_cond(CONST f:TResFlags):TAsmCond;
+function is_calljmp(o:tasmop):boolean;
+function flags_to_cond(CONST f:TResFlags):TAsmCond;
 procedure convert_register_to_enum(var r:Tregister);
 function cgsize2subreg(s:Tcgsize):Tsubregister;
-
-IMPLEMENTATION
-
-uses  verbose;
-
+implementation
+uses
+  verbose;
 const
   CallJmpOp=[A_JMPL..A_CBccc];
 function is_calljmp(o:tasmop):boolean;
@@ -712,12 +616,11 @@ function is_calljmp(o:tasmop):boolean;
   end;
 function flags_to_cond(const f:TResFlags):TAsmCond;
   CONST
-    flags_2_cond:ARRAY[TResFlags]OF TAsmCond=
+    flags_2_cond:array[TResFlags]OF TAsmCond=
     (C_E,C_NE,C_G,C_L,C_GE,C_LE,C_C,C_NC,C_A,C_AE,C_B,C_BE);
   BEGIN
     result:=flags_2_cond[f];
   END;
-
 procedure convert_register_to_enum(var r:Tregister);
 begin
   if r.enum=R_INTREGISTER
@@ -760,20 +663,18 @@ begin
         internalerror(200301082);
     end;
 end;
-
 function cgsize2subreg(s:Tcgsize):Tsubregister;
-
 begin
   cgsize2subreg:=R_SUBWHOLE;
 end;
-
-END.
-
-
-
+end.
 {
   $Log$
-  Revision 1.29  2003-04-29 12:03:52  mazen
+  Revision 1.30  2003-05-06 14:58:46  mazen
+  - non used constants OT_* removed
+  * some keywords moved lower case
+
+  Revision 1.29  2003/04/29 12:03:52  mazen
   * TOldRegister isnow just an alias for TCpuRegister
   * TCpuRegister is used to define cpu register set physically available
   + CpuRegs array to easially create correspondence between TCpuRegister and TRegister