* Synchronize with trunk

git-svn-id: branches/unicodekvm@40331 -

compiler/arm/aasmcpu.pas

@@ -1150,8 +1150,9 @@ implementation
                                           while assigned(hp2) do
                                             begin
                                               if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
-                                                and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
-                                              then
+                                                and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label) and
+                                                { gottpoff symbols are PC relative, so we cannot reuse them }
+                                                (tai_const(hp2).consttype<>aitconst_gottpoff) then
                                                 begin
                                                   with taicpu(curtai).oper[curop]^.ref^ do
                                                     begin

compiler/arm/aoptcpu.pas

@@ -83,6 +83,10 @@ Implementation
     cgobj,procinfo,
     aasmbase,aasmdata;
 
+{ Range check must be disabled explicitly as conversions between signed and unsigned
+  32-bit values are done without explicit typecasts }
+{$R-}
+
   function CanBeCond(p : tai) : boolean;
     begin
       result:=

compiler/llvm/nllvmmem.pas

@@ -48,7 +48,7 @@ interface
         procedure pass_generate_code; override;
         procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
         procedure update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
-        procedure update_reference_offset(var ref: treference; index, mulsize: aint); override;
+        procedure update_reference_offset(var ref: treference; index, mulsize: ASizeInt); override;
       end;
 
 
@@ -294,7 +294,7 @@ implementation
     end;
 
 
-  procedure tllvmvecnode.update_reference_offset(var ref: treference; index, mulsize: aint);
+  procedure tllvmvecnode.update_reference_offset(var ref: treference; index, mulsize: ASizeInt);
     begin
       if not is_packed_array(left.resultdef) or
          not (tarraydef(left.resultdef).elementdef.typ in [enumdef,orddef]) then

compiler/m68k/aoptcpu.pas

@@ -49,6 +49,9 @@ unit aoptcpu;
     uses
       cutils, aasmcpu, cgutils, globals, verbose, cpuinfo, itcpugas;
 
+{ Range check must be disabled explicitly as conversions between signed and unsigned
+  32-bit values are done without explicit typecasts }
+{$R-}
 
     function opname(var p: tai): string;
       begin
@@ -163,8 +166,10 @@ unit aoptcpu;
                     if MatchOperand(taicpu(p).oper[0]^,taicpu(p).oper[1]^) then
                       begin
                         DebugMsg('Optimizer: '+opstr+' + '+opstr+' removed',p);
+			GetNextInstruction(p,next);
                         asml.remove(p);
                         p.free;
+			p:=next;
                       end
                     else
                       DebugMsg('Optimizer: '+opstr+' + '+opstr+' to '+opstr+' #1',p)
@@ -266,8 +271,10 @@ unit aoptcpu;
                    (taicpu(p).oper[0]^.ref^.offset = 0) then
                   begin
                     DebugMsg('Optimizer: LEA 0(Ax),Ax removed',p);
+		    GetNextInstruction(p,next);
                     asml.remove(p);
                     p.free;
+		    p:=next;
                     result:=true;
                   end;
               { Address register sub/add can be replaced with ADDQ/SUBQ or LEA if the value is in the

compiler/m68k/cgcpu.pas

@@ -138,6 +138,9 @@ unit cgcpu;
        symsym,symtable,defutil,paramgr,procinfo,
        rgobj,tgobj,rgcpu,fmodule;
 
+{ Range check must be disabled explicitly as conversions between signed and unsigned
+  32-bit values are done without explicit typecasts }
+{$R-}
 
     const
       { opcode table lookup }

compiler/ncgmem.pas

@@ -862,7 +862,7 @@ implementation
 
       var
          offsetdec,
-         extraoffset : aint;
+         extraoffset : ASizeInt;
          rightp      : pnode;
          newsize  : tcgsize;
          mulsize,

compiler/riscv/nrvadd.pas

@@ -63,6 +63,13 @@ implementation
       ncon,nset,
       ncgutil,tgobj,rgobj,rgcpu,cgobj,hlcgobj;
 
+{$undef AVOID_OVERFLOW}
+{$ifopt Q+}
+  {$define AVOID_OVERFLOW}
+  const
+     low_value = {$ifdef CPUALU64} low(int64) {$else} low(longint) {$endif};
+{$endif}
+
     procedure trvaddnode.Cmp(signed: boolean);
       var
         flabel,tlabel: tasmlabel;
@@ -88,7 +95,10 @@ implementation
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
 
               if (right.location.loc=LOC_CONSTANT) and
-                 (not is_imm12(-right.location.value)) then
+                 { right.location.value might be $8000000000000000, 
+                   and its minus value generates an overflow here }
+                 {$ifdef AVOID_OVERFLOW} ((right.location.value = low_value) or {$endif}
+                 (not is_imm12(-right.location.value)) {$ifdef AVOID_OVERFLOW}){$endif} then
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
 
               if right.location.loc=LOC_CONSTANT then
@@ -103,7 +113,10 @@ implementation
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
 
               if (right.location.loc=LOC_CONSTANT) and
-                 (not is_imm12(-right.location.value)) then
+                 { right.location.value might be $8000000000000000, 
+                   and its minus value generates an overflow here }
+                 {$ifdef AVOID_OVERFLOW} ((right.location.value = low_value) or {$endif}
+                 (not is_imm12(-right.location.value)) {$ifdef AVOID_OVERFLOW}){$endif} then
                 hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,false);
 
               if right.location.loc=LOC_CONSTANT then

compiler/riscv32/cgcpu.pas

@@ -69,6 +69,9 @@ unit cgcpu;
        symconst,symsym,fmodule,
        rgobj,tgobj,cpupi,procinfo,paramgr;
 
+{ Range check must be disabled explicitly as conversions between signed and unsigned
+  32-bit values are done without explicit typecasts }
+{$R-}
 
     procedure tcgrv32.init_register_allocators;
       begin

compiler/riscv64/cgcpu.pas

@@ -63,6 +63,9 @@ implementation
       symconst, fmodule, symtable,
       rgobj, tgobj, cpupi, procinfo, paramgr, cpupara;
 
+{ Range check must be disabled explicitly as conversions between signed and unsigned
+  64-bit and 32-bit values are done without explicit typecasts }
+{$R-}
 
     procedure tcgrv64.init_register_allocators;
       begin

compiler/x86/cgx86.pas

@@ -2773,7 +2773,7 @@ unit cgx86;
 
     type  copymode=(copy_move,copy_mmx,copy_string,copy_mm,copy_avx);
 
-    var srcref,dstref:Treference;
+    var srcref,dstref,tmpref:Treference;
         r,r0,r1,r2,r3:Tregister;
         helpsize:tcgint;
         copysize:byte;
@@ -3049,8 +3049,10 @@ unit cgx86;
               end
             else
               begin
-                dstref.segment:=NR_NO;
-                a_loadaddr_ref_reg(list,dstref,REGDI);
+                { load offset of dest. reference }
+                tmpref:=dstref;
+                tmpref.segment:=NR_NO;
+                a_loadaddr_ref_reg(list,tmpref,REGDI);
 {$ifdef volatile_es}
                 saved_es:=false;
 {$else volatile_es}
@@ -3086,8 +3088,10 @@ unit cgx86;
               end
             else
               begin
-                srcref.segment:=NR_NO;
-                a_loadaddr_ref_reg(list,srcref,REGSI);
+                { load offset of source reference }
+                tmpref:=srcref;
+                tmpref.segment:=NR_NO;
+                a_loadaddr_ref_reg(list,tmpref,REGSI);
                 list.concat(taicpu.op_reg(A_PUSH,push_segment_size,NR_DS));
                 saved_ds:=true;
                 if srcref.segment<>NR_NO then