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@@ -134,7 +134,6 @@ unit aoptx86;
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function OptPass1LEA(var p : tai) : boolean;
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function OptPass1Sub(var p : tai) : boolean;
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function OptPass1SHLSAL(var p : tai) : boolean;
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- function OptPass1SETcc(var p : tai) : boolean;
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function OptPass1FSTP(var p : tai) : boolean;
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function OptPass1FLD(var p : tai) : boolean;
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function OptPass1Cmp(var p : tai) : boolean;
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@@ -150,6 +149,9 @@ unit aoptx86;
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function OptPass2Lea(var p: tai): Boolean;
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function OptPass2SUB(var p: tai): Boolean;
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function OptPass2ADD(var p : tai): Boolean;
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+ function OptPass2SETcc(var p : tai) : boolean;
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+
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+ function CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
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function PostPeepholeOptMov(var p : tai) : Boolean;
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function PostPeepholeOptMovzx(var p : tai) : Boolean;
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@@ -215,6 +217,7 @@ unit aoptx86;
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const
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SPeepholeOptimization = '';
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{$endif DEBUG_AOPTCPU}
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+ LIST_STEP_SIZE = 4;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const opsize: topsizes): boolean;
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begin
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@@ -4153,97 +4156,120 @@ unit aoptx86;
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end;
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- function TX86AsmOptimizer.OptPass1SETcc(var p: tai): boolean;
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+ function TX86AsmOptimizer.CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
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var
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- hp1,hp2,next: tai; SetC, JumpC: TAsmCond; Unconditional: Boolean;
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+ CurrentRef: TReference;
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+ FullReg: TRegister;
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+ hp1, hp2: tai;
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begin
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- Result:=false;
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+ Result := False;
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+ if (first_mov.opsize <> S_B) or (second_mov.opsize <> S_B) then
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+ Exit;
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- if MatchOpType(taicpu(p),top_reg) and GetNextInstruction(p, hp1) then
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- begin
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- if ((MatchInstruction(hp1, A_TEST, [S_B]) and
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- MatchOpType(taicpu(hp1),top_reg,top_reg) and
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- (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg)) or
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- (MatchInstruction(hp1, A_CMP, [S_B]) and
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- MatchOpType(taicpu(hp1),top_const,top_reg) and
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- (taicpu(hp1).oper[0]^.val=0))
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- ) and
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- (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
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- GetNextInstruction(hp1, hp2) and
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- MatchInstruction(hp2, A_Jcc, []) then
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- { Change from: To:
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+ { We assume you've checked if the operand is actually a reference by
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+ this point. If it isn't, you'll most likely get an access violation }
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+ CurrentRef := first_mov.oper[1]^.ref^;
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- set(C) %reg j(~C) label
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- test %reg,%reg/cmp $0,%reg
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- je label
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+ { Memory must be aligned }
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+ if (CurrentRef.offset mod 4) <> 0 then
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+ Exit;
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+ Inc(CurrentRef.offset);
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+ CurrentRef.alignment := 1; { Otherwise references_equal will return False }
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- set(C) %reg j(C) label
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- test %reg,%reg/cmp $0,%reg
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- jne label
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- }
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+ if MatchOperand(second_mov.oper[0]^, 0) and
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+ references_equal(second_mov.oper[1]^.ref^, CurrentRef) and
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+ GetNextInstruction(second_mov, hp1) and
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+ (hp1.typ = ait_instruction) and
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+ (taicpu(hp1).opcode = A_MOV) and
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+ MatchOpType(taicpu(hp1), top_const, top_ref) and
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+ (taicpu(hp1).oper[0]^.val = 0) then
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+ begin
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+ Inc(CurrentRef.offset);
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+ CurrentRef.alignment := taicpu(hp1).oper[1]^.ref^.alignment; { Otherwise references_equal might return False }
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+
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+ FullReg := newreg(R_INTREGISTER,getsupreg(first_mov.oper[0]^.reg), R_SUBD);
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+
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+ if references_equal(taicpu(hp1).oper[1]^.ref^, CurrentRef) then
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begin
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- next := tai(p.Next);
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+ case taicpu(hp1).opsize of
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+ S_B:
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+ if GetNextInstruction(hp1, hp2) and
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+ MatchInstruction(taicpu(hp2), A_MOV, [S_B]) and
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+ MatchOpType(taicpu(hp2), top_const, top_ref) and
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+ (taicpu(hp2).oper[0]^.val = 0) then
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+ begin
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+ Inc(CurrentRef.offset);
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+ CurrentRef.alignment := 1; { Otherwise references_equal will return False }
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- TransferUsedRegs(TmpUsedRegs);
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- UpdateUsedRegs(TmpUsedRegs, next);
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- UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
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+ if references_equal(taicpu(hp2).oper[1]^.ref^, CurrentRef) and
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+ (taicpu(hp2).opsize = S_B) then
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+ begin
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+ RemoveInstruction(hp1);
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+ RemoveInstruction(hp2);
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- JumpC := taicpu(hp2).condition;
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- Unconditional := False;
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+ first_mov.opsize := S_L;
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- if conditions_equal(JumpC, C_E) then
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- SetC := inverse_cond(taicpu(p).condition)
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- else if conditions_equal(JumpC, C_NE) then
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- SetC := taicpu(p).condition
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- else
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- { We've got something weird here (and inefficent) }
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- begin
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- DebugMsg('DEBUG: Inefficient jump - check code generation', p);
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- SetC := C_NONE;
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+ if first_mov.oper[0]^.typ = top_reg then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVb/MOVb -> MOVZX/MOVl', first_mov);
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- { JAE/JNB will always branch (use 'condition_in', since C_AE <> C_NB normally) }
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- if condition_in(C_AE, JumpC) then
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- Unconditional := True
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- else
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- { Not sure what to do with this jump - drop out }
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- Exit;
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- end;
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+ { Reuse second_mov as a MOVZX instruction }
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+ second_mov.opcode := A_MOVZX;
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+ second_mov.opsize := S_BL;
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+ second_mov.loadreg(0, first_mov.oper[0]^.reg);
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+ second_mov.loadreg(1, FullReg);
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- RemoveInstruction(hp1);
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+ first_mov.oper[0]^.reg := FullReg;
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- if Unconditional then
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- MakeUnconditional(taicpu(hp2))
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- else
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- begin
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- if SetC = C_NONE then
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- InternalError(2018061402);
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+ asml.Remove(second_mov);
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+ asml.InsertBefore(second_mov, first_mov);
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+ end
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+ else
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+ { It's a value }
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVb/MOVb -> MOVl', first_mov);
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+ RemoveInstruction(second_mov);
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+ end;
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- taicpu(hp2).SetCondition(SetC);
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- end;
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+ Result := True;
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+ Exit;
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+ end;
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+ end;
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+ S_W:
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+ begin
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+ RemoveInstruction(hp1);
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- if not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs) then
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- begin
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- RemoveCurrentp(p, hp2);
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- Result := True;
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- end;
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+ first_mov.opsize := S_L;
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- DebugMsg(SPeepholeOptimization + 'SETcc/TESTCmp/Jcc -> Jcc',p);
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- end
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- else if MatchInstruction(hp1, A_MOV, [S_B]) and
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- MatchOpType(taicpu(hp1),top_reg,top_reg) and
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- MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[0]^) then
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- begin
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- TransferUsedRegs(TmpUsedRegs);
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- UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
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- if not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp1, TmpUsedRegs) then
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- begin
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- AllocRegBetween(taicpu(p).oper[0]^.reg,p,hp1,UsedRegs);
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- taicpu(p).oper[0]^.reg:=taicpu(hp1).oper[1]^.reg;
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- RemoveInstruction(hp1);
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- DebugMsg(SPeepholeOptimization + 'SETcc/Mov -> SETcc',p);
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- Result := true;
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- end;
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+ if first_mov.oper[0]^.typ = top_reg then
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVw -> MOVZX/MOVl', first_mov);
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+
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+ { Reuse second_mov as a MOVZX instruction }
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+ second_mov.opcode := A_MOVZX;
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+ second_mov.opsize := S_BL;
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+ second_mov.loadreg(0, first_mov.oper[0]^.reg);
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+ second_mov.loadreg(1, FullReg);
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+
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+ first_mov.oper[0]^.reg := FullReg;
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+
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+ asml.Remove(second_mov);
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+ asml.InsertBefore(second_mov, first_mov);
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+ end
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+ else
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+ { It's a value }
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+ begin
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+ DebugMsg(SPeepholeOptimization + 'MOVb/MOVb/MOVw -> MOVl', first_mov);
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+ RemoveInstruction(second_mov);
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+ end;
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+
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+ Result := True;
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+ Exit;
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+ end;
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+ else
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+ ;
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+ end;
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end;
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end;
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end;
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@@ -5265,8 +5291,6 @@ unit aoptx86;
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function TX86AsmOptimizer.OptPass2Movx(var p : tai) : boolean;
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- const
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- LIST_STEP_SIZE = 4;
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var
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ThisReg: TRegister;
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MinSize, MaxSize, TrySmaller, TargetSize: TOpSize;
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@@ -5973,6 +5997,359 @@ unit aoptx86;
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end;
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+ function TX86AsmOptimizer.OptPass2SETcc(var p: tai): boolean;
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+ var
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+ hp1,hp2,next: tai; SetC, JumpC: TAsmCond;
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+ Unconditional, PotentialModified: Boolean;
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+ OperPtr: POper;
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+
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+ NewRef: TReference;
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+
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+ InstrList: array of taicpu;
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+ InstrMax, Index: Integer;
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+ const
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+{$ifdef DEBUG_AOPTCPU}
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+ SNoFlags: shortstring = ' so the flags aren''t modified';
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+{$else DEBUG_AOPTCPU}
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+ SNoFlags = '';
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+{$endif DEBUG_AOPTCPU}
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+ begin
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+ Result:=false;
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+
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+ if MatchOpType(taicpu(p),top_reg) and GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) then
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+ begin
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+ if MatchInstruction(hp1, A_TEST, [S_B]) and
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+ MatchOpType(taicpu(hp1),top_reg,top_reg) and
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+ (taicpu(hp1).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
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+ (taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
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+ GetNextInstruction(hp1, hp2) and
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+ MatchInstruction(hp2, A_Jcc, []) then
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+ { Change from: To:
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+
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+ set(C) %reg j(~C) label
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+ test %reg,%reg/cmp $0,%reg
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+ je label
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+
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+
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+ set(C) %reg j(C) label
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+ test %reg,%reg/cmp $0,%reg
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+ jne label
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+ }
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+ begin
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+ { Before we do anything else, we need to check the instructions
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+ in between SETcc and TEST to make sure they don't modify the
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+ FLAGS register - if -O2 or under, there won't be any
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+ instructions between SET and TEST }
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+
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+ TransferUsedRegs(TmpUsedRegs);
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+ UpdateUsedRegs(TmpUsedRegs, tai(p.next));
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+
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+ if (cs_opt_level3 in current_settings.optimizerswitches) then
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+ begin
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+ next := p;
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+ SetLength(InstrList, 0);
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+ InstrMax := -1;
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+ PotentialModified := False;
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+
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+ { Make a note of every instruction that modifies the FLAGS
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+ register }
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+ while GetNextInstruction(next, next) and (next <> hp1) do
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+ begin
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+ if next.typ <> ait_instruction then
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+ { GetNextInstructionUsingReg should have returned False }
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+ InternalError(2021051701);
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+
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+ if RegModifiedByInstruction(NR_DEFAULTFLAGS, next) then
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+ begin
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+ case taicpu(next).opcode of
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+ A_SETcc,
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+ A_CMOVcc,
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+ A_Jcc:
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+ begin
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+ if PotentialModified then
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+ { Not safe because the flags were modified earlier }
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+ Exit
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+ else
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+ { Condition is the same as the initial SETcc, so this is safe
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+ (don't add to instruction list though) }
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+ Continue;
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+ end;
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+ A_ADD:
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+ begin
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+ if (taicpu(next).opsize = S_B) or
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+ { LEA doesn't support 8-bit operands }
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+ (taicpu(next).oper[1]^.typ <> top_reg) or
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+ { Must write to a register }
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+ (taicpu(next).oper[0]^.typ = top_ref) then
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+ { Require a constant or a register }
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+ Exit;
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+
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+ PotentialModified := True;
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+ end;
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+ A_SUB:
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+ begin
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+ if (taicpu(next).opsize = S_B) or
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+ { LEA doesn't support 8-bit operands }
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+ (taicpu(next).oper[1]^.typ <> top_reg) or
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+ { Must write to a register }
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+ (taicpu(next).oper[0]^.typ <> top_const) or
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+ (taicpu(next).oper[0]^.val = $80000000) then
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+ { Can't subtract a register with LEA - also
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+ check that the value isn't -2^31, as this
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+ can't be negated }
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+ Exit;
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+
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+ PotentialModified := True;
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+ end;
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+ A_SAL,
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+ A_SHL:
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+ begin
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+ if (taicpu(next).opsize = S_B) or
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+ { LEA doesn't support 8-bit operands }
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+ (taicpu(next).oper[1]^.typ <> top_reg) or
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+ { Must write to a register }
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+ (taicpu(next).oper[0]^.typ <> top_const) or
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+ (taicpu(next).oper[0]^.val < 0) or
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+ (taicpu(next).oper[0]^.val > 3) then
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+ Exit;
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+
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+ PotentialModified := True;
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+ end;
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+ A_IMUL:
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+ begin
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+ if (taicpu(next).ops <> 3) or
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+ (taicpu(next).oper[1]^.typ <> top_reg) or
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+ { Must write to a register }
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+ (taicpu(next).oper[2]^.val in [2,3,4,5,8,9]) then
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+ { We can convert "imul x,%reg1,%reg2" (where x = 2, 4 or 8)
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+ to "lea (%reg1,x),%reg2". If x = 3, 5 or 9, we can
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+ change this to "lea (%reg1,%reg1,(x-1)),%reg2" }
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+ Exit
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+ else
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+ PotentialModified := True;
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+ end;
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+ else
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+ { Don't know how to change this, so abort }
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+ Exit;
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+ end;
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+
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+ { Contains highest index (so instruction count - 1) }
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+ Inc(InstrMax);
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+ if InstrMax > High(InstrList) then
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+ SetLength(InstrList, InstrMax + LIST_STEP_SIZE);
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+
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+ InstrList[InstrMax] := taicpu(next);
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+ end;
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+ UpdateUsedRegs(TmpUsedRegs, tai(next.next));
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+ end;
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+
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+ if not Assigned(next) or (next <> hp1) then
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+ { It should be equal to hp1 }
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+ InternalError(2021051702);
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+
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+ { Cycle through each instruction and check to see if we can
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+ change them to versions that don't modify the flags }
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+ if (InstrMax >= 0) then
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+ begin
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+ for Index := 0 to InstrMax do
|
|
|
+ case InstrList[Index].opcode of
|
|
|
+ A_ADD:
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'ADD -> LEA' + SNoFlags, InstrList[Index]);
|
|
|
+ InstrList[Index].opcode := A_LEA;
|
|
|
+ reference_reset(NewRef, 1, []);
|
|
|
+ NewRef.base := InstrList[Index].oper[1]^.reg;
|
|
|
+
|
|
|
+ if InstrList[Index].oper[0]^.typ = top_reg then
|
|
|
+ begin
|
|
|
+ NewRef.index := InstrList[Index].oper[0]^.reg;
|
|
|
+ NewRef.scalefactor := 1;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ NewRef.offset := InstrList[Index].oper[0]^.val;
|
|
|
+
|
|
|
+ InstrList[Index].loadref(0, NewRef);
|
|
|
+ end;
|
|
|
+ A_SUB:
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SUB -> LEA' + SNoFlags, InstrList[Index]);
|
|
|
+ InstrList[Index].opcode := A_LEA;
|
|
|
+ reference_reset(NewRef, 1, []);
|
|
|
+ NewRef.base := InstrList[Index].oper[1]^.reg;
|
|
|
+ NewRef.offset := -InstrList[Index].oper[0]^.val;
|
|
|
+
|
|
|
+ InstrList[Index].loadref(0, NewRef);
|
|
|
+ end;
|
|
|
+ A_SHL,
|
|
|
+ A_SAL:
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SHL -> LEA' + SNoFlags, InstrList[Index]);
|
|
|
+ InstrList[Index].opcode := A_LEA;
|
|
|
+ reference_reset(NewRef, 1, []);
|
|
|
+ NewRef.index := InstrList[Index].oper[1]^.reg;
|
|
|
+ NewRef.scalefactor := 1 shl (InstrList[Index].oper[0]^.val);
|
|
|
+
|
|
|
+ InstrList[Index].loadref(0, NewRef);
|
|
|
+ end;
|
|
|
+ A_IMUL:
|
|
|
+ begin
|
|
|
+ DebugMsg(SPeepholeOptimization + 'IMUL -> LEA' + SNoFlags, InstrList[Index]);
|
|
|
+ InstrList[Index].opcode := A_LEA;
|
|
|
+ reference_reset(NewRef, 1, []);
|
|
|
+ NewRef.index := InstrList[Index].oper[1]^.reg;
|
|
|
+ case InstrList[Index].oper[0]^.val of
|
|
|
+ 2, 4, 8:
|
|
|
+ NewRef.scalefactor := InstrList[Index].oper[0]^.val;
|
|
|
+ else {3, 5 and 9}
|
|
|
+ begin
|
|
|
+ NewRef.scalefactor := InstrList[Index].oper[0]^.val - 1;
|
|
|
+ NewRef.base := InstrList[Index].oper[1]^.reg;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+ InstrList[Index].loadref(0, NewRef);
|
|
|
+ end;
|
|
|
+ else
|
|
|
+ InternalError(2021051710);
|
|
|
+ end;
|
|
|
+
|
|
|
+ end;
|
|
|
+
|
|
|
+ { Mark the FLAGS register as used across this whole block }
|
|
|
+ AllocRegBetween(NR_DEFAULTFLAGS, p, hp1, UsedRegs);
|
|
|
+ end;
|
|
|
+
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(hp1.next));
|
|
|
+
|
|
|
+ JumpC := taicpu(hp2).condition;
|
|
|
+ Unconditional := False;
|
|
|
+
|
|
|
+ if conditions_equal(JumpC, C_E) then
|
|
|
+ SetC := inverse_cond(taicpu(p).condition)
|
|
|
+ else if conditions_equal(JumpC, C_NE) then
|
|
|
+ SetC := taicpu(p).condition
|
|
|
+ else
|
|
|
+ { We've got something weird here (and inefficent) }
|
|
|
+ begin
|
|
|
+ DebugMsg('DEBUG: Inefficient jump - check code generation', p);
|
|
|
+ SetC := C_NONE;
|
|
|
+
|
|
|
+ { JAE/JNB will always branch (use 'condition_in', since C_AE <> C_NB normally) }
|
|
|
+ if condition_in(C_AE, JumpC) then
|
|
|
+ Unconditional := True
|
|
|
+ else
|
|
|
+ { Not sure what to do with this jump - drop out }
|
|
|
+ Exit;
|
|
|
+ end;
|
|
|
+
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+
|
|
|
+ if Unconditional then
|
|
|
+ MakeUnconditional(taicpu(hp2))
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if SetC = C_NONE then
|
|
|
+ InternalError(2018061402);
|
|
|
+
|
|
|
+ taicpu(hp2).SetCondition(SetC);
|
|
|
+ end;
|
|
|
+
|
|
|
+ if not RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp2, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ RemoveCurrentp(p, hp2);
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SETcc/TEST/Jcc -> Jcc',p);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SETcc/TEST/Jcc -> SETcc/Jcc',p);
|
|
|
+
|
|
|
+ Result := True;
|
|
|
+ end
|
|
|
+ else if
|
|
|
+ { Make sure the instructions are adjacent }
|
|
|
+ (
|
|
|
+ not (cs_opt_level3 in current_settings.optimizerswitches) or
|
|
|
+ GetNextInstruction(p, hp1)
|
|
|
+ ) and
|
|
|
+ MatchInstruction(hp1, A_MOV, [S_B]) and
|
|
|
+ { Writing to memory is allowed }
|
|
|
+ MatchOperand(taicpu(p).oper[0]^, taicpu(hp1).oper[0]^.reg) then
|
|
|
+ begin
|
|
|
+ {
|
|
|
+ Watch out for sequences such as:
|
|
|
+
|
|
|
+ set(c)b %regb
|
|
|
+ movb %regb,(ref)
|
|
|
+ movb $0,1(ref)
|
|
|
+ movb $0,2(ref)
|
|
|
+ movb $0,3(ref)
|
|
|
+
|
|
|
+ Much more efficient to turn it into:
|
|
|
+ movl $0,%regl
|
|
|
+ set(c)b %regb
|
|
|
+ movl %regl,(ref)
|
|
|
+
|
|
|
+ Or:
|
|
|
+ set(c)b %regb
|
|
|
+ movzbl %regb,%regl
|
|
|
+ movl %regl,(ref)
|
|
|
+ }
|
|
|
+ if (taicpu(hp1).oper[1]^.typ = top_ref) and
|
|
|
+ GetNextInstruction(hp1, hp2) and
|
|
|
+ MatchInstruction(hp2, A_MOV, [S_B]) and
|
|
|
+ (taicpu(hp2).oper[1]^.typ = top_ref) and
|
|
|
+ CheckMemoryWrite(taicpu(hp1), taicpu(hp2)) then
|
|
|
+ begin
|
|
|
+ { Don't do anything else except set Result to True }
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if taicpu(p).oper[0]^.typ = top_reg then
|
|
|
+ begin
|
|
|
+ TransferUsedRegs(TmpUsedRegs);
|
|
|
+ UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
|
|
|
+ end;
|
|
|
+
|
|
|
+ { If it's not a register, it's a memory address }
|
|
|
+ if (taicpu(p).oper[0]^.typ <> top_reg) or RegUsedAfterInstruction(taicpu(p).oper[0]^.reg, hp1, TmpUsedRegs) then
|
|
|
+ begin
|
|
|
+ { Even if the register is still in use, we can minimise the
|
|
|
+ pipeline stall by changing the MOV into another SETcc. }
|
|
|
+ taicpu(hp1).opcode := A_SETcc;
|
|
|
+ taicpu(hp1).condition := taicpu(p).condition;
|
|
|
+ if taicpu(hp1).oper[1]^.typ = top_ref then
|
|
|
+ begin
|
|
|
+ { Swapping the operand pointers like this is probably a
|
|
|
+ bit naughty, but it is far faster than using loadoper
|
|
|
+ to transfer the reference from oper[1] to oper[0] if
|
|
|
+ you take into account the extra procedure calls and
|
|
|
+ the memory allocation and deallocation required }
|
|
|
+ OperPtr := taicpu(hp1).oper[1];
|
|
|
+ taicpu(hp1).oper[1] := taicpu(hp1).oper[0];
|
|
|
+ taicpu(hp1).oper[0] := OperPtr;
|
|
|
+ end
|
|
|
+ else
|
|
|
+ taicpu(hp1).oper[0]^.reg := taicpu(hp1).oper[1]^.reg;
|
|
|
+
|
|
|
+ taicpu(hp1).clearop(1);
|
|
|
+ taicpu(hp1).ops := 1;
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SETcc/Mov -> SETcc/SETcc',p);
|
|
|
+ end
|
|
|
+ else
|
|
|
+ begin
|
|
|
+ if taicpu(hp1).oper[1]^.typ = top_reg then
|
|
|
+ AllocRegBetween(taicpu(hp1).oper[1]^.reg,p,hp1,UsedRegs);
|
|
|
+
|
|
|
+ taicpu(p).loadoper(0, taicpu(hp1).oper[1]^);
|
|
|
+ RemoveInstruction(hp1);
|
|
|
+ DebugMsg(SPeepholeOptimization + 'SETcc/Mov -> SETcc',p);
|
|
|
+ end
|
|
|
+ end;
|
|
|
+ Result := True;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+ end;
|
|
|
+
|
|
|
+
|
|
|
function TX86AsmOptimizer.OptPass2Jmp(var p : tai) : boolean;
|
|
|
var
|
|
|
hp1, hp2, hp3: tai;
|
florian