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* set index register correctly * index register might not be changed

git-svn-id: trunk@22229 -
florian 13 years ago
parent
commit
58a85e79ce
1 changed files with 5 additions and 2 deletions
  1. 5 2
      compiler/arm/aoptcpu.pas

+ 5 - 2
compiler/arm/aoptcpu.pas

@@ -380,7 +380,10 @@ Implementation
         (taicpu(hp1).oper[1]^.reg=p.oper[1]^.ref^.base) and
         (taicpu(hp1).oper[1]^.reg=p.oper[1]^.ref^.base) and
         { don't apply the optimization if the base register is loaded }
         { don't apply the optimization if the base register is loaded }
         (p.oper[0]^.reg<>p.oper[1]^.ref^.base) and
         (p.oper[0]^.reg<>p.oper[1]^.ref^.base) and
-        not(RegModifiedBetween(taicpu(hp1).oper[0]^.reg,p,hp1)) then
+        not(RegModifiedBetween(taicpu(hp1).oper[0]^.reg,p,hp1)) and
+        { don't apply the optimization if the (new) index register is loaded }
+        (p.oper[0]^.reg<>taicpu(hp1).oper[2]^.reg) and
+        not(RegModifiedBetween(taicpu(hp1).oper[2]^.reg,p,hp1)) then
         begin
         begin
           DebugMsg('Peephole Str/LdrAdd/Sub2Str/Ldr Postindex done', p);
           DebugMsg('Peephole Str/LdrAdd/Sub2Str/Ldr Postindex done', p);
           p.oper[1]^.ref^.addressmode:=AM_POSTINDEXED;
           p.oper[1]^.ref^.addressmode:=AM_POSTINDEXED;
@@ -393,7 +396,7 @@ Implementation
             end
             end
           else
           else
             begin
             begin
-              p.oper[1]^.ref^.index:=taicpu(hp1).oper[1]^.reg;
+              p.oper[1]^.ref^.index:=taicpu(hp1).oper[2]^.reg;
               if taicpu(hp1).opcode=A_ADD then
               if taicpu(hp1).opcode=A_ADD then
                 p.oper[1]^.ref^.signindex:=1
                 p.oper[1]^.ref^.signindex:=1
               else
               else