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@@ -4088,8 +4088,182 @@
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PROCESSOR_INTEL_386 = 386;
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PROCESSOR_INTEL_386 = 386;
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PROCESSOR_INTEL_486 = 486;
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PROCESSOR_INTEL_486 = 486;
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PROCESSOR_INTEL_PENTIUM = 586;
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PROCESSOR_INTEL_PENTIUM = 586;
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- PROCESSOR_MIPS_R4000 = 4000;
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+ PROCESSOR_MIPS_R4000 = 4000; // incl R4101 & R3910 for Windows CE
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PROCESSOR_ALPHA_21064 = 21064;
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PROCESSOR_ALPHA_21064 = 21064;
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+
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+ PROCESSOR_INTEL_PENTIUMII = 686;
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+ PROCESSOR_MIPS_R5000 = 5000; // incl R5432 for Windows CE
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+ PROCESSOR_PPC_403 = 403;
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+ PROCESSOR_PPC_601 = 601;
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+ PROCESSOR_PPC_603 = 603;
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+ PROCESSOR_PPC_604 = 604;
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+ PROCESSOR_PPC_620 = 620;
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+ PROCESSOR_HITACHI_SH3 = 10003; // Windows CE
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+ PROCESSOR_HITACHI_SH3E = 10004; // Windows CE
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+ PROCESSOR_HITACHI_SH4 = 10005; // Windows CE
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+ PROCESSOR_MOTOROLA_821 = 821; // Windows CE
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+ PROCESSOR_SHx_SH3 = 103; // Windows CE
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+ PROCESSOR_SHx_SH3DSP = 105; // Windows CE
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+ PROCESSOR_SHx_SH4 = 104; // Windows CE
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+ PROCESSOR_STRONGARM = 2577; // Windows CE - 0xA11
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+ PROCESSOR_ARM720 = 1824; // Windows CE - 0x720
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+ PROCESSOR_ARM820 = 2080; // Windows CE - 0x820
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+ PROCESSOR_ARM920 = 2336; // Windows CE - 0x920
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+ PROCESSOR_ARM_7TDMI = 70001; // Windows CE
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+
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+ PROCESSOR_ARCHITECTURE_INTEL = 0;
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+ PROCESSOR_ARCHITECTURE_MIPS = 1;
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+ PROCESSOR_ARCHITECTURE_ALPHA = 2;
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+ PROCESSOR_ARCHITECTURE_PPC = 3;
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+ PROCESSOR_ARCHITECTURE_SHX = 4;
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+ PROCESSOR_ARCHITECTURE_ARM = 5;
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+ PROCESSOR_ARCHITECTURE_IA64 = 6;
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+ PROCESSOR_ARCHITECTURE_ALPHA64 = 7;
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+ PROCESSOR_ARCHITECTURE_UNKNOWN = $FFFF;
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+
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+ PROCESSOR_X86_32BIT_CORE = 1;
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+
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+ PROCESSOR_MIPS16_CORE = 1;
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+ PROCESSOR_MIPSII_CORE = 2;
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+ PROCESSOR_MIPSIV_CORE = 3;
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+
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+ PROCESSOR_HITACHI_SH3_CORE = 1;
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+ PROCESSOR_HITACHI_SH4_CORE = 2;
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+
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+ PROCESSOR_ARM_V4_CORE = 1;
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+ PROCESSOR_ARM_V4I_CORE = 2;
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+ PROCESSOR_ARM_V4T_CORE = 3;
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+
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+ PROCESSOR_FEATURE_NOFP = 0;
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+ PROCESSOR_FEATURE_FP = 1;
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+ PROCESSOR_FEATURE_DSP = PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_QUERY_INSTRUCTION = $00000000;
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+
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+{
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+#define PROCESSOR_INSTRUCTION_CODE(arch, core, feature) \
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+ ((arch) << 24 | (core) << 16 | (feature))
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+}
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+
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+ PROCESSOR_X86_32BIT_INSTRUCTION = (PROCESSOR_ARCHITECTURE_INTEL shl 24) or
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+ (PROCESSOR_X86_32BIT_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_MIPS_MIPS16_INSTRUCTION = (PROCESSOR_ARCHITECTURE_MIPS shl 24) or
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+ (PROCESSOR_MIPS16_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_MIPS_MIPSII_INSTRUCTION = (PROCESSOR_ARCHITECTURE_MIPS shl 24) or
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+ (PROCESSOR_MIPSII_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_MIPS_MIPSIIFP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_MIPS shl 24) or
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+ (PROCESSOR_MIPSII_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_MIPS_MIPSIV_INSTRUCTION = (PROCESSOR_ARCHITECTURE_MIPS shl 24) or
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+ (PROCESSOR_MIPSIV_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_MIPS_MIPSIVFP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_MIPS shl 24) or
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+ (PROCESSOR_MIPSIV_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_HITACHI_SH3_INSTRUCTION = (PROCESSOR_ARCHITECTURE_SHX shl 24) or
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+ (PROCESSOR_HITACHI_SH3_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_HITACHI_SH3DSP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_SHX shl 24) or
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+ (PROCESSOR_HITACHI_SH3_CORE shl 16) or
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+ PROCESSOR_FEATURE_DSP;
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+
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+ PROCESSOR_HITACHI_SH4_INSTRUCTION = (PROCESSOR_ARCHITECTURE_SHX shl 24) or
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+ (PROCESSOR_HITACHI_SH4_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_ARM_V4_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_ARM_V4FP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_ARM_V4I_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4I_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_ARM_V4IFP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4I_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PROCESSOR_ARM_V4T_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4T_CORE shl 16) or
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+ PROCESSOR_FEATURE_NOFP;
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+
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+ PROCESSOR_ARM_V4TFP_INSTRUCTION = (PROCESSOR_ARCHITECTURE_ARM shl 24) or
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+ (PROCESSOR_ARM_V4T_CORE shl 16) or
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+ PROCESSOR_FEATURE_FP;
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+
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+ PF_FLOATING_POINT_PRECISION_ERRATA = 0;
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+ PF_FLOATING_POINT_EMULATED = 1;
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+ PF_COMPARE_EXCHANGE_DOUBLE = 2;
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+ PF_MMX_INSTRUCTIONS_AVAILABLE = 3;
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+ PF_PPC_MOVEMEM_64BIT_OK = 4;
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+ PF_ALPHA_BYTE_INSTRUCTIONS = 5;
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+ PF_XMMI_INSTRUCTIONS_AVAILABLE = 6;
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+ PF_3DNOW_INSTRUCTIONS_AVAILABLE = 7;
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+ PF_RDTSC_INSTRUCTION_AVAILABLE = 8;
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+ PF_PAE_ENABLED = 9;
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+ PF_XMMI64_INSTRUCTIONS_AVAILABLE = 10;
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+
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+{ Table from MSDN. Instruction set compatibility.
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+OS instructions set Supported instruction sets
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+--------------------------------------------------------------------------------
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+PROCESSOR_X86_32BIT_INSTRUCTION PROCESSOR_X86_32BIT_INSTRUCTION
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+
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+PROCESSOR_MIPS_MIPS16_INSTRUCTION PROCESSOR_MIPS_MIPS16_INSTRUCTION
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+ PROCESSOR_MIPS_MIPSII_INSTRUCTION
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+
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+PROCESSOR_MIPS_MIPSII_INSTRUCTION PROCESSOR_MIPS_MIPSII_INSTRUCTION
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+
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+PROCESSOR_MIPS_MIPSIIFP_INSTRUCTION PROCESSOR_MIPS_MIPSIIFP_INSTRUCTION
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+
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+PROCESSOR_MIPS_MIPSIV_INSTRUCTION PROCESSOR_MIPS_MIPSIV_INSTRUCTION
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+
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+PROCESSOR_MIPS_MIPSIVFP_INSTRUCTION PROCESSOR_MIPS_MIPSIVFP_INSTRUCTION
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+
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+PROCESSOR_HITACHI_SH3_INSTRUCTION PROCESSOR_HITACHI_SH3_INSTRUCTION
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+
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+PROCESSOR_HITACHI_SH3DSP_INSTRUCTION PROCESSOR_HITACHI_SH3DSP_INSTRUCTION
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+ PROCESSOR_HITACHI_SH3_INSTRUCTION
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+
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+PROCESSOR_HITACHI_SH4_INSTRUCTION PROCESSOR_HITACHI_SH4_INSTRUCTION
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+
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+PROCESSOR_ARM_V4_INSTRUCTION PROCESSOR_ARM_V4_INSTRUCTION
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+
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+PROCESSOR_ARM_V4FP_INSTRUCTION PROCESSOR_ARM_V4FP_INSTRUCTION
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+ PROCESSOR_ARM_V4_INSTRUCTION
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+
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+PROCESSOR_ARM_V4I_INSTRUCTION PROCESSOR_ARM_V4I_INSTRUCTION
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+ PROCESSOR_ARM_V4T_INSTRUCTION
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+
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+PROCESSOR_ARM_V4IFP_INSTRUCTION PROCESSOR_ARM_V4IFP_INSTRUCTION
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+ PROCESSOR_ARM_V4TFP_INSTRUCTION
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+ PROCESSOR_ARM_V4I_INSTRUCTION
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+ PROCESSOR_ARM_V4T_INSTRUCTION
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+
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+PROCESSOR_ARM_V4T_INSTRUCTION PROCESSOR_ ARM_V4I_INSTRUCTION
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+ PROCESSOR_ARM_V4T_INSTRUCTION
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+
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+PROCESSOR_ARM_V4TFP_INSTRUCTION PROCESSOR_ARM_V4TFP_INSTRUCTION
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+ PROCESSOR_ARM_V4IFP_INSTRUCTION
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+ PROCESSOR_ARM_V4I_INSTRUCTION
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+ PROCESSOR_ARM_V4T_INSTRUCTION
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+}
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+
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+
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+
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{ FSCTL_SET_COMPRESSION }
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{ FSCTL_SET_COMPRESSION }
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COMPRESSION_FORMAT_NONE = 0;
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COMPRESSION_FORMAT_NONE = 0;
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COMPRESSION_FORMAT_DEFAULT = 1;
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COMPRESSION_FORMAT_DEFAULT = 1;
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@@ -5269,10 +5443,12 @@
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STATUS_STACK_OVERFLOW = $C00000FD;
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STATUS_STACK_OVERFLOW = $C00000FD;
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STATUS_CONTROL_C_EXIT = $C000013A;
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STATUS_CONTROL_C_EXIT = $C000013A;
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{$define EXCEPTION_CTRL_C}
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{$define EXCEPTION_CTRL_C}
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+{ Declared above.
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PROCESSOR_ARCHITECTURE_INTEL = 0;
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PROCESSOR_ARCHITECTURE_INTEL = 0;
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PROCESSOR_ARCHITECTURE_MIPS = 1;
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PROCESSOR_ARCHITECTURE_MIPS = 1;
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PROCESSOR_ARCHITECTURE_ALPHA = 2;
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PROCESSOR_ARCHITECTURE_ALPHA = 2;
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PROCESSOR_ARCHITECTURE_PPC = 3;
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PROCESSOR_ARCHITECTURE_PPC = 3;
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+}
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{ was #define dname(params) def_expr }
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{ was #define dname(params) def_expr }
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function FreeModule(h:HINST):WINBOOL;
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function FreeModule(h:HINST):WINBOOL;
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yury