Merge remote-tracking branch 'origin/main' into tg74/avx512-0037785

# Conflicts:
#	.gitattributes
#	compiler/msgidx.inc
#	compiler/msgtxt.inc

.gitattributes

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 * text=auto !eol
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+*.bak
+*.exe
+*.ppu
+*.pcp
+*.o
+*.s
+*.fpm
+*.a
+*.hex
+*.elf
+*.bin
+*.so
+*.dll
+*.ppl
+.*.swp
+*~
+*.lps
+*.elg
+*.log
+*.obj
+*.asm
+*.rsj
+*.res
+*.orig
+*.rej
+*.patch
+*.diff
+*.lst
+*.app
+fpcmade.*
+*-stamp.*
+build-stamp.*
+log.*
+faillist.*
+longlog.*
+bin
+backup
+lazbuild
+*.wpo
+a.out
+/compiler/ppc*
+!/compiler/ppc*.lpi
+*.lpi
+!/compiler/ppc*.pas
+/compiler/*/pp
+/compiler/utils/fpc
+/compiler/utils/msg2inc
+/compiler/utils/mka64ins
+/compiler/utils/mkz80ins
+/compiler/utils/mkarmins
+/compiler/utils/mkx86ins
+/compiler/utils/ppudump
+/compiler/utils/ppufiles
+/compiler/utils/ppumove
+/compiler/utils/mkx86inl
+/packages/fpmake
+/packages/fpmkunit/units_bs
+/utils/fpmake
+units
+/tests/output
+!/tests/test/units
+bin/
+fpmake

LICENSE

@@ -0,0 +1,366 @@
+This is the file COPYING.FPC, it applies to the Free Pascal Run-Time Library 
+(RTL) and packages (packages) distributed by members of the Free Pascal 
+Development Team.
+
+The source code of the Free Pascal Runtime Libraries and packages are 
+distributed under the Library GNU General Public License 
+(see the file COPYING) with the following modification:
+
+As a special exception, the copyright holders of this library give you
+permission to link this library with independent modules to produce an
+executable, regardless of the license terms of these independent modules,
+and to copy and distribute the resulting executable under terms of your choice,
+provided that you also meet, for each linked independent module, the terms
+and conditions of the license of that module. An independent module is a module
+which is not derived from or based on this library. If you modify this
+library, you may extend this exception to your version of the library, but you are
+not obligated to do so. If you do not wish to do so, delete this exception
+statement from your version.
+
+If you didn't receive a copy of the file COPYING, contact:
+      Free Software Foundation
+      675 Mass Ave
+      Cambridge, MA  02139
+      USA
+
+The compiler itself is licensed under the GPL V2:
+
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Lesser General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
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+that everyone understands that there is no warranty for this free
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+want its recipients to know that what they have is not the original, so
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+
+                    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
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+a notice placed by the copyright holder saying it may be distributed
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+running the Program is not restricted, and the output from the Program
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+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
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+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
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+
+  2. You may modify your copy or copies of the Program or any portion
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+These requirements apply to the modified work as a whole.  If
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+
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+exercise the right to control the distribution of derivative or
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+
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+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
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+under Section 2) in object code or executable form under the terms of
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+
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+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+                            NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    testconversion
+    Copyright (C) 2021  FPC
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License along
+    with this program; if not, write to the Free Software Foundation, Inc.,
+    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.

Makefile

@@ -2,7 +2,7 @@
 # Don't edit, this file is generated by FPCMake Version 2.0.0
 #
 default: help
-MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
+MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-freebsd aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm32-embedded wasm32-wasi sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
 BSDs = freebsd netbsd openbsd darwin dragonfly
 UNIXs = linux $(BSDs) solaris qnx haiku aix
 LIMIT83fs = go32v2 os2 emx watcom msdos win16 atari
@@ -349,8 +349,8 @@ endif
 endif
 override PACKAGE_NAME=fpc
 override PACKAGE_VERSION=3.3.1
-REQUIREDVERSION=3.2.0
-REQUIREDVERSION2=3.0.4
+REQUIREDVERSION=3.2.2
+REQUIREDVERSION2=3.2.0
 ifndef inOS2
 override FPCDIR:=$(BASEDIR)
 export FPCDIR
@@ -419,6 +419,9 @@ endif
 ifeq ($(CPU_TARGET),z80)
 PPSUF=z80
 endif
+ifeq ($(CPU_TARGET),wasm32)
+PPSUF=wasm32
+endif
 ifdef CROSSCOMPILE
 ifneq ($(CPU_TARGET),jvm)
 PPPRE=ppcross
@@ -772,6 +775,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override TARGET_DIRS+=compiler rtl utils packages installer
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
@@ -784,7 +790,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override TARGET_DIRS+=compiler rtl utils packages installer
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override TARGET_DIRS+=compiler rtl utils packages installer
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -1073,10 +1082,18 @@ else
 ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
 FPCMAKE_CROSSGCCOPT=-mabi=32
 else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),riscv64),)
+FPCMAKE_CROSSGCCOPT=-mabi=lp64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),riscv32),)
+FPCMAKE_CROSSGCCOPT=-mabi=ilp32
+else
 FPCMAKE_CROSSGCCOPT=-m32
 endif
 endif
 endif
+endif
+endif
 FPCMAKEGCCLIBDIR:=$(shell dirname `gcc $(FPCMAKE_CROSSGCCOPT) -print-libgcc-file-name`)
 endif
 endif
@@ -1323,6 +1340,9 @@ endif
 ifeq ($(OS_TARGET),zxspectrum)
 OEXT=.rel
 endif
+ifeq ($(OS_TARGET),wasi)
+EXEEXT=.wasm
+endif
 ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)
 FPCMADE=fpcmade.$(SHORTSUFFIX)
 ZIPSUFFIX=$(SHORTSUFFIX)
@@ -1680,11 +1700,24 @@ override COMPILER_UNITTARGETDIR=$(COMPILER_TARGETDIR)
 override UNITTARGETDIRPREFIX=$(TARGETDIRPREFIX)
 endif
 endif
+ifdef SYSROOTPATH
+override FPCOPT+=-XR$(SYSROOTPATH)
+else
+ifeq ($(OS_TARGET),$(OS_SOURCE))
+ifneq ($(findstring $(OS_TARGET),darwin),)
+ifneq ($(findstring $(CPU_TARGET),aarch64),)
+ifneq ($(wildcard /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk),)
+override FPCOPT+=-XR/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk
+endif
+endif
+endif
+endif
+endif
 ifdef CREATESHARED
 override FPCOPT+=-Cg
 endif
 ifneq ($(findstring $(OS_TARGET),dragonfly freebsd openbsd netbsd linux solaris),)
-ifneq ($(findstring $(CPU_TARGET),x86_64 mips mipsel),)
+ifneq ($(findstring $(CPU_TARGET),x86_64 mips mipsel riscv64),)
 override FPCOPT+=-Cg
 endif
 endif
@@ -2709,6 +2742,13 @@ TARGET_DIRS_UTILS=1
 TARGET_DIRS_PACKAGES=1
 TARGET_DIRS_INSTALLER=1
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+TARGET_DIRS_COMPILER=1
+TARGET_DIRS_RTL=1
+TARGET_DIRS_UTILS=1
+TARGET_DIRS_PACKAGES=1
+TARGET_DIRS_INSTALLER=1
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 TARGET_DIRS_COMPILER=1
 TARGET_DIRS_RTL=1
@@ -2737,7 +2777,14 @@ TARGET_DIRS_UTILS=1
 TARGET_DIRS_PACKAGES=1
 TARGET_DIRS_INSTALLER=1
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+TARGET_DIRS_COMPILER=1
+TARGET_DIRS_RTL=1
+TARGET_DIRS_UTILS=1
+TARGET_DIRS_PACKAGES=1
+TARGET_DIRS_INSTALLER=1
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 TARGET_DIRS_COMPILER=1
 TARGET_DIRS_RTL=1
 TARGET_DIRS_UTILS=1

Makefile.fpc

@@ -20,8 +20,8 @@ fpcdir=.
 rule=help
 
 [prerules]
-REQUIREDVERSION=3.2.0
-REQUIREDVERSION2=3.0.4
+REQUIREDVERSION=3.2.2
+REQUIREDVERSION2=3.2.0
 
 
 # make versions < 3.77 (OS2 version) are buggy
@@ -97,6 +97,9 @@ endif
 ifeq ($(CPU_TARGET),z80)
 PPSUF=z80
 endif
+ifeq ($(CPU_TARGET),wasm32)
+PPSUF=wasm32
+endif
 
 # cross compilers uses full cpu_target, not just ppc-suffix
 # (except if the target cannot run a native compiler)

README.md

@@ -0,0 +1,19 @@
+# FPC Source code repository
+
+## Synopsis
+This repository contains the sources of the [Free Pascal](https://www.freepascal.org/) compiler distribution.
+
+
+It contains
+* The compiler sources in the directory *compiler*.
+* The run-time library in the directory *rtl*.
+* The packages distributed with the compiler in the directory *packages*.
+* Several utilities in the directory *utils*.
+* The compiler testsuite in the directory *tests*.
+
+## License
+The compiler is licensed under GPL v2, the run-time files are licensed under modified LGPL. 
+Both can be found in the LICENSE file, and the file rtl/COPYING.txt
+
+## Documentation
+Extensive documentation can be found on the [documentation website](https://docs.freepascal.org/). 

compiler/Makefile

@@ -2,7 +2,7 @@
 # Don't edit, this file is generated by FPCMake Version 2.0.0
 #
 default: all
-MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm-wasm sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
+MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim i386-android i386-aros m68k-linux m68k-netbsd m68k-amiga m68k-atari m68k-palmos m68k-macosclassic m68k-embedded m68k-sinclairql powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macosclassic powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-haiku x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded x86_64-iphonesim x86_64-android x86_64-aros x86_64-dragonfly arm-linux arm-netbsd arm-palmos arm-wince arm-gba arm-nds arm-embedded arm-symbian arm-android arm-aros arm-freertos arm-ios powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux mipsel-embedded mipsel-android mips64el-linux jvm-java jvm-android i8086-embedded i8086-msdos i8086-win16 aarch64-linux aarch64-freebsd aarch64-darwin aarch64-win64 aarch64-android aarch64-ios wasm32-embedded wasm32-wasi sparc64-linux riscv32-linux riscv32-embedded riscv64-linux riscv64-embedded xtensa-linux xtensa-embedded xtensa-freertos z80-embedded z80-zxspectrum z80-msxdos z80-amstradcpc
 BSDs = freebsd netbsd openbsd darwin dragonfly
 UNIXs = linux $(BSDs) solaris qnx haiku aix
 LIMIT83fs = go32v2 os2 emx watcom msdos win16 atari
@@ -350,10 +350,10 @@ endif
 override PACKAGE_NAME=compiler
 override PACKAGE_VERSION=3.3.1
 unexport FPC_VERSION FPC_COMPILERINFO
-CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80
+CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80 wasm32
 ALLTARGETS=$(CYCLETARGETS)
-NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos symbian watcom wii win16 zxspectrum
-NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80
+NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos sinclairql symbian watcom wii win16 zxspectrum
+NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80 wasm32
 ifneq ($(CPU_SOURCE),$(CPU_TARGET))
 ifneq ($(findstring $(CPU_TARGET),$(NO_NATIVE_COMPILER_CPU_LIST)),)
 NoNativeBinaries=1
@@ -552,6 +552,9 @@ endif
 ifeq ($(CPC_TARGET),z80)
 CPUSUF=z80
 endif
+ifeq ($(CPC_TARGET),wasm32)
+CPUSUF=wasm32
+endif
 NOCPUDEF=1
 MSGFILE=msg/error$(FPCLANG).msg
 SVNVERSION:=$(firstword $(wildcard $(addsuffix /svnversion$(SRCEXEEXT),$(SEARCHPATH))))
@@ -578,13 +581,13 @@ endif
 endif
 endif
 endif
-override LOCALOPT+=-d$(CPC_TARGET) -dGDB -dBROWSERLOG
+override LOCALOPT+=-d$(CPC_TARGET) -dGDB
 ifdef LLVM
 ifeq ($(findstring $(PPC_TARGET),x86_64 aarch64 arm),)
 $(error The $(PPC_TARGET) architecture is not (yet) supported by the FPC/LLVM code generator)
 endif
 ifeq ($(findstring $(OS_TARGET),darwin iphonesim linux),)
-$(error The $(PPC_TARGET) target OS is not (yet) supported by the FPC/LLVM code generator)
+$(error The $(OS_TARGET) target OS is not (yet) supported by the FPC/LLVM code generator)
 endif
 override LOCALOPT+=-dllvm -Fullvm
 endif
@@ -633,6 +636,9 @@ endif
 ifeq ($(PPC_TARGET),riscv64)
 override LOCALOPT+=-Furiscv
 endif
+ifeq ($(PPC_TARGET),wasm32)
+override LOCALOPT+=-dNOOPT
+endif
 OPTWPOCOLLECT=-OWdevirtcalls,optvmts -FW$(BASEDIR)/pp1.wpo
 OPTWPOPERFORM=-Owdevirtcalls,optvmts -Fw$(BASEDIR)/pp1.wpo
 ifneq ($(findstring $(OS_TARGET),darwin linux dragonfly freebsd solaris),)
@@ -904,6 +910,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override TARGET_DIRS+=utils
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override TARGET_DIRS+=utils
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override TARGET_DIRS+=utils
 endif
@@ -916,7 +925,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override TARGET_DIRS+=utils
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override TARGET_DIRS+=utils
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override TARGET_DIRS+=utils
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -1216,6 +1228,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override TARGET_PROGRAMS+=pp
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override TARGET_PROGRAMS+=pp
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override TARGET_PROGRAMS+=pp
 endif
@@ -1228,7 +1243,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override TARGET_PROGRAMS+=pp
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override TARGET_PROGRAMS+=pp
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override TARGET_PROGRAMS+=pp
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -1529,6 +1547,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
@@ -1541,7 +1562,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override COMPILER_INCLUDEDIR+=$(CPC_TARGET)
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -1841,6 +1865,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
@@ -1853,7 +1880,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override COMPILER_UNITDIR+=$(COMPILERSOURCEDIR)
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -2153,6 +2183,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
@@ -2165,7 +2198,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override COMPILER_TARGETDIR+=$(CPU_UNITDIR)/bin/$(FULL_TARGET)
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -2465,6 +2501,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
@@ -2477,7 +2516,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 override COMPILER_UNITTARGETDIR+=$(CPU_UNITDIR)/units/$(FULL_TARGET)
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -2765,10 +2807,18 @@ else
 ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),mips mipsel),)
 FPCMAKE_CROSSGCCOPT=-mabi=32
 else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),riscv64),)
+FPCMAKE_CROSSGCCOPT=-mabi=lp64
+else
+ifneq ($(findstring $(FPCFPMAKE_CPU_OPT),riscv32),)
+FPCMAKE_CROSSGCCOPT=-mabi=ilp32
+else
 FPCMAKE_CROSSGCCOPT=-m32
 endif
 endif
 endif
+endif
+endif
 FPCMAKEGCCLIBDIR:=$(shell dirname `gcc $(FPCMAKE_CROSSGCCOPT) -print-libgcc-file-name`)
 endif
 endif
@@ -3015,6 +3065,9 @@ endif
 ifeq ($(OS_TARGET),zxspectrum)
 OEXT=.rel
 endif
+ifeq ($(OS_TARGET),wasi)
+EXEEXT=.wasm
+endif
 ifneq ($(findstring $(OS_SOURCE),$(LIMIT83fs)),)
 FPCMADE=fpcmade.$(SHORTSUFFIX)
 ZIPSUFFIX=$(SHORTSUFFIX)
@@ -3531,6 +3584,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 REQUIRE_PACKAGES_RTL=1
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+REQUIRE_PACKAGES_RTL=1
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 REQUIRE_PACKAGES_RTL=1
 endif
@@ -3543,7 +3599,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 REQUIRE_PACKAGES_RTL=1
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+REQUIRE_PACKAGES_RTL=1
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 REQUIRE_PACKAGES_RTL=1
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -3723,11 +3782,24 @@ override COMPILER_UNITTARGETDIR=$(COMPILER_TARGETDIR)
 override UNITTARGETDIRPREFIX=$(TARGETDIRPREFIX)
 endif
 endif
+ifdef SYSROOTPATH
+override FPCOPT+=-XR$(SYSROOTPATH)
+else
+ifeq ($(OS_TARGET),$(OS_SOURCE))
+ifneq ($(findstring $(OS_TARGET),darwin),)
+ifneq ($(findstring $(CPU_TARGET),aarch64),)
+ifneq ($(wildcard /Library/Developer/CommandLineTools/SDKs/MacOSX.sdk),)
+override FPCOPT+=-XR/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk
+endif
+endif
+endif
+endif
+endif
 ifdef CREATESHARED
 override FPCOPT+=-Cg
 endif
 ifneq ($(findstring $(OS_TARGET),dragonfly freebsd openbsd netbsd linux solaris),)
-ifneq ($(findstring $(CPU_TARGET),x86_64 mips mipsel),)
+ifneq ($(findstring $(CPU_TARGET),x86_64 mips mipsel riscv64),)
 override FPCOPT+=-Cg
 endif
 endif
@@ -4498,6 +4570,9 @@ endif
 ifeq ($(FULL_TARGET),aarch64-linux)
 TARGET_DIRS_UTILS=1
 endif
+ifeq ($(FULL_TARGET),aarch64-freebsd)
+TARGET_DIRS_UTILS=1
+endif
 ifeq ($(FULL_TARGET),aarch64-darwin)
 TARGET_DIRS_UTILS=1
 endif
@@ -4510,7 +4585,10 @@ endif
 ifeq ($(FULL_TARGET),aarch64-ios)
 TARGET_DIRS_UTILS=1
 endif
-ifeq ($(FULL_TARGET),wasm-wasm)
+ifeq ($(FULL_TARGET),wasm32-embedded)
+TARGET_DIRS_UTILS=1
+endif
+ifeq ($(FULL_TARGET),wasm32-wasi)
 TARGET_DIRS_UTILS=1
 endif
 ifeq ($(FULL_TARGET),sparc64-linux)
@@ -4762,8 +4840,8 @@ endif
 ifdef TEMPWPONAME2PREFIX
 	$(MAKE) g$(TEMPWPONAME2) COMPILERTEMPNAME=$(TEMPWPONAME2)
 endif
-PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80
-PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64 xtensa z80
+PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80 wasm32
+PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64 xtensa z80 wasm32
 INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
 SYMLINKINSTALL_TARGETS=$(addsuffix _symlink_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
 .PHONY: $(PPC_TARGETS) $(INSTALL_TARGETS)$(SYMLINKINSTALL_TARGETS)
@@ -4867,7 +4945,10 @@ regdatmips : mips/mipsreg.dat
 regdatz80 : z80/z80reg.dat
 	    $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkz80reg.pp
 	cd z80 && ..$(PATHSEP)utils$(PATHSEP)mkz80reg$(SRCEXEEXT)
-regdat : regdatx86 regdatarm regdatsp regdatavr regdataarch64 regdatmips regdatsp64 regdatz80
+regdatwasm : wasm32/wasmreg.dat
+	    $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkwasmreg.pp
+	cd wasm32 && ..$(PATHSEP)utils$(PATHSEP)mkwasmreg$(SRCEXEEXT)
+regdat : regdatx86 regdatarm regdatsp regdatavr regdataarch64 regdatmips regdatsp64 regdatz80 regdatwasm
 intrdatx86 : x86/x86intr.dat
 		$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkx86inl.pp
 	cd x86 && ..$(PATHSEP)utils$(PATHSEP)mkx86inl$(SRCEXEEXT)
@@ -4913,7 +4994,7 @@ endif
 	$(COMPILER) pp.pas
 	$(EXECPPAS)
 	$(MOVE) $(COMPILER_TARGETDIR)/$(PPEXENAME) $(EXENAME)
-.PHONY: cycle fullcycle wpocycle
+.PHONY: cycle full full_targets fullcycle wpocycle
 ifeq ($(CPU_SOURCE),$(PPC_TARGET))
 ifeq ($(OS_SOURCE),$(OS_TARGET))
 ifndef NOWPOCYCLE
@@ -5052,7 +5133,9 @@ endif
 cycledep:
 	$(MAKE) cycle USEDEPEND=1
 extcycle:
-	$(MAKE) cycle OPT="$(OPT) -n -OG2p3 -glttt -CRriot -dEXTDEBUG" ALLOW_WARNINGS=1
+	$(MAKE) cycle RTLOPT="$(RTLOPT) -n -glttt -CRriot -dEXTDEBUG" LOCALOPT="$(LOCALOPT) -n -glttt -CRriot -dEXTDEBUG" ALLOW_WARNINGS=1
+extoptcycle:
+	$(MAKE) cycle RTLOPT="$(RTLOPT) -n -glttt -CRriot -dEXTDEBUG -dDEBUG_ALL_OPT" LOCALOPT="$(LOCALOPT) -n -glttt -CRriot -dEXTDEBUG -dDEBUG_ALL_OPT" ALLOW_WARNINGS=1
 cvstest:
 	$(MAKE) cycle 'LOCALOPT=-n -Se' 'RTLOPT=-n -Se'
 ifeq ($(findstring -dFPC_SOFT_FPUX80,$(LOCALOPT)),)
@@ -5078,6 +5161,8 @@ ifdef DOWPOCYCLE
 	$(MAKE) rtl 'FPC=$(BASEDIR)/$(EXENAMEPREFIX)$(EXENAME)'
 endif
 	$(MAKE) $(FULL_TARGETS) 'FPC=$(BASEDIR)/$(EXENAMEPREFIX)$(EXENAME)'
+full_targets:
+	$(MAKE) $(FULL_TARGETS)
 htmldocs:
 	$(PASDOC) -p -h -o html$(PATHSEP)$(PPC_TARGET) -d fpc -d gdb -d $(PPC_TARGET) -u $(PPC_TARGET) $(PPC_TARGET)$(PATHSEP)*.pas systems$(PATHSEP)*.pas *.pas
 .PHONY: quickinstall exeinstall install installsymlink fullinstall fullinstallsymlink

compiler/Makefile.fpc

@@ -32,15 +32,15 @@ fpcdir=..
 unexport FPC_VERSION FPC_COMPILERINFO
 
 # Which platforms are ready for inclusion in the cycle
-CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80
+CYCLETARGETS=i386 powerpc sparc arm x86_64 powerpc64 m68k armeb mipsel mips avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80 wasm32
 
 # All supported targets used for clean
 ALLTARGETS=$(CYCLETARGETS)
 
 # All OS targets that do not support native compiler
-NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos symbian watcom wii win16 zxspectrum
+NO_NATIVE_COMPILER_OS_LIST=amstradcpc embedded freertos gba macosclassic msdos msxdos nds palmos sinclairql symbian watcom wii win16 zxspectrum
 # All CPU targets that do not support native compiler
-NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80
+NO_NATIVE_COMPILER_CPU_LIST=avr i8086 jvm z80 wasm32
 
 # Don't compile a native compiler & utilities for targets
 # which do not support it
@@ -279,6 +279,9 @@ endif
 ifeq ($(CPC_TARGET),z80)
 CPUSUF=z80
 endif
+ifeq ($(CPC_TARGET),wasm32)
+CPUSUF=wasm32
+endif
 
 # Do not define the default -d$(CPU_TARGET) because that
 # will conflict with our -d$(CPC_TARGET)
@@ -320,7 +323,7 @@ endif
 endif
 
 # set correct defines (-d$(CPU_TARGET) is automatically added in makefile.fpc)
-override LOCALOPT+=-d$(CPC_TARGET) -dGDB -dBROWSERLOG
+override LOCALOPT+=-d$(CPC_TARGET) -dGDB
 
 #include LLVM define/directory if requested
 ifdef LLVM
@@ -329,7 +332,7 @@ $(error The $(PPC_TARGET) architecture is not (yet) supported by the FPC/LLVM co
 endif
 
 ifeq ($(findstring $(OS_TARGET),darwin iphonesim linux),)
-$(error The $(PPC_TARGET) target OS is not (yet) supported by the FPC/LLVM code generator)
+$(error The $(OS_TARGET) target OS is not (yet) supported by the FPC/LLVM code generator)
 endif
 
 override LOCALOPT+=-dllvm -Fullvm
@@ -410,6 +413,11 @@ ifeq ($(PPC_TARGET),riscv64)
 override LOCALOPT+=-Furiscv
 endif
 
+# WASM32 specific
+ifeq ($(PPC_TARGET),wasm32)
+override LOCALOPT+=-dNOOPT
+endif
+
 OPTWPOCOLLECT=-OWdevirtcalls,optvmts -FW$(BASEDIR)/pp1.wpo
 OPTWPOPERFORM=-Owdevirtcalls,optvmts -Fw$(BASEDIR)/pp1.wpo
 # symbol liveness WPO requires nm, smart linking and no stripping (the latter
@@ -613,8 +621,8 @@ endif
 # cpu targets
 #####################################################################
 
-PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80
-PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64 xtensa z80
+PPC_TARGETS=i386 m68k powerpc sparc arm armeb x86_64 powerpc64 mips mipsel avr jvm i8086 aarch64 sparc64 riscv32 riscv64 xtensa z80 wasm32
+PPC_SUFFIXES=386 68k ppc sparc arm armeb x64 ppc64 mips mipsel avr jvm 8086 a64 sparc64 rv32 rv64 xtensa z80 wasm32
 INSTALL_TARGETS=$(addsuffix _exe_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
 SYMLINKINSTALL_TARGETS=$(addsuffix _symlink_install,$(sort $(CYCLETARGETS) $(PPC_TARGETS)))
 
@@ -766,7 +774,11 @@ regdatz80 : z80/z80reg.dat
             $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkz80reg.pp
         cd z80 && ..$(PATHSEP)utils$(PATHSEP)mkz80reg$(SRCEXEEXT)
 
-regdat : regdatx86 regdatarm regdatsp regdatavr regdataarch64 regdatmips regdatsp64 regdatz80
+regdatwasm : wasm32/wasmreg.dat
+	    $(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkwasmreg.pp
+        cd wasm32 && ..$(PATHSEP)utils$(PATHSEP)mkwasmreg$(SRCEXEEXT)
+
+regdat : regdatx86 regdatarm regdatsp regdatavr regdataarch64 regdatmips regdatsp64 regdatz80 regdatwasm
 
 intrdatx86 : x86/x86intr.dat
 		$(COMPILER) -FE$(COMPILERUTILSDIR) $(COMPILERUTILSDIR)/mkx86inl.pp
@@ -839,7 +851,7 @@ endif
 #
 #####################################################################
 
-.PHONY: cycle fullcycle wpocycle
+.PHONY: cycle full full_targets fullcycle wpocycle
 
 ifeq ($(CPU_SOURCE),$(PPC_TARGET))
 
@@ -1024,7 +1036,10 @@ cycledep:
 # extcycle should still work, but generates
 # lots of warnings, so ALLOW_WARNINGS=1 is required
 extcycle:
-        $(MAKE) cycle OPT="$(OPT) -n -OG2p3 -glttt -CRriot -dEXTDEBUG" ALLOW_WARNINGS=1
+        $(MAKE) cycle RTLOPT="$(RTLOPT) -n -glttt -CRriot -dEXTDEBUG" LOCALOPT="$(LOCALOPT) -n -glttt -CRriot -dEXTDEBUG" ALLOW_WARNINGS=1
+
+extoptcycle:
+        $(MAKE) cycle RTLOPT="$(RTLOPT) -n -glttt -CRriot -dEXTDEBUG -dDEBUG_ALL_OPT" LOCALOPT="$(LOCALOPT) -n -glttt -CRriot -dEXTDEBUG -dDEBUG_ALL_OPT" ALLOW_WARNINGS=1
 
 cvstest:
         $(MAKE) cycle 'LOCALOPT=-n -Se' 'RTLOPT=-n -Se'
@@ -1041,7 +1056,8 @@ cvstest:
 # unless FPC_SUPPORT_X87_TYPES_ON_WIN64 is set,
 # win64 cannot compile i386 or i8086 compiler
 # This is also the case for other CPUs that don't support
-# 80bit real type.
+# 80bit real type, unless -dFPC_SOFT_FPUX80
+# option is used.
 
 ifeq ($(findstring -dFPC_SOFT_FPUX80,$(LOCALOPT)),)
 ifeq ($(OS_SOURCE),win64)
@@ -1071,6 +1087,9 @@ ifdef DOWPOCYCLE
 endif
         $(MAKE) $(FULL_TARGETS) 'FPC=$(BASEDIR)/$(EXENAMEPREFIX)$(EXENAME)'
 
+full_targets:
+	$(MAKE) $(FULL_TARGETS)
+
 #####################################################################
 # Docs
 #####################################################################

compiler/aarch64/a64att.inc

@@ -397,5 +397,32 @@
 'lsr',
 'ror',
 'neg',
-'ins'
+'ins',
+'ldclr',
+'ldeor',
+'ldset',
+'ldsmax',
+'ldsmin',
+'ldumax',
+'ldumin',
+'stadd',
+'stclr',
+'steor',
+'stset',
+'stsmax',
+'stsmin',
+'stumax',
+'stumin',
+'swp',
+'swpa',
+'swpal',
+'swpl',
+'ldadd',
+'ldadda',
+'ldaddal',
+'ldaddl',
+'cas',
+'casa',
+'casal',
+'casl'
 );

compiler/aarch64/a64atts.inc

@@ -397,5 +397,32 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/aarch64/a64ins.dat

@@ -798,3 +798,60 @@
 
 [INS]
 
+; Large System Extensions
+
+
+[LDCLR]
+
+[LDEOR]
+
+[LDSET]
+
+[LDSMAX]
+
+[LDSMIN]
+
+[LDUMAX]
+
+[LDUMIN]
+
+[STADD]
+
+[STCLR]
+
+[STEOR]
+
+[STSET]
+
+[STSMAX]
+
+[STSMIN]
+
+[STUMAX]
+
+[STUMIN]
+
+[SWP]
+
+[SWPA]
+
+[SWPAL]
+
+[SWPL]
+
+[LDADD]
+
+[LDADDA]
+
+[LDADDAL]
+
+[LDADDL]
+
+[CAS]
+
+[CASA]
+
+[CASAL]
+
+[CASL]
+

compiler/aarch64/a64op.inc

@@ -397,5 +397,32 @@ A_LSL,
 A_LSR,
 A_ROR,
 A_NEG,
-A_INS
+A_INS,
+A_LDCLR,
+A_LDEOR,
+A_LDSET,
+A_LDSMAX,
+A_LDSMIN,
+A_LDUMAX,
+A_LDUMIN,
+A_STADD,
+A_STCLR,
+A_STEOR,
+A_STSET,
+A_STSMAX,
+A_STSMIN,
+A_STUMAX,
+A_STUMIN,
+A_SWP,
+A_SWPA,
+A_SWPAL,
+A_SWPL,
+A_LDADD,
+A_LDADDA,
+A_LDADDAL,
+A_LDADDL,
+A_CAS,
+A_CASA,
+A_CASAL,
+A_CASL
 );

compiler/aarch64/aasmcpu.pas

@@ -882,10 +882,27 @@ implementation
                   else
                     result:=sr_complex;
                 end;
+              A_LDADD,
+              A_LDADDA,
+              A_LDADDAL,
+              A_LDADDL,
+
+              A_SWP,
+              A_SWPA,
+              A_SWPAL,
+              A_SWPL,
+
+              A_CAS,
+              A_CASA,
+              A_CASAL,
+              A_CASL,
+
+              A_STADD,
               A_LDAR,
               A_LDAXR,
               A_LDXR,
               A_LDXP,
+
               A_STLR,
               A_STLXR,
               A_STLXP,
@@ -1044,13 +1061,20 @@ implementation
                  { check for pre/post indexed in spilling_get_operation_type_ref }
                  result:=operand_read;
              end;
+           A_MOVK,
+           A_BFI:
+             begin
+               if opnr=0 then
+                 result:=operand_readwrite
+               else
+                 result:=operand_read;
+             end;
 {$ifdef EXTDEBUG}
            { play save to avoid hard to find bugs, better fail at compile time }
            A_ADD,
            A_ADRP,
            A_AND,
            A_ASR,
-           A_BFI,
            A_BFXIL,
            A_CLZ,
            A_CSEL,
@@ -1078,7 +1102,6 @@ implementation
            A_LSR,
            A_LSRV,
            A_MOV,
-           A_MOVK,
            A_MOVN,
            A_MOVZ,
            A_MSUB,

compiler/aarch64/agcpugas.pas

@@ -41,10 +41,12 @@ unit agcpugas;
 
       TAArch64Assembler=class(TGNUassembler)
         constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
+        function MakeCmdLine: TCmdStr; override;
       end;
 
       TAArch64AppleAssembler=class(TAppleGNUassembler)
         constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
+        function MakeCmdLine: TCmdStr; override;
       end;
 
       TAArch64ClangGASAssembler=class(TAArch64Assembler)
@@ -53,6 +55,7 @@ unit agcpugas;
       protected
         function sectionflags(secflags:TSectionFlags):string;override;
       public
+        function MakeCmdLine: TCmdStr; override;
         procedure WriteAsmList; override;
       end;
 
@@ -65,7 +68,26 @@ unit agcpugas;
     const
       cputype_to_gas_march : array[tcputype] of string = (
         '', // cpu_none
-        'armv8'
+        '', // armv8 is not accepted by GNU assembler
+        'armv8-a',
+        'armv8.1-a',
+        'armv8.2-a',
+        'armv8.3-a',
+        'armv8.4-a',
+        'armv8.5-a',
+        'armv8.6-a'
+      );
+
+      cputype_to_clang_march : array[tcputype] of string = (
+        '', // cpu_none
+        'armv8',
+        'armv8-a',
+        'armv8.1-a',
+        'armv8.2-a',
+        'armv8.3-a',
+        'armv8.4-a',
+        'armv8.5-a',
+        'armv8.6-a'
       );
 
   implementation
@@ -87,6 +109,15 @@ unit agcpugas;
         InstrWriter := TAArch64InstrWriter.create(self);
       end;
 
+    function TAArch64Assembler.MakeCmdLine: TCmdStr;
+      begin
+        result:=inherited MakeCmdLine;
+        if cputype_to_gas_march[current_settings.cputype] <> '' then
+	  Replace(result,'$MARCHOPT','-march='+cputype_to_gas_march[current_settings.cputype])
+        else
+          Replace(result,'$MARCHOPT','');
+      end;
+
 {****************************************************************************}
 {                      Apple AArch64 Assembler writer                        }
 {****************************************************************************}
@@ -98,10 +129,24 @@ unit agcpugas;
       end;
 
 
+    function TAArch64AppleAssembler.MakeCmdLine: TCmdStr;
+      begin
+        result:=inherited MakeCmdLine;
+        if cputype_to_gas_march[current_settings.cputype] <> '' then
+	  Replace(result,'$MARCHOPT','-march='+cputype_to_gas_march[current_settings.cputype])
+        else
+          Replace(result,'$MARCHOPT','');
+      end;
+
 {****************************************************************************}
 {                      CLang AArch64 Assembler writer                        }
 {****************************************************************************}
 
+    function TAArch64ClangGASAssembler.MakeCmdLine: TCmdStr;
+      begin
+        result:=inherited MakeCmdLine;
+      end;
+
     procedure TAArch64ClangGASAssembler.TransformSEHDirectives(list:TAsmList);
 
       function convert_unwinddata(list:tasmlist):tdynamicarray;
@@ -766,8 +811,8 @@ unit agcpugas;
             id     : as_gas;
             idtxt  : 'AS';
             asmbin : 'as';
-            asmcmd : '-o $OBJ $EXTRAOPT $ASM';
-            supported_targets : [system_aarch64_linux,system_aarch64_android];
+            asmcmd : '-o $OBJ $MARCHOPT $EXTRAOPT $ASM';
+            supported_targets : [system_aarch64_freebsd,system_aarch64_linux,system_aarch64_android];
             flags : [af_needar,af_smartlink_sections];
             labelprefix : '.L';
             labelmaxlen : -1;
@@ -780,9 +825,9 @@ unit agcpugas;
             id     : as_clang_asdarwin;
             idtxt  : 'CLANG';
             asmbin : 'clang';
-            asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $EXTRAOPT -x assembler $ASM';
+            asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $MARCHOPT $EXTRAOPT -x assembler $ASM';
             supported_targets : [system_aarch64_ios,system_aarch64_darwin];
-            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm];
+            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm,af_supports_hlcfi];
             labelprefix : 'L';
             labelmaxlen : -1;
             comment : '# ';
@@ -792,11 +837,11 @@ unit agcpugas;
        as_aarch64_clang_gas_info : tasminfo =
           (
             id     : as_clang_gas;
-            idtxt  : 'CLANG';
+            idtxt  : 'AS-CLANG';
             asmbin : 'clang';
-            asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $EXTRAOPT -x assembler $ASM';
+            asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $MARCHOPT $EXTRAOPT -x assembler $ASM';
             supported_targets : [system_aarch64_win64];
-            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm];
+            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm,af_supports_hlcfi];
             labelprefix : '.L';
             labelmaxlen : -1;
             comment : '// ';

compiler/aarch64/aoptcpu.pas

@@ -44,6 +44,10 @@ Interface
         function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;override;
         function InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;override;
         function LookForPostindexedPattern(var p : tai) : boolean;
+      public
+        { With these routines, there's optimisation code that's general for all ARM platforms }
+        function OptPass1LDR(var p: tai): Boolean; override;
+        function OptPass1STR(var p: tai): Boolean; override;
       private
         function RemoveSuperfluousFMov(const p: tai; movp: tai; const optimizer: string): boolean;
         function OptPass1Shift(var p: tai): boolean;
@@ -199,9 +203,9 @@ Implementation
         not(RegModifiedBetween(taicpu(hp1).oper[2]^.reg,p,hp1)) then
         begin
           if taicpu(p).opcode = A_LDR then
-            DebugMsg('Peephole LdrAdd/Sub2Ldr Postindex done', p)
+            DebugMsg(SPeepholeOptimization + 'LdrAdd/Sub2Ldr Postindex done', p)
           else
-            DebugMsg('Peephole StrAdd/Sub2Str Postindex done', p);
+            DebugMsg(SPeepholeOptimization + 'StrAdd/Sub2Str Postindex done', p);
 
           taicpu(p).oper[1]^.ref^.addressmode:=AM_POSTINDEXED;
           if taicpu(hp1).opcode=A_ADD then
@@ -244,7 +248,7 @@ Implementation
           dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(movp.Next));
           if assigned(dealloc) then
             begin
-              DebugMsg('Peephole '+optimizer+' removed superfluous vmov', movp);
+              DebugMsg(SPeepholeOptimization + optimizer+' removed superfluous vmov', movp);
               result:=true;
 
               { taicpu(p).oper[0]^.reg is not used anymore, try to find its allocation
@@ -291,6 +295,24 @@ Implementation
     end;
 
 
+  function TCpuAsmOptimizer.OptPass1LDR(var p: tai): Boolean;
+    begin
+      Result := False;
+      if inherited OptPass1LDR(p) or
+        LookForPostindexedPattern(p) then
+        Exit(True);
+    end;
+
+
+  function TCpuAsmOptimizer.OptPass1STR(var p: tai): Boolean;
+    begin
+      Result := False;
+      if inherited OptPass1STR(p) or
+        LookForPostindexedPattern(p) then
+        Exit(True);
+    end;
+
+
   function TCpuAsmOptimizer.OptPass1Shift(var p : tai): boolean;
     var
       hp1,hp2: tai;
@@ -379,15 +401,23 @@ Implementation
                          taicpu(hp1).oper[0]^.reg, taicpu(p).oper[1]^.reg,
                          shifterop);
 
+                { Make sure the register used in the shifting is tracked all
+                  the way through, otherwise it may become deallocated while
+                  it's still live and cause incorrect optimisations later }
+                if (taicpu(hp1).oper[0]^.reg <> taicpu(p).oper[1]^.reg) then
+                  begin
+                    TransferUsedRegs(TmpUsedRegs);
+                    UpdateUsedRegs(TmpUsedRegs, tai(p.Next));
+                    ALlocRegBetween(taicpu(p).oper[1]^.reg, p, hp1, TmpUsedRegs);
+                  end;
+
                 taicpu(hp2).fileinfo:=taicpu(hp1).fileinfo;
                 asml.insertbefore(hp2, hp1);
-                GetNextInstruction(p, hp2);
-                asml.remove(p);
-                asml.remove(hp1);
-                p.free;
-                hp1.free;
-                p:=hp2;
-                DebugMsg('Peephole FoldShiftProcess done', p);
+
+                RemoveInstruction(hp1);
+                RemoveCurrentp(p);
+
+                DebugMsg(SPeepholeOptimization + 'FoldShiftProcess done', hp2);
                 Result:=true;
                 break;
               end;
@@ -480,7 +510,7 @@ Implementation
           hp3.free;
           hp4.free;
           p:=hp2;
-          DebugMsg('Peephole Bl2B done', p);
+          DebugMsg(SPeepholeOptimization + 'Bl2B done', p);
           Result:=true;
         end;
     end;
@@ -495,7 +525,7 @@ Implementation
        (taicpu(p).oppostfix=PF_None) then
        begin
          RemoveCurrentP(p);
-         DebugMsg('Peephole Mov2None done', p);
+         DebugMsg(SPeepholeOptimization + 'Mov2None done', p);
          Result:=true;
        end
 
@@ -661,9 +691,9 @@ Implementation
                                 }
                                 taicpu(p).opcode := TargetOpcode;
                                 if TargetOpcode = A_STP then
-                                  DebugMsg('Peephole Optimization: StrStr2Stp', p)
+                                  DebugMsg(SPeepholeOptimization + 'StrStr2Stp', p)
                                 else
-                                  DebugMsg('Peephole Optimization: LdrLdr2Ldp', p);
+                                  DebugMsg(SPeepholeOptimization + 'LdrLdr2Ldp', p);
                                 taicpu(p).ops := 3;
                                 taicpu(p).loadref(2, taicpu(p).oper[1]^.ref^);
                                 taicpu(p).loadreg(1, taicpu(hp1).oper[0]^.reg);
@@ -687,9 +717,9 @@ Implementation
                                 }
                                 taicpu(p).opcode := TargetOpcode;
                                 if TargetOpcode = A_STP then
-                                  DebugMsg('Peephole Optimization: StrStr2Stp (reverse)', p)
+                                  DebugMsg(SPeepholeOptimization + 'StrStr2Stp (reverse)', p)
                                 else
-                                  DebugMsg('Peephole Optimization: LdrLdr2Ldp (reverse)', p);
+                                  DebugMsg(SPeepholeOptimization + 'LdrLdr2Ldp (reverse)', p);
                                 taicpu(p).ops := 3;
                                 taicpu(p).loadref(2, taicpu(hp1).oper[1]^.ref^);
                                 taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
@@ -744,7 +774,7 @@ Implementation
           p.free;
           hp1.free;
           p:=hp2;
-          DebugMsg('Peephole CMPB.E/NE2CBNZ/CBZ done', p);
+          DebugMsg(SPeepholeOptimization + 'CMPB.E/NE2CBNZ/CBZ done', p);
           Result:=true;
         end;
     end;
@@ -756,9 +786,10 @@ Implementation
       if p.typ=ait_instruction then
         begin
           case taicpu(p).opcode of
-            A_LDR,
+            A_LDR:
+              Result:=OptPass1LDR(p);
             A_STR:
-              Result:=LookForPostindexedPattern(p);
+              Result:=OptPass1STR(p);
             A_MOV:
               Result:=OptPass1Mov(p);
             A_STP:
@@ -770,6 +801,7 @@ Implementation
               Result:=OptPass1Shift(p);
             A_AND:
               Result:=OptPass1And(p);
+            A_CSEL,
             A_ADD,
             A_ADC,
             A_SUB,

compiler/aarch64/cgcpu.pas

@@ -34,6 +34,9 @@ interface
        rgcpu;
 
     type
+
+      { tcgaarch64 }
+
       tcgaarch64=class(tcg)
        protected
         { changes register size without adding register allocation info }
@@ -92,6 +95,7 @@ interface
         procedure g_flags2reg(list: TAsmList; size: tcgsize; const f:tresflags; reg: tregister);override;
         procedure g_overflowcheck(list: TAsmList; const loc: tlocation; def: tdef);override;
         procedure g_overflowcheck_loc(list: TAsmList; const loc: tlocation; def: tdef; ovloc: tlocation);override;
+        procedure g_stackpointer_alloc(list: TAsmList; localsize: longint);override;
         procedure g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);override;
         procedure g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean);override;
         procedure g_maybe_got_init(list: TAsmList); override;
@@ -120,6 +124,7 @@ interface
         C_LT,C_GE,C_LE,C_NE,C_LS,C_CC,C_CS,C_HI
       );
 
+      winstackpagesize = 4096;
 
 implementation
 
@@ -583,13 +588,15 @@ implementation
         opc: tasmop;
         shift: byte;
         so: tshifterop;
-        reginited,doinverted: boolean;
+        reginited,doinverted,extendedsize: boolean;
         manipulated_a: tcgint;
         leftover_a: word;
       begin
 {$ifdef extdebug}
-        list.concat(tai_comment.Create(strpnew('Generating constant ' + tostr(a))));
+        list.concat(tai_comment.Create(strpnew('Generating constant ' + tostr(a) + ' / $' + hexstr(a, 16))));
 {$endif extdebug}
+        extendedsize := (size in [OS_64,OS_S64]);
+
         case a of
           { Small positive number }
           $0..$FFFF:
@@ -613,19 +620,50 @@ implementation
             end;
           else
             begin
+              if not extendedsize then
+                { Mostly so programmers don't get confused when they view the disassembly and
+                  'a' is sign-extended to 64-bit, say, but also avoids potential problems with
+                  third-party assemblers if the number is out of bounds for a given size }
+                a := Cardinal(a);
 
-              if size in [OS_64,OS_S64] then
+              { Check to see if a is a valid shifter constant that can be encoded in ORR as is }
+              if is_shifter_const(a,size) then
+                begin
+                  { Use synthetic "MOV" instruction instead of "ORR reg,wzr,#a" (an alias),
+                    since AArch64 conventions prefer this, and it's clearer in the
+                    disassembly }
+                  list.concat(taicpu.op_reg_const(A_MOV,reg,a));
+                  Exit;
+                end;
+
+              { If the value of a fits into 32 bits, it's fastest to use movz/movk regardless }
+              if extendedsize and ((a shr 32) <> 0) then
                 begin
-                  { Check to see if a is a valid shifter constant that can be encoded in ORR as is }
-                  if is_shifter_const(a,size) then
+                  { This determines whether this write can be performed with an ORR followed by MOVK
+                    by copying the 3nd word to the 1st word for the ORR constant, then overwriting
+                    the 1st word.  The alternative would require 4 instructions.  This sequence is
+                    common when division reciprocals are calculated (e.g. 3 produces AAAAAAAAAAAAAAAB). }
+                  leftover_a := word(a and $FFFF);
+                  manipulated_a := (a and $FFFFFFFFFFFF0000) or ((a shr 32) and $FFFF);
+                  { if manipulated_a = a, don't check, because is_shifter_const was already
+                    called for a and it returned False.  Reduces processing time. [Kit] }
+                  if (manipulated_a <> a) and is_shifter_const(manipulated_a, OS_64) then
                     begin
-                      list.concat(taicpu.op_reg_reg_const(A_ORR,reg,makeregsize(NR_XZR,size),a));
+                      { Encode value as:
+                          orr  reg,xzr,manipulated_a
+                          movk reg,#(leftover_a)
+
+                        Use "orr" instead of "mov" here for the assembly dump so it better
+                        implies that something special is happening with the number arrangement.
+                      }
+                      list.concat(taicpu.op_reg_reg_const(A_ORR, reg, NR_XZR, manipulated_a));
+                      list.concat(taicpu.op_reg_const(A_MOVK, reg, leftover_a));
                       Exit;
                     end;
 
-                  { This determines whether this write can be peformed with an ORR followed by MOVK
+                  { This determines whether this write can be performed with an ORR followed by MOVK
                     by copying the 2nd word to the 4th word for the ORR constant, then overwriting
-                    the 4th word (unless the word is.  The alternative would require 3 instructions }
+                    the 4th word.  The alternative would require 3 instructions }
                   leftover_a := word(a shr 48);
                   manipulated_a := (a and $0000FFFFFFFFFFFF);
 
@@ -642,16 +680,20 @@ implementation
                   manipulated_a := manipulated_a or (((a shr 16) and $FFFF) shl 48);
                   { if manipulated_a = a, don't check, because is_shifter_const was already
                     called for a and it returned False.  Reduces processing time. [Kit] }
-                  if (manipulated_a <> a) and is_shifter_const(manipulated_a, size) then
+                  if (manipulated_a <> a) and is_shifter_const(manipulated_a, OS_64) then
                     begin
-                      list.concat(taicpu.op_reg_reg_const(A_ORR, reg, makeregsize(NR_XZR, size), manipulated_a));
-                      if (leftover_a <> 0) then
-                        begin
-                          shifterop_reset(so);
-                          so.shiftmode := SM_LSL;
-                          so.shiftimm := 48;
-                          list.concat(taicpu.op_reg_const_shifterop(A_MOVK, reg, leftover_a, so));
-                        end;
+                      { Encode value as:
+                          orr  reg,xzr,manipulated_a
+                          movk reg,#(leftover_a),lsl #48
+
+                        Use "orr" instead of "mov" here for the assembly dump so it better
+                        implies that something special is happening with the number arrangement.
+                      }
+                      list.concat(taicpu.op_reg_reg_const(A_ORR, reg, NR_XZR, manipulated_a));
+                      shifterop_reset(so);
+                      so.shiftmode := SM_LSL;
+                      so.shiftimm := 48;
+                      list.concat(taicpu.op_reg_const_shifterop(A_MOVK, reg, leftover_a, so));
                       Exit;
                     end;
 
@@ -664,7 +706,7 @@ implementation
                           stored as the first 16 bits followed by a shifter constant }
                         case a of
                           TCgInt($FFFF0000FFFF0000)..TCgInt($FFFF0000FFFFFFFF):
-                            doinverted := False
+                            doinverted := False;
                           else
                             begin
                               doinverted := True;
@@ -678,10 +720,7 @@ implementation
                   end;
                 end
               else
-                begin
-                  a:=cardinal(a);
-                  doinverted:=False;
-                end;
+                doinverted:=False;
             end;
         end;
 
@@ -808,7 +847,7 @@ implementation
               reg:=makeregsize(reg,OS_64);
             fromsize:=tosize;
           end;
-        if (ref.alignment<>0) and
+        if not(target_info.system=system_aarch64_darwin) and (ref.alignment<>0) and
            (ref.alignment<tcgsize2size[tosize]) then
           begin
             a_load_reg_ref_unaligned(list,fromsize,tosize,reg,ref);
@@ -857,7 +896,7 @@ implementation
         }
         if fromsize in [OS_8,OS_16,OS_32] then
           reg:=makeregsize(reg,OS_32);
-        if (ref.alignment<>0) and
+        if not(target_info.system=system_aarch64_darwin) and (ref.alignment<>0) and
            (ref.alignment<tcgsize2size[fromsize]) then
           begin
             a_load_ref_reg_unaligned(list,fromsize,tosize,ref,reg);
@@ -1335,8 +1374,13 @@ implementation
           OP_NEG,
           OP_NOT:
             begin
-              list.concat(taicpu.op_reg_reg(TOpCG2AsmOpReg[op],dst,src));
-              maybeadjustresult(list,op,size,dst);
+              if (op=OP_NOT) and (size in [OS_8,OS_S8]) then
+                list.concat(taicpu.op_reg_reg_const(A_EOR,dst,src,255))
+              else
+                begin
+                  list.concat(taicpu.op_reg_reg(TOpCG2AsmOpReg[op],dst,src));
+                  maybeadjustresult(list,op,size,dst);
+                end;
             end
           else
             a_op_reg_reg_reg(list,op,size,src,dst,dst);
@@ -1770,6 +1814,55 @@ implementation
       end;
 
 
+    procedure tcgaarch64.g_stackpointer_alloc(list : TAsmList;localsize : longint);
+      var
+        href : treference;
+        i : integer;
+        again : tasmlabel;
+      begin
+        if localsize>0 then
+         begin
+           { windows guards only a few pages for stack growing,
+             so we have to access every page first              }
+           if (target_info.system=system_aarch64_win64) and
+              (localsize>=winstackpagesize) then
+             begin
+               if localsize div winstackpagesize<=4 then
+                 begin
+                   handle_reg_imm12_reg(list,A_SUB,OS_ADDR,NR_SP,localsize,NR_SP,NR_IP0,false,true);
+                   for i:=1 to localsize div winstackpagesize do
+                     begin
+                       reference_reset_base(href,NR_SP,localsize-i*winstackpagesize+4,ctempposinvalid,4,[]);
+                       list.concat(Taicpu.op_reg_ref(A_STR,NR_WZR,href));
+                     end;
+                   reference_reset_base(href,NR_SP,0,ctempposinvalid,4,[]);
+                   list.concat(Taicpu.op_reg_ref(A_STR,NR_WZR,href));
+                 end
+               else
+                 begin
+                    current_asmdata.getjumplabel(again);
+                    getcpuregister(list,NR_IP0);
+                    a_load_const_reg(list,OS_ADDR,localsize div winstackpagesize,NR_IP0);
+                    a_label(list,again);
+                    handle_reg_imm12_reg(list,A_SUB,OS_ADDR,NR_SP,winstackpagesize,NR_SP,NR_IP1,false,true);
+                    reference_reset_base(href,NR_SP,0,ctempposinvalid,4,[]);
+                    list.concat(Taicpu.op_reg_ref(A_STR,NR_WZR,href));
+                    list.concat(setoppostfix(Taicpu.op_reg_reg_const(A_SUB,NR_IP0,NR_IP0,1),PF_S));
+                    a_jmp_cond(list,OC_NE,again);
+                    handle_reg_imm12_reg(list,A_SUB,OS_ADDR,NR_SP,localsize mod winstackpagesize,NR_SP,NR_IP1,false,true);
+                    ungetcpuregister(list,NR_IP0);
+                 end
+             end
+           else
+             begin
+               handle_reg_imm12_reg(list,A_SUB,OS_ADDR,NR_SP,localsize,NR_SP,NR_IP0,false,true);
+               if target_info.system=system_aarch64_win64 then
+                 list.concat(cai_seh_directive.create_offset(ash_stackalloc,localsize));
+             end;
+         end;
+      end;
+
+
     procedure tcgaarch64.g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);
       var
         hitem: tlinkedlistitem;
@@ -1831,9 +1924,7 @@ implementation
               begin
                 localsize:=align(localsize,16);
                 current_procinfo.final_localsize:=localsize;
-                handle_reg_imm12_reg(list,A_SUB,OS_ADDR,NR_SP,localsize,NR_SP,NR_IP0,false,true);
-                if target_info.system=system_aarch64_win64 then
-                  list.concat(cai_seh_directive.create_offset(ash_stackalloc,localsize));
+                g_stackpointer_alloc(list,localsize);
               end;
             { By default, we use the frame pointer to access parameters passed via
               the stack and the stack pointer to address local variables and temps

compiler/aarch64/cpuinfo.pas

@@ -37,7 +37,14 @@ Type
    { possible supported processors for this target }
    tcputype =
       (cpu_none,
-       cpu_armv8
+       cpu_armv8,
+       cpu_armv8a,
+       cpu_armv81a,
+       cpu_armv82a,
+       cpu_armv83a,
+       cpu_armv84a,
+       cpu_armv85a,
+       cpu_armv86a
       );
 
 Type
@@ -97,8 +104,15 @@ Const
      pocall_interrupt
    ];
 
-   cputypestr : array[tcputype] of string[8] = ('',
-     'ARMV8'
+   cputypestr : array[tcputype] of string[9] = ('',
+     'ARMV8',
+     'ARMV8-A',
+     'ARMV8.1-A',
+     'ARMV8.2-A',
+     'ARMV8.3-A',
+     'ARMV8.4-A',
+     'ARMV8.5-A',
+     'ARMV8.6-A'
    );
 
    fputypestr : array[tfputype] of string[9] = ('',
@@ -121,6 +135,33 @@ Const
    level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
    level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
 
+type
+   tcpuflags =
+     (CPUAARCH64_HAS_LSE       { CPU supports Large System Extensions }
+     );
+
+   tfpuflags =
+     (CPUAARCH64_HAS_VFP       { CPU supports VFP }
+     );
+
+const
+   cpu_capabilities : array[tcputype] of set of tcpuflags =
+     ( { cpu_none      } [],
+       { cpu_armv8     } [],
+       { cpu_armv8a    } [],
+       { cpu_armv81a   } [CPUAARCH64_HAS_LSE],
+       { cpu_armv82a   } [CPUAARCH64_HAS_LSE],
+       { cpu_armv83a   } [CPUAARCH64_HAS_LSE],
+       { cpu_armv84a   } [CPUAARCH64_HAS_LSE],
+       { cpu_armv85a   } [CPUAARCH64_HAS_LSE],
+       { cpu_armv86a   } [CPUAARCH64_HAS_LSE]
+     );
+
+   fpu_capabilities : array[tfputype] of set of tfpuflags =
+     ( { fpu_none         } [],
+       { fpu_vfp          } [CPUAARCH64_HAS_VFP]
+     );
+
 Implementation
 
 end.

compiler/aarch64/cputarg.pas

@@ -35,6 +35,9 @@ implementation
              Targets
 **************************************}
 
+    {$ifndef NOTARGETBSD}
+      ,t_bsd
+    {$endif}
     {$ifndef NOTARGETLINUX}
       ,t_linux
     {$endif}

compiler/aarch64/hlcgcpu.pas

@@ -210,7 +210,8 @@ implementation
       if slopt in [SL_SETZERO,SL_SETMAX] then
         inherited
       else if not(sreg.bitlen in [32,64]) or
-              (sreg.startbit<>0) then
+              (sreg.startbit<>0) or
+              (getsubreg(fromreg)<getsubreg(sreg.subsetreg)) then
         begin
           makeregssamesize(list,def_cgsize(fromsize),sreg.subsetregsize,fromreg,sreg.subsetreg,fromreg,toreg);
           list.concat(taicpu.op_reg_reg_const_const(A_BFI,toreg,fromreg,sreg.startbit,sreg.bitlen))

compiler/aarch64/ncpuinl.pas

@@ -1,7 +1,7 @@
 {
     Copyright (c) 1998-2002 by Florian Klaempfl
 
-    Generates ARM inline nodes
+    Generates AAarch64 inline nodes
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -35,6 +35,8 @@ interface
         function first_sqrt_real: tnode; override;
         function first_round_real: tnode; override;
         function first_trunc_real: tnode; override;
+        function first_int_real: tnode; override;
+        function first_frac_real: tnode; override;
         function first_fma : tnode; override;
         procedure second_abs_real; override;
         procedure second_sqr_real; override;
@@ -42,6 +44,8 @@ interface
         procedure second_abs_long; override;
         procedure second_round_real; override;
         procedure second_trunc_real; override;
+        procedure second_int_real; override;
+        procedure second_frac_real; override;
         procedure second_get_frame; override;
         procedure second_fma; override;
         procedure second_prefetch; override;
@@ -108,16 +112,31 @@ implementation
       end;
 
 
-     function taarch64inlinenode.first_fma : tnode;
-       begin
-         if ((is_double(resultdef)) or (is_single(resultdef))) then
-           begin
-             expectloc:=LOC_MMREGISTER;
-             Result:=nil;
-           end
-         else
-           Result:=inherited first_fma;
-       end;
+    function taarch64inlinenode.first_int_real : tnode;
+      begin
+        expectloc:=LOC_MMREGISTER;
+        result:=nil;
+      end;
+
+
+    function taarch64inlinenode.first_frac_real : tnode;
+      begin
+        expectloc:=LOC_MMREGISTER;
+        result:=nil;
+      end;
+
+
+    function taarch64inlinenode.first_fma : tnode;
+      begin
+        if ((is_double(resultdef)) or (is_single(resultdef))) then
+          begin
+            expectloc:=LOC_MMREGISTER;
+            Result:=nil;
+          end
+        else
+          Result:=inherited first_fma;
+     end;
+
 
     procedure taarch64inlinenode.second_abs_real;
       begin
@@ -187,6 +206,33 @@ implementation
       end;
 
 
+    procedure taarch64inlinenode.second_int_real;
+      var
+        hreg: tregister;
+      begin
+        secondpass(left);
+        hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
+        location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
+        location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
+        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FRINTZ,location.register,left.location.register));
+        cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
+      end;
+
+
+    procedure taarch64inlinenode.second_frac_real;
+      var
+        hreg: tregister;
+      begin
+        secondpass(left);
+        hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
+        location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
+        location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
+        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FRINTZ,location.register,left.location.register));
+        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_FSUB,location.register,left.location.register,location.register));
+        cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
+      end;
+
+
     procedure taarch64inlinenode.second_get_frame;
       begin
         location_reset(location,LOC_CREGISTER,OS_ADDR);

compiler/aarch64/ncpumat.pas

@@ -71,20 +71,35 @@ implementation
       var
          op         : tasmop;
          tmpreg,
+         zeroreg,
          numerator,
          divider,
+         largernumreg,
+         largerresreg,
          resultreg  : tregister;
-         hl : tasmlabel;
+         hl         : tasmlabel;
          overflowloc: tlocation;
-         power: longint;
+         power      : longint;
+         opsize     : tcgsize;
+
+         dividend   : Int64;
+         high_bit,
+         reciprocal : QWord;
+         { Just to save on stack space and the like }
+         reciprocal_signed : Int64 absolute reciprocal;
+
+         expandword,
+         magic_add  : Boolean;
+         shift      : byte;
+
+         shifterop  : tshifterop;
+         hp         : taicpu;
 
        procedure genOrdConstNodeDiv;
          var
            helper1, helper2: TRegister;
            so: tshifterop;
-           opsize: TCgSize;
          begin
-           opsize:=def_cgsize(resultdef);
            if tordconstnode(right).value=0 then
              internalerror(2020021601)
            else if tordconstnode(right).value=1 then
@@ -98,7 +113,7 @@ implementation
                current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_NEG,
                  resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S))));
              end
-           else if ispowerof2(tordconstnode(right).value,power) then
+           else if isabspowerof2(tordconstnode(right).value,power) then
              begin
                if (is_signed(right.resultdef)) then
                  begin
@@ -115,98 +130,318 @@ implementation
                     so.shiftimm:=resultdef.size*8-power;
                     current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
                     cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,def_cgsize(resultdef),power,helper2,resultreg);
+
+                    if (tordconstnode(right).value < 0) then
+                      { Invert the result }
+                      current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NEG,resultreg,resultreg));
                   end
-               else
-                 cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,opsize,power,numerator,resultreg)
+                else
+                  cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,opsize,power,numerator,resultreg)
              end
            else
-             { Everything else is handled in the generic code }
-             cg.g_div_const_reg_reg(current_asmdata.CurrAsmList,opsize,
-               tordconstnode(right).value.svalue,numerator,resultreg);
+             { Generic division }
+             begin
+               if is_signed(left.resultdef) then
+                 op:=A_SDIV
+               else
+                 op:=A_UDIV;
+
+               { If we didn't acquire the original divisor earlier, grab it now }
+               if divider = NR_NO then
+                 begin
+                   divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                   cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
+                 end;
+
+               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,divider));
+             end;
          end;
 
-      begin
-       secondpass(left);
-       secondpass(right);
-       { avoid warning }
-       divider:=NR_NO;
-
-       { set result location }
-       location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
-       location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
-       resultreg:=location.register;
-
-       { put numerator in register }
-       hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
-       numerator:=left.location.register;
-
-       if (right.nodetype=ordconstn) and
-          ((tordconstnode(right).value=1) or
-           (tordconstnode(right).value=int64(-1)) or
-           (tordconstnode(right).value=0) or
-           ispowerof2(tordconstnode(right).value,power)) then
+       procedure genOverflowCheck;
          begin
-           genOrdConstNodeDiv;
-           if nodetype=modn then
+           { in case of overflow checking, also check for low(int64) div (-1)
+             (no hardware support for this either) }
+           if (cs_check_overflow in current_settings.localswitches) and
+              is_signed(left.resultdef) and
+              ((right.nodetype<>ordconstn) or
+               (tordconstnode(right).value=-1)) then
              begin
-               divider:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
-               cg.a_load_const_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),int64(tordconstnode(right).value),divider);
+               { num=ffff... and div=8000... <=>
+                 num xor not(div xor 8000...) = 0
+                 (and we have the "eon" operation, which performs "xor not(...)" }
+               tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
+               hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,low(int64),numerator,tmpreg);
+               current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_EON,
+                 tmpreg,numerator,tmpreg));
+               current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,tmpreg,0));
+               { now the zero/equal flag is set in case we divided low(int64) by
+                 (-1) }
+               location_reset(overflowloc,LOC_FLAGS,OS_NO);
+               overflowloc.resflags:=F_EQ;
+               cg.g_overflowcheck_loc(current_asmdata.CurrAsmList,location,resultdef,overflowloc);
              end;
-         end
-       else
-         begin
-           { load divider in a register }
-           hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
-           divider:=right.location.register;
-
-           { start division }
-           if is_signed(left.resultdef) then
-             op:=A_SDIV
-           else
-             op:=A_UDIV;
-           current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,numerator,divider));
          end;
 
-       { no divide-by-zero detection available in hardware, emulate (if it's a
-         constant, this will have been detected earlier already) }
-       if (right.nodetype<>ordconstn) then
-         begin
-           current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,
-             right.location.register,0));
+      begin
+        secondpass(left);
+        secondpass(right);
+        { avoid warning }
+        divider := NR_NO;
+        largernumreg := NR_NO;
+        expandword := False;
 
-           current_asmdata.getjumplabel(hl);
-           current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_B,C_NE,hl));
-           cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO',false);
-           cg.a_label(current_asmdata.CurrAsmList,hl);
-         end;
+        opsize := def_cgsize(resultdef);
 
-       { in case of overflow checking, also check for low(int64) div (-1)
-         (no hardware support for this either) }
-       if (cs_check_overflow in current_settings.localswitches) and
-          is_signed(left.resultdef) and
-          ((right.nodetype<>ordconstn) or
-           (tordconstnode(right).value=-1)) then
-         begin
-           { num=ffff... and div=8000... <=>
-             num xor not(div xor 8000...) = 0
-             (and we have the "eon" operation, which performs "xor not(...)" }
-           tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
-           hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,low(int64),left.location.register,tmpreg);
-           current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_EON,
-             tmpreg,left.location.register,tmpreg));
-           current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,tmpreg,0));
-           { now the zero/equal flag is set in case we divided low(int64) by
-             (-1) }
-           location_reset(overflowloc,LOC_FLAGS,OS_NO);
-           overflowloc.resflags:=F_EQ;
-           cg.g_overflowcheck_loc(current_asmdata.CurrAsmList,location,resultdef,overflowloc);
-         end;
+        { set result location }
+        location_reset(location,LOC_REGISTER,opsize);
+        location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+        resultreg:=location.register;
 
-       { in case of modulo, multiply result again by the divider and subtract
-         from the numerator }
-       if nodetype=modn then
-         current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
-           resultreg,divider,numerator));
+        { put numerator in register }
+        hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
+        numerator:=left.location.register;
+
+        if (right.nodetype=ordconstn) then
+          begin
+            { If optimising for size, just use regular division operations }
+            if (cs_opt_size in current_settings.optimizerswitches) or
+              ((tordconstnode(right).value=1) or
+              (tordconstnode(right).value=int64(-1)) or
+              isabspowerof2(tordconstnode(right).value,power)) then
+              begin
+
+                { Store divisor for later (and executed at the same time as the multiplication) }
+                if (nodetype=modn) then
+                  begin
+                    if (tordconstnode(right).value = 1) or (tordconstnode(right).value = int64(-1)) then
+                      begin
+                        { Just evaluates to zero }
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_MOVZ,resultreg, 0));
+                        Exit;
+                      end
+                    { "not cs_opt_size" saves from checking the value of the divisor again
+                      (if cs_opt_size is not set, then the divisor is a power of 2) }
+                    else if not (cs_opt_size in current_settings.optimizerswitches) then
+                      begin
+                        divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                        cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
+                      end
+                  end;
+
+                genOrdConstNodeDiv;
+                genOverflowCheck;
+
+                { in case of modulo, multiply result again by the divider and subtract
+                  from the numerator }
+                if (nodetype=modn) then
+                  begin
+                    if ispowerof2(tordconstnode(right).value,power) then
+                      begin
+                        shifterop.shiftmode := SM_LSL;
+                        shifterop.shiftimm := power;
+
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_SUB,resultreg,numerator,resultreg,shifterop));
+                      end
+                    else
+                      current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
+                        resultreg,divider,numerator));
+                  end;
+
+                Exit;
+              end
+            else
+              begin
+                if is_signed(left.resultdef) then
+                  begin
+                    if (nodetype=modn) then { Signed mod doesn't work properly }
+                      begin
+                        divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                        cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
+                        genOrdConstNodeDiv;
+                      end
+                    else
+                      begin
+                        { Read signed value to avoid Internal Error 200706094 }
+                        dividend := tordconstnode(right).value.svalue;
+
+                        calc_divconst_magic_signed(resultdef.size * 8, dividend, reciprocal_signed, shift);
+                        cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, reciprocal_signed, resultreg);
+
+                        { SMULH is only available for the full 64-bit registers }
+                        if opsize in [OS_64, OS_S64] then
+                          begin
+                            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SMULH,resultreg,resultreg,numerator));
+                            largerresreg := resultreg;
+                          end
+                        else
+                          begin
+                            largerresreg := newreg(getregtype(resultreg), getsupreg(resultreg), R_SUBWHOLE);
+                            largernumreg := newreg(getregtype(numerator), getsupreg(numerator), R_SUBWHOLE);
+                            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MUL,largerresreg,largerresreg,largernumreg));
+                            expandword := True; { Merge the shift operation with something below }
+                          end;
+
+                        { Store divisor for later (and executed at the same time as the multiplication) }
+                        if nodetype=modn then
+                          begin
+                            divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                            cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,dividend,divider);
+                          end;
+
+                        { add or subtract dividend }
+                        if (dividend > 0) and (reciprocal_signed < 0) then
+                          begin
+                            if expandword then
+                              begin
+                                shifterop.shiftmode := SM_ASR;
+                                shifterop.shiftimm := 32;
+                                expandword := False;
+                                current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,largerresreg,largernumreg,largerresreg,shifterop));
+                              end
+                            else
+                              current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ADD,resultreg,resultreg,numerator));
+                          end
+                        else if (dividend < 0) and (reciprocal_signed > 0) then
+                          begin
+                            if expandword then
+                              begin
+                                { We can't append LSR to the SUB below because it's on the wrong operand }
+                                expandword := False;
+                                current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,largerresreg,largerresreg,32));
+                              end;
+
+                            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,resultreg,resultreg,numerator));
+                          end
+                        else if expandword then
+                          Inc(shift,32);
+
+                        { shift if necessary }
+                        if (shift <> 0) then
+                          begin
+                            if expandword then
+                              current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,largerresreg,largerresreg,shift))
+                            else
+                              current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,resultreg,resultreg,shift));
+                          end;
+
+                        { extract and add the sign bit }
+                        shifterop.shiftmode := SM_LSR;
+                        shifterop.shiftimm := left.resultdef.size*8 - 1;
+
+                        if (dividend < 0) then
+                          current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,resultreg,resultreg,resultreg,shifterop))
+                        else
+                          current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,resultreg,resultreg,numerator,shifterop));
+                      end;
+                  end
+                else
+                  begin
+                    calc_divconst_magic_unsigned(resultdef.size * 8, tordconstnode(right).value, reciprocal, magic_add, shift);
+                    { Add explicit typecast to tcgint type, to avoid range or overflow check }
+                    cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, tcgint(reciprocal), resultreg);
+                    { UMULH is only available for the full 64-bit registers }
+                    if opsize in [OS_64, OS_S64] then
+                      begin
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_UMULH,resultreg,resultreg,numerator));
+                        largerresreg := resultreg;
+                      end
+                    else
+                      begin
+                        largerresreg := newreg(getregtype(resultreg), getsupreg(resultreg), R_SUBWHOLE);
+                        largernumreg := newreg(getregtype(numerator), getsupreg(numerator), R_SUBWHOLE);
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MUL,largerresreg,largerresreg,largernumreg));
+                        expandword := True; { Try to merge the shift operation with something below }
+                      end;
+
+                    { Store divisor for later (and executed at the same time as the multiplication) }
+                    if (nodetype=modn) then
+                      begin
+                        divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                        cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
+                      end;
+
+                    if magic_add then
+                      begin
+                        { We can't append LSR to the ADD below because it would require extending the registers
+                          and interfere with the carry bit }
+                        if expandword then
+                          current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,largerresreg,largerresreg,32));
+
+                        { Add the reciprocal to the high-order word, tracking the carry bit, shift, then
+                          insert the carry bit via CSEL and ORR }
+
+                        if opsize in [OS_64,OS_S64] then
+                          zeroreg := NR_XZR
+                        else
+                          zeroreg := NR_WZR;
+
+                        high_bit := QWord(1) shl ((resultdef.size * 8) - shift);
+
+                        tmpreg := cg.getintregister(current_asmdata.CurrAsmList, opsize);
+                        cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, high_bit, tmpreg);
+
+                        { Generate ADDS instruction }
+                        hp := taicpu.op_reg_reg_reg(A_ADD,resultreg,resultreg,numerator);
+                        hp.oppostfix := PF_S;
+                        current_asmdata.CurrAsmList.concat(hp);
+
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_cond(A_CSEL,tmpreg,tmpreg,zeroreg, C_CS));
+
+                        shifterop.shiftmode := SM_LSR;
+                        shifterop.shiftimm := shift;
+
+                        current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,resultreg,tmpreg,resultreg,shifterop));
+                      end
+                    else if expandword then
+                      { Include the right-shift by 32 to get the high-order DWord }
+                      current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,largerresreg,largerresreg,shift + 32))
+                    else
+                      current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,resultreg,resultreg,shift));
+                  end;
+
+              end;
+
+          end
+        { no divide-by-zero detection available in hardware, emulate (if it's a
+          constant, this will have been detected earlier already) }
+        else
+          begin
+            { load divider in a register }
+            hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
+            divider:=right.location.register;
+
+            { ARM-64 developer guides recommend checking for division by zero conditions
+              AFTER the division, since the check and the division can be done in tandem }
+            if is_signed(left.resultdef) then
+              op:=A_SDIV
+            else
+              op:=A_UDIV;
+
+            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,divider));
+
+            current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,divider,0));
+            current_asmdata.getjumplabel(hl);
+            current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_B,C_NE,hl));
+            cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO',false);
+            cg.a_label(current_asmdata.CurrAsmList,hl);
+          end;
+
+        genOverflowCheck;
+
+        { in case of modulo, multiply result again by the divider and subtract
+          from the numerator }
+        if (nodetype=modn) then
+          begin
+            { If we didn't acquire the original divisor earlier, grab it now }
+            if divider = NR_NO then
+              begin
+                divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
+                cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
+              end;
+
+            current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
+              resultreg,divider,numerator));
+          end;
     end;
 
 

compiler/aarch64/racpugas.pas

@@ -556,6 +556,10 @@ Unit racpugas;
 
 
     function taarch64attreader.ToConditionCode(const hs: string; is_operand: boolean): tasmcond;
+{$push}{$j-}
+      const
+        extracond2str: array[C_HS..C_LO] of string[2] = ('CS','CC');
+{$pop}
       begin
         case actopcode of
           A_CSEL,A_CSINC,A_CSINV,A_CSNEG,A_CSET,A_CSETM,
@@ -568,11 +572,16 @@ Unit racpugas;
                 begin
                   { workaround for DFA bug }
                   result:=low(tasmcond);
-                  for result:=low(tasmcond) to high(tasmcond) do
+                  for result:=low(uppercond2str) to high(uppercond2str) do
                     begin
                       if hs=uppercond2str[result] then
                         exit;
                     end;
+                  for result:=low(extracond2str) to high(extracond2str) do
+                    begin
+                      if hs=extracond2str[result] then
+                        exit;
+                    end;
                 end;
             end;
           else

compiler/aarch64/rgcpu.pas

@@ -1,7 +1,7 @@
 {
     Copyright (c) 1998-2002 by Florian Klaempfl
 
-    This unit implements the SPARC specific class for the register
+    This unit implements the AArch64 specific class for the register
     allocator
 
     This program is free software; you can redistribute it and/or modify
@@ -87,8 +87,8 @@ implementation
           begin
             helplist:=TAsmList.create;
 
-            if getregtype(tempreg)=R_INTREGISTER then
-              hreg:=tempreg
+            if (getregtype(tempreg)=R_INTREGISTER) then
+              hreg:=getregisterinline(helplist,[R_SUBWHOLE])
             else
               hreg:=cg.getaddressregister(helplist);
 
@@ -100,6 +100,8 @@ implementation
             else
               helpins:=spilling_create_store(tempreg,tmpref);
             helplist.concat(helpins);
+            if (getregtype(tempreg)=R_INTREGISTER) then
+              ungetregisterinline(helplist,hreg);
             add_cpu_interferences(helpins);
             list.insertlistafter(pos,helplist);
             helplist.free;

compiler/aasmcnst.pas

@@ -1165,7 +1165,7 @@ implementation
    class function ttai_typedconstbuilder.get_string_symofs(typ: tstringtype; winlikewidestring: boolean): pint;
      begin
        { darwin's linker does not support negative offsets }
-       if not(target_info.system in systems_darwin) and
+       if not(target_info.system in systems_darwin+systems_wasm) and
           { it seems that clang's assembler has a bug with the ADRP instruction... }
           (target_info.system<>system_aarch64_win64) then
          result:=0
@@ -1584,7 +1584,9 @@ implementation
 
    class function ttai_typedconstbuilder.is_smartlink_vectorized_dead_strip: boolean;
      begin
-       result:=tf_smartlink_sections in target_info.flags;
+       result:=(tf_smartlink_sections in target_info.flags) and
+               (not(target_info.system in systems_darwin) or
+                (tf_supports_symbolorderfile in target_info.flags));
      end;
 
 

compiler/aasmtai.pas

@@ -90,6 +90,11 @@ interface
           ait_llvmmetadatanode, (* llvm metadata node: !id = !{type value, ...} *)
           ait_llvmmetadatareftypedconst, { reference to metadata inside a metadata constant }
           ait_llvmmetadatarefoperand, { llvm metadata referece: !metadataname !id }
+{$endif}
+{$ifdef wasm}
+          ait_importexport,
+          ait_local,
+          ait_functype,
 {$endif}
           { SEH directives used in ARM,MIPS and x86_64 COFF targets }
           ait_seh_directive,
@@ -232,6 +237,11 @@ interface
           'llvmmetadata',
           'llvmmetadatareftc',
           'llvmmetadatarefop',
+{$endif}
+{$ifdef wasm}
+          'importexport',
+          'local',
+          'functype',
 {$endif}
           'cfi',
           'seh_directive',
@@ -288,6 +298,11 @@ interface
        ,top_fenceflags
        ,top_roundingmode
 {$endif defined(riscv32) or defined(riscv64)}
+{$ifdef wasm}
+       ,top_functype
+       ,top_single
+       ,top_double
+{$endif wasm}
        );
 
       { kinds of operations that an instruction can perform on an operand }
@@ -341,6 +356,9 @@ interface
                      ait_llvmmetadatareftypedconst,
                      ait_llvmmetadatarefoperand,
 {$endif llvm}
+{$ifdef wasm}
+                     ait_importexport,ait_local,ait_functype,
+{$endif wasm}
                      ait_seh_directive,
                      ait_cfi,
                      ait_eabi_attribute
@@ -384,7 +402,7 @@ interface
         { supported by recent clang-based assemblers for data-in-code  }
         asd_data_region, asd_end_data_region,
         { ARM }
-        asd_thumb_func,asd_code,
+        asd_thumb_func,asd_code,asd_force_thumb,
         { restricts the assembler only to those instructions, which are
           available on the specified CPU; this represents directives such as
           NASM's 'CPU 686' or MASM/TASM's '.686p'. Might not be supported by
@@ -434,6 +452,7 @@ interface
         { ARM }
         'thumb_func',
         'code',
+	'force_thumb',
         'cpu',
         { for the OMF object format }
         'omf_line',
@@ -516,6 +535,11 @@ interface
             top_fenceflags : (fenceflags : TFenceFlags);
             top_roundingmode : (roundingmode : TRoundingMode);
         {$endif defined(riscv32) or defined(riscv64)}
+        {$ifdef wasm}
+            top_functype : (functype: TWasmFuncType);
+            top_single : (sval:single);
+            top_double : (dval:double);
+        {$endif wasm}
         end;
         poper=^toper;
 
@@ -2995,6 +3019,10 @@ implementation
               top_wstring:
                 donewidestring(pwstrval);
 {$endif jvm}
+{$ifdef wasm}
+              top_functype:
+                FreeAndNil(functype);
+{$endif wasm}
               else
                 ;
             end;

compiler/aggas.pas

@@ -1,4 +1,4 @@
-  {
+  {                  f
     Copyright (c) 1998-2006 by the Free Pascal team
 
     This unit implements the generic part of the GNU assembler
@@ -32,7 +32,10 @@ interface
 
     uses
       globtype,globals,
-      aasmbase,aasmtai,aasmdata,aasmcfi,
+      cpubase,aasmbase,aasmtai,aasmdata,aasmcfi,
+{$ifdef wasm}
+      aasmcpu,
+{$endif wasm}
       assemble;
 
     type
@@ -66,6 +69,9 @@ interface
         procedure WriteTree(p:TAsmList);override;
         procedure WriteAsmList;override;
         destructor destroy; override;
+{$ifdef WASM}
+        procedure WriteFuncType(functype: TWasmFuncType);
+{$endif WASM}
        private
         setcount: longint;
         procedure WriteDecodedSleb128(a: int64);
@@ -118,7 +124,7 @@ implementation
 {$ifdef m68k}
       cpuinfo,aasmcpu,
 {$endif m68k}
-      cpubase,objcasm;
+      objcasm;
 
     const
       line_length = 70;
@@ -507,7 +513,8 @@ implementation
          system_i386_OS2,
          system_i386_EMX: ;
          system_m68k_atari, { atari tos/mint GNU AS also doesn't seem to like .section (KB) }
-         system_m68k_amiga: { amiga has old GNU AS (2.14), which blews up from .section (KB) }
+         system_m68k_amiga, { amiga has old GNU AS (2.14), which blews up from .section (KB) }
+         system_m68k_sinclairql: { same story, only ancient GNU tools available (KB) }
            begin
              { ... but vasm is GAS compatible on amiga/atari, and supports named sections }
              if create_smartlink_sections then
@@ -549,6 +556,11 @@ implementation
            begin
              if (atype in [sec_stub]) then
                writer.AsmWrite('.section ');
+           end;
+         system_wasm32_wasi,
+         system_wasm32_embedded:
+           begin
+             writer.AsmWrite('.section ');
            end
          else
            begin
@@ -711,6 +723,37 @@ implementation
       end;
 
 
+{$ifdef WASM}
+    procedure TGNUAssembler.WriteFuncType(functype: TWasmFuncType);
+      var
+        wasm_basic_typ: TWasmBasicType;
+        first: boolean;
+      begin
+        writer.AsmWrite('(');
+        first:=true;
+        for wasm_basic_typ in functype.params do
+          begin
+            if first then
+              first:=false
+            else
+              writer.AsmWrite(',');
+            writer.AsmWrite(gas_wasm_basic_type_str[wasm_basic_typ]);
+          end;
+        writer.AsmWrite(') -> (');
+        first:=true;
+        for wasm_basic_typ in functype.results do
+          begin
+            if first then
+              first:=false
+            else
+              writer.AsmWrite(',');
+            writer.AsmWrite(gas_wasm_basic_type_str[wasm_basic_typ]);
+          end;
+        writer.AsmWrite(')');
+      end;
+{$endif WASM}
+
+
     procedure TGNUAssembler.WriteTree(p:TAsmList);
 
       function needsObject(hp : tai_symbol) : boolean;
@@ -798,6 +841,28 @@ implementation
             end;
         end;
 
+{$ifdef WASM}
+      procedure WriteFuncTypeDirective(hp:tai_functype);
+        begin
+          writer.AsmWrite(#9'.functype'#9);
+          writer.AsmWrite(hp.funcname);
+          writer.AsmWrite(' ');
+          WriteFuncType(hp.functype);
+          writer.AsmLn;
+        end;
+
+
+      procedure WriteImportExport(hp:tai_impexp);
+        var
+          symstypestr: string;
+        begin
+          Str(hp.symstype,symstypestr);
+          writer.AsmWriteLn(asminfo^.comment+'ait_importexport(extname='''+hp.extname+''', intname='''+hp.intname+''', extmodule='''+hp.extmodule+''', symstype='+symstypestr+')');
+          if hp.extmodule='' then
+            writer.AsmWriteLn(#9'.export_name '+hp.intname+', '+hp.extname);
+        end;
+{$endif WASM}
+
     var
       ch       : char;
       lasthp,
@@ -1258,13 +1323,17 @@ implementation
              begin
                if (tai_label(hp).labsym.is_used) then
                 begin
-                  if (tai_label(hp).labsym.bind=AB_PRIVATE_EXTERN) then
-                    begin
-                      writer.AsmWrite(#9'.private_extern ');
-                      writer.AsmWriteln(tai_label(hp).labsym.name);
-                    end;
+{$ifdef DEBUG_LABEL}
+                  writer.AsmWrite(asminfo^.comment);
+                  writer.AsmWriteLn('References = ' + tostr(tai_label(hp).labsym.getrefs));
+{$endif DEBUG_LABEL}
                   if tai_label(hp).labsym.bind in [AB_GLOBAL,AB_PRIVATE_EXTERN] then
                    begin
+                     if (tai_label(hp).labsym.bind=AB_PRIVATE_EXTERN) then
+                       begin
+                         writer.AsmWrite(#9'.private_extern ');
+                         writer.AsmWriteln(tai_label(hp).labsym.name);
+                       end;
 {$ifdef arm}
                      { do no change arm mode accidently, .globl seems to reset the mode }
                      if GenerateThumbCode or GenerateThumb2Code then
@@ -1343,7 +1412,8 @@ implementation
                  end
                else
                  begin
-                   if ((target_info.system <> system_arm_linux) and (target_info.system <> system_arm_android)) then
+                   if ((target_info.system <> system_arm_linux) and (target_info.system <> system_arm_android)) or
+                     (target_asm.id=as_arm_vasm) then
                      sepChar := '@'
                    else
                      sepChar := '#';
@@ -1377,6 +1447,10 @@ implementation
                  { the .localentry directive has to specify the size from the
                    start till here of the non-local entry code as second argument }
                  s:=', .-';
+               if ((target_info.system <> system_arm_linux) and (target_info.system <> system_arm_android)) then
+                 sepChar := '@'
+               else
+                 sepChar := '#';
                if replaceforbidden then
                  begin
                    { avoid string truncation }
@@ -1388,6 +1462,11 @@ implementation
                        writer.AsmWrite(#9'.globl ');
                        writer.AsmWriteLn(ApplyAsmSymbolRestrictions(tai_symbolpair(hp).sym^));
                      end;
+                   if (tf_needs_symbol_type in target_info.flags) then
+                     begin
+                       writer.AsmWrite(#9'.type'#9 + ApplyAsmSymbolRestrictions(tai_symbolpair(hp).sym^));
+                       writer.AsmWriteLn(',' + sepChar + 'function');
+                     end;
                  end
                else
                  begin
@@ -1400,6 +1479,11 @@ implementation
                        writer.AsmWrite(#9'.globl ');
                        writer.AsmWriteLn(tai_symbolpair(hp).sym^);
                      end;
+                   if (tf_needs_symbol_type in target_info.flags) then
+                     begin
+                       writer.AsmWrite(#9'.type'#9 + tai_symbolpair(hp).sym^);
+                       writer.AsmWriteLn(',' + sepChar + 'function');
+                     end;
                  end;
              end;
            ait_symbol_end :
@@ -1538,16 +1622,43 @@ implementation
              end;
            ait_eabi_attribute:
              begin
-               case tai_eabi_attribute(hp).eattr_typ of
-                 eattrtype_dword:
-                   writer.AsmWrite(#9'.eabi_attribute '+tostr(tai_eabi_attribute(hp).tag)+','+tostr(tai_eabi_attribute(hp).value));
-                 eattrtype_ntbs:
-                   writer.AsmWrite(#9'.eabi_attribute '+tostr(tai_eabi_attribute(hp).tag)+',"'+tai_eabi_attribute(hp).valuestr^+'"');
-                 else
-                   Internalerror(2019100601);
-               end;
-               writer.AsmLn;
+               { as of today, vasm does not support the eabi directives }
+               if target_asm.id<>as_arm_vasm then
+                 begin
+                   case tai_eabi_attribute(hp).eattr_typ of
+                     eattrtype_dword:
+                       writer.AsmWrite(#9'.eabi_attribute '+tostr(tai_eabi_attribute(hp).tag)+','+tostr(tai_eabi_attribute(hp).value));
+                     eattrtype_ntbs:
+                       begin
+                         if assigned(tai_eabi_attribute(hp).valuestr) then
+                           writer.AsmWrite(#9'.eabi_attribute '+tostr(tai_eabi_attribute(hp).tag)+',"'+tai_eabi_attribute(hp).valuestr^+'"')
+                         else
+                           writer.AsmWrite(#9'.eabi_attribute '+tostr(tai_eabi_attribute(hp).tag)+',""');
+                       end
+                     else
+                       Internalerror(2019100601);
+                   end;
+                   writer.AsmLn;
+                 end;
+             end;
+
+{$ifdef WASM}
+           ait_local:
+             begin
+               if tai_local(hp).first then
+                 writer.AsmWrite(#9'.local'#9)
+               else
+                 writer.AsmWrite(', ');
+               writer.AsmWrite(gas_wasm_basic_type_str[tai_local(hp).bastyp]);
+               if tai_local(hp).last then
+                 writer.AsmLn;
              end;
+           ait_functype:
+             WriteFuncTypeDirective(tai_functype(hp));
+           ait_importexport:
+             WriteImportExport(tai_impexp(hp));
+{$endif WASM}
+
            else
              if not WriteComments(hp) then
                internalerror(2006012201);

compiler/aopt.pas

@@ -219,8 +219,9 @@ Unit aopt;
                             p := hp1;
                           End
                         { merge allocations/deallocations }
-                        else if assigned(findregalloc(tai_regalloc(p).reg, tai(p.next)))
-                          and getnextinstruction(p,hp1) and
+                        else if assigned(findregalloc(tai_regalloc(p).reg, tai(p.next))) and
+                          getnextinstruction(p,hp1) and
+                          (not(RegLoadedWithNewValue(tai_regalloc(p).Reg, hp1)) or InstructionLoadsFromReg(tai_regalloc(p).Reg, hp1)) and
                           { don't merge deallocations/allocation which mark a new use of register, this
                             enables more possibilities for the peephole optimizer }
                           not(tai_regalloc(p).keep) then

compiler/aoptobj.pas

@@ -1400,6 +1400,8 @@ Unit AoptObj;
             reg:=newreg(R_FPUREGISTER,getsupreg(reg),R_SUBWHOLE);
           R_ADDRESSREGISTER:
             reg:=newreg(R_ADDRESSREGISTER,getsupreg(reg),R_SUBWHOLE);
+          R_SPECIALREGISTER:
+            reg:=newreg(R_SPECIALREGISTER,getsupreg(reg),R_SUBWHOLE);
           else
             Internalerror(2018030701);
         end;
@@ -2000,10 +2002,7 @@ Unit AoptObj;
 {$ifdef cpudelayslot}
                         RemoveDelaySlot(p);
 {$endif cpudelayslot}
-                        UpdateUsedRegs(tai(p.Next));
-                        AsmL.Remove(p);
-                        p.Free;
-                        p := hp1;
+                        RemoveCurrentP(p, hp1);
 
                         Result := True;
                         Exit;
@@ -2041,8 +2040,7 @@ Unit AoptObj;
 {$ifdef cpudelayslot}
                             RemoveDelaySlot(hp1);
 {$endif cpudelayslot}
-                            asml.remove(hp1);
-                            hp1.free;
+                            RemoveInstruction(hp1);
 
                             stoploop := False;
 
@@ -2079,7 +2077,7 @@ Unit AoptObj;
                 else
                   begin
                     { Do not try to optimize if the test generating the condition
-                      is the same instruction, like 'bne	$v0,$zero,.Lj3' for MIPS }
+                      is the same instruction, like 'bne $v0,$zero,.Lj3' for MIPS }
                     if (taicpu(p).ops>1) or (taicpu(hp1).ops>1) then
                       exit;
 
@@ -2087,7 +2085,8 @@ Unit AoptObj;
                         jmp<cond1>    @Lbl1
                         jmp<cond2>    @Lbl2
 
-                        Remove 2nd jump if conditions are equal or cond2 is fully covered by cond1
+                        Remove 2nd jump if conditions are equal or cond2 is a subset of cond1
+                        (as if the first jump didn't branch, then neither will the 2nd)
                     }
 
                     if condition_in(taicpu(hp1).condition, taicpu(p).condition) then
@@ -2096,9 +2095,10 @@ Unit AoptObj;
 
                         NCJLabel.decrefs;
                         GetNextInstruction(hp1, hp2);
-
-                        AsmL.Remove(hp1);
-                        hp1.Free;
+{$ifdef cpudelayslot}
+                        RemoveDelaySlot(hp1);
+{$endif cpudelayslot}
+                        RemoveInstruction(hp1);
 
                         hp1 := hp2;
 
@@ -2112,9 +2112,9 @@ Unit AoptObj;
                         jmp<cond1>  @Lbl1
                         jmp<cond2>  @Lbl2
 
-                      And inv(cond2) is a subset of cond1 (e.g. je followed by jne, or jae followed by jbe) )
+                      And inv(cond1) is a subset of cond2 (e.g. je followed by jne, or jae followed by jbe) )
                     }
-                    if condition_in(inverse_cond(taicpu(hp1).condition), taicpu(p).condition) then
+                    if condition_in(inverse_cond(taicpu(p).condition), taicpu(hp1).condition) then
                       begin
                         GetNextInstruction(hp1, hp2);
 
@@ -2122,16 +2122,16 @@ Unit AoptObj;
                           the first jump completely }
                         if FindLabel(CJLabel, hp2) then
                           begin
+                            { However, to be absolutely correct, cond2 must be changed to inv(cond1) }
+                            taicpu(hp1).condition := inverse_cond(taicpu(p).condition);
+
                             DebugMsg(SPeepholeOptimization+'jmp<cond> before jmp<inv_cond> - removed first jump',p);
 
                             CJLabel.decrefs;
 {$ifdef cpudelayslot}
                             RemoveDelaySlot(p);
 {$endif cpudelayslot}
-                            UpdateUsedRegs(tai(p.Next));
-                            AsmL.Remove(p);
-                            p.Free;
-                            p := hp1;
+                            RemoveCurrentP(p, hp1);
 
                             Result := True;
                             Exit;
@@ -2144,7 +2144,7 @@ Unit AoptObj;
                             improve this particular optimisation to work on AVR,
                             please do. [Kit] }
                           begin
-                            { Since cond1 is a subset of inv(cond2), jmp<cond2> will always branch if
+                            { Since inv(cond1) is a subset of cond2, jmp<cond2> will always branch if
                               jmp<cond1> does not, so change jmp<cond2> to an unconditional jump. }
 
                             DebugMsg(SPeepholeOptimization+'jmp<cond> before jmp<inv_cond> - made second jump unconditional',p);

compiler/aoptutils.pas

@@ -35,6 +35,10 @@ unit aoptutils;
     function MatchOpType(const p : taicpu; type0,type1,type2 : toptype) : Boolean;
 {$endif max_operands>2}
 
+    { skips all alignment fields and returns the next label (or non-align).
+      returns immediately with true if hp is a label }
+    function SkipAligns(hp: tai; out hp2: tai): boolean;
+
     { skips all labels and returns the next "real" instruction }
     function SkipLabels(hp: tai; out hp2: tai): boolean;
 
@@ -67,6 +71,21 @@ unit aoptutils;
 {$endif max_operands>2}
 
 
+    { skips all alignment fields and returns the next label (or non-align).
+      Returns immediately with True if hp is a label }
+    function SkipAligns(hp: tai; out hp2: tai): boolean;
+      begin
+        while assigned(hp) and
+              (hp.typ in SkipInstr + [ait_label,ait_align]) Do
+          begin
+            { Check that the label is actually live }
+            if (hp.typ = ait_label) and tai_label(hp).labsym.is_used then
+              Break;
+            hp := tai(hp.next);
+          end;
+        SkipAligns := SetAndTest(hp, hp2);
+      end;
+
     { skips all labels and returns the next "real" instruction }
     function SkipLabels(hp: tai; out hp2: tai): boolean;
       begin

compiler/arm/aasmcpu.pas

@@ -166,14 +166,14 @@ uses
       IF_ARMv7M     = $00F00000;
       IF_ARMv7EM    = $01000000;
 
-      IF_FPMASK     = $F0000000;
-      IF_FPA        = $10000000;
-      IF_VFPv2      = $20000000;
-      IF_VFPv3      = $40000000;
-      IF_VFPv4      = $80000000;
+      IF_FPMASK     = $00000F00;
+      IF_FPA        = $00000100;
+      IF_VFPv2      = $00000200;
+      IF_VFPv3      = $00000400;
+      IF_VFPv4      = $00000800;
 
       { if the instruction can change in a second pass }
-      IF_PASS2  = longint($80000000);
+      IF_PASS2  = $80000000;
 
     type
       TInsTabCache=array[TasmOp] of longint;
@@ -278,7 +278,7 @@ uses
       private
          { arm version info }
          fArmVMask,
-         fArmMask  : longint;
+         fArmMask  : longword;
          { next fields are filled in pass1, so pass2 is faster }
          inssize   : shortint;
          insoffset : longint;
@@ -1621,6 +1621,9 @@ implementation
           end;
       end;
 
+{$push}
+{ Disable range and overflow checking here }
+{$R-}{$Q-}        
     procedure fix_invalid_imms(list: TAsmList);
       var
         curtai: tai;
@@ -1669,6 +1672,7 @@ implementation
           end;
       end;
 
+{$pop}
 
     procedure gather_it_info(list: TAsmList);
       var
@@ -2209,6 +2213,7 @@ implementation
             IF_NONE,
             IF_ARMv4,
             IF_ARMv4,
+            IF_ARMv4,
             IF_ARMv4T or IF_ARMv4,
             IF_ARMv4T or IF_ARMv4 or IF_ARMv5 or IF_ARMv5T,
             IF_ARMv4T or IF_ARMv4 or IF_ARMv5 or IF_ARMv5T or IF_ARMv5TE,

compiler/arm/agarmgas.pas

@@ -61,6 +61,7 @@ unit agarmgas;
     const 
       cputype_to_gas_march : array[tcputype] of string = (
         '', // cpu_none
+        'armv2',
         'armv3',
         'armv4',
         'armv4t',
@@ -435,6 +436,16 @@ unit agarmgas;
                        internalerror(2003112903);
                    end;
                  end
+               { syscall number for vasm does not need a # }
+               else if (target_asm.id=as_arm_vasm) and (i=0) and ((op=A_SWI) or (op=A_SVC)) then
+                 begin
+                   case taicpu(hp).oper[0]^.typ of
+                     top_const:
+                       s:=s+sep+tostr(taicpu(hp).oper[0]^.val);
+                     else
+                       internalerror(2021052301);
+                   end;
+                 end
                else
                  s:=s+sep+getopstr(taicpu(hp).oper[i]^);
 
@@ -484,7 +495,7 @@ unit agarmgas;
             asmbin : 'clang';
             asmcmd : '-x assembler -c -target $TRIPLET -o $OBJ $EXTRAOPT -x assembler $ASM';
             supported_targets : [system_arm_ios];
-            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm];
+            flags : [af_needar,af_smartlink_sections,af_supports_dwarf,af_llvm,af_supports_hlcfi];
             labelprefix : 'L';
             labelmaxlen : -1;
             comment : '# ';

compiler/arm/agarmvasm.pas

@@ -0,0 +1,150 @@
+{
+    Copyright (c) 2016 by the Free Pascal development team
+
+    This unit is the VASM assembler writer for ARM
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+
+unit agarmvasm;
+
+{$i fpcdefs.inc}
+
+  interface
+
+    uses
+       aasmbase,systems,
+       aasmtai,aasmdata,
+       assemble,aggas,agarmgas,
+       cpubase,cgutils,
+       globtype;
+
+  type
+    TARMVASM = class(TARMGNUAssembler)
+    protected
+      function sectionattrs(atype:TAsmSectiontype):string; override;
+    public
+      constructor CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean); override;
+      function MakeCmdLine: TCmdStr; override;
+    end;
+
+  implementation
+
+    uses
+       cutils,cfileutl,globals,verbose,
+       cgbase,
+       cscript,
+       itcpugas,cpuinfo,
+       aasmcpu;
+
+{****************************************************************************}
+{                         VASM m68k Assembler writer                         }
+{****************************************************************************}
+
+
+    constructor TARMVASM.CreateWithWriter(info: pasminfo; wr: TExternalAssemblerOutputFile; freewriter, smart: boolean);
+      begin
+        inherited;
+        InstrWriter := TARMInstrWriter.create(self);
+      end;
+
+
+    function TARMVASM.sectionattrs(atype:TAsmSectiontype):string;
+      begin
+        case atype of
+          sec_code, sec_fpc, sec_init, sec_fini:
+            result:='acrx';
+          { map sec_rodata as read-write, otherwise the linker (vlink) complains if it
+            has to write into the relocations in a rodata section. (KB) }
+          sec_data, sec_rodata:
+            result:='adrw';
+          sec_rodata_norel:
+            result:='adr';
+          sec_bss, sec_threadvar:
+            result:='aurw';
+          sec_stab, sec_stabstr:
+            result:='dr';
+          else
+            result:='';
+        end;
+      end;
+
+
+    const
+      cputype_to_vasm_march : array[tcputype] of string = (
+        '', // cpu_none
+        'a2',
+        'a3',
+        'a4',
+        'a4t',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '',
+        '');
+
+    function TARMVASM.MakeCmdLine: TCmdStr;
+      var
+        objtype: string;
+      begin
+        result:=asminfo^.asmcmd;
+
+        case target_info.system of
+          { a.out doesn't support named sections, lets use ELF for interoperability }
+          system_arm_linux: objtype:='-Felf';
+        else
+          internalerror(2016052601);
+        end;
+
+        Replace(result,'$ASM',maybequoted(ScriptFixFileName(AsmFileName)));
+        Replace(result,'$OBJ',maybequoted(ScriptFixFileName(ObjFileName)));
+        Replace(result,'$ARCH','-'+cputype_to_vasm_march[current_settings.cputype]);
+        Replace(result,'$OTYPE',objtype);
+        Replace(result,'$EXTRAOPT',asmextraopt);
+      end;
+
+{*****************************************************************************
+                                  Initialize
+*****************************************************************************}
+
+  const
+    as_arm_vasm_info : tasminfo =
+       (
+         id     : as_arm_vasm;
+
+         idtxt  : 'VASM';
+         asmbin : 'vasmarm_std';
+         asmcmd:  '-quiet -elfregs -gas $OTYPE $ARCH -o $OBJ $EXTRAOPT $ASM';
+         supported_targets : [system_arm_linux];
+         flags : [af_needar,af_smartlink_sections];
+         labelprefix : '.L';
+         labelmaxlen : -1;
+         comment : '# ';
+         dollarsign: '$';
+       );
+
+begin
+  RegisterAssembler(as_arm_vasm_info,TARMVASM);
+end.

compiler/arm/cgcpu.pas

@@ -787,10 +787,11 @@ unit cgcpu;
         shifterop : tshifterop;
         bitsset : byte;
         negative : boolean;
-        first : boolean;
+        first, doshiftadd: boolean;
         b,
         cycles : byte;
         maxeffort : byte;
+        leftmostbit,i,shiftvalue: DWord;
       begin
         result:=true;
         cycles:=0;
@@ -800,7 +801,6 @@ unit cgcpu;
         if negative then
           inc(cycles);
         multiplier:=dword(abs(a));
-        bitsset:=popcnt(multiplier and $fffffffe);
 
         { heuristics to estimate how much instructions are reasonable to replace the mul,
           this is currently based on XScale timings }
@@ -824,6 +824,30 @@ unit cgcpu;
         if ((dword(a) and $ffff8000)=0) or ((dword(a) and $ffff8000)=$ffff8000) then
           dec(maxeffort);
 
+        { "symmetric" bit pattern like $10101010 where
+          res:=a*$10101010 can be simplified into
+
+          temp:=a*$1010
+          res:=temp+temp shl 16
+        }
+        doshiftadd:=false;
+        leftmostbit:=BsrDWord(multiplier);
+        shiftvalue:=0;
+        if (maxeffort>1) and (leftmostbit>2) then
+          begin
+            for i:=2 to 31 do
+              if (multiplier shr i)=(multiplier and ($ffffffff shr (32-i))) then
+                begin
+                  doshiftadd:=true;
+                  shiftvalue:=i;
+                  dec(maxeffort);
+                  multiplier:=multiplier shr shiftvalue;
+                  break;
+                end;
+          end;
+
+        bitsset:=popcnt(multiplier and $fffffffe);
+
         { most simple cases }
         if a=1 then
           a_load_reg_reg(list,OS_32,OS_32,src,dst)
@@ -857,6 +881,11 @@ unit cgcpu;
                 first:=false;
                 dec(multiplier,1 shl shifterop.shiftimm);
               end;
+            if doshiftadd then
+              begin
+                shifterop.shiftimm:=shiftvalue;
+                list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,dst,dst,shifterop));
+              end;
             if negative then
               list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
           end
@@ -889,6 +918,11 @@ unit cgcpu;
                     end;
                 first:=false;
               end;
+            if doshiftadd then
+              begin
+                shifterop.shiftimm:=shiftvalue;
+                list.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,dst,dst,dst,shifterop));
+              end;
             if negative then
               list.concat(taicpu.op_reg_reg_const(A_RSB,dst,dst,0));
           end
@@ -3739,6 +3773,10 @@ unit cgcpu;
               end;
 
             registerarea:=0;
+            { do not save integer registers if the procedure does not return }
+            if po_noreturn in current_procinfo.procdef.procoptions then
+              regs:=[];
+
             if regs<>[] then
                begin
                  for r:=RS_R0 to RS_R15 do
@@ -3815,6 +3853,10 @@ unit cgcpu;
          stackmisalignment: pint;
          stack_parameters : Boolean;
       begin
+        { a routine not returning needs no exit code,
+          we trust this directive as arm thumb is normally used if small code shall be generated }
+        if po_noreturn in current_procinfo.procdef.procoptions then
+          exit;
         if not(nostackframe) then
           begin
             stack_parameters:=current_procinfo.procdef.stack_tainting_parameter(calleeside);
@@ -5018,6 +5060,10 @@ unit cgcpu;
          LocalSize : longint;
          stackmisalignment: pint;
       begin
+        { a routine not returning needs no exit code,
+          we trust this directive as arm thumb is normally used if small code shall be generated }
+        if po_noreturn in current_procinfo.procdef.procoptions then
+          exit;
         if not(nostackframe) then
           begin
             stackmisalignment:=0;

compiler/arm/cpubase.pas

@@ -605,6 +605,9 @@ unit cpubase;
       end;
 
 
+{$push}
+{ Disable range and overflow checking here }
+{$R-}{$Q-}        
     function is_thumb32_imm(d: aint): boolean;
       var
         t : aint;
@@ -639,9 +642,6 @@ unit cpubase;
           end;
       end;
     
-{$push}
-{ Disable range and overflow checking here }
-{$R-}{$Q-}        
     function is_continuous_mask(d : aword;var lsb, width: byte) : boolean;
       var
         msb : byte;

compiler/arm/cpuinfo.pas

@@ -37,6 +37,7 @@ Type
    { possible supported processors for this target }
    tcputype =
       (cpu_none,
+       cpu_armv2,
        cpu_armv3,
        cpu_armv4,
        cpu_armv4t,
@@ -496,8 +497,10 @@ Type
 
       { Atmel }
       ct_sam3x8e,
+      ct_samd51p19a,
       ct_arduino_due,
       ct_flip_n_click,
+      ct_wio_terminal,
       
       { Nordic Semiconductor }
       ct_nrf51422_xxaa,
@@ -552,6 +555,7 @@ Const
    ];
 
    cputypestr : array[tcputype] of string[8] = ('',
+     'ARMV2',
      'ARMV3',
      'ARMV4',
      'ARMV4T',
@@ -1019,8 +1023,12 @@ Const
 
       { Atmel }
       (controllertypestr:'ATSAM3X8E';     controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
+
+      (controllertypestr:'SAMD51P19A';    controllerunitstr:'SAMD51P19A'; cputype:cpu_armv7em; fputype:fpu_fpv4_sp_d16; flashbase:$00000000; flashsize:$00080000; srambase:$20000000; sramsize:$00030000),
+      
       (controllertypestr:'ARDUINO_DUE';   controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
       (controllertypestr:'FLIP_N_CLICK';  controllerunitstr:'SAM3X8E'; cputype:cpu_armv7m; fputype:fpu_soft; flashbase:$00080000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
+      (controllertypestr:'WIO_TERMINAL'; controllerunitstr:'SAMD51P19A'   ; cputype:cpu_armv7em; fputype:fpu_fpv4_sp_d16; flashbase:$00004000; flashsize:$0007C000; srambase:$20000000; sramsize:$00030000),
       
       { Nordic Semiconductor }
       (controllertypestr:'NRF51422_XXAA'; controllerunitstr:'NRF51'; cputype:cpu_armv6m; fputype:fpu_soft; flashbase:$00000000; flashsize:$00040000;      srambase:$20000000; sramsize:$00004000),
@@ -1089,6 +1097,7 @@ Const
  const
    cpu_capabilities : array[tcputype] of set of tcpuflags =
      ( { cpu_none     } [],
+       { cpu_armv2    } [],
        { cpu_armv3    } [],
        { cpu_armv4    } [CPUARM_HAS_ALL_MEM,CPUARM_HAS_UMULL],
        { cpu_armv4t   } [CPUARM_HAS_THUMB,CPUARM_HAS_ALL_MEM,CPUARM_HAS_BX,CPUARM_HAS_UMULL],

compiler/arm/cputarg.pas

@@ -81,6 +81,10 @@ implementation
       ,agarmgas
     {$endif}
 
+    {$ifndef Noagrmvasm}
+      ,agarmvasm
+    {$endif Noagarmvasm}
+
       ,ogcoff
       ,ogelf
       ,cpuelf

compiler/arm/narmmat.pas

@@ -77,8 +77,8 @@ implementation
            (nodetype=divn) and
            not(is_64bit(resultdef)) and
            {Only the ARM and thumb2-isa support umull and smull, which are required for arbitary division by const optimization}
-           (GenerateArmCode or
-            GenerateThumb2Code or
+           (((GenerateArmCode or
+             GenerateThumb2Code) and (CPUARM_HAS_UMULL in cpu_capabilities[current_settings.cputype])) or
             (ispowerof2(tordconstnode(right).value,power) or
             (tordconstnode(right).value=1) or
             (tordconstnode(right).value=int64(-1))

compiler/arm/narmset.pas

@@ -191,15 +191,23 @@ implementation
 
         procedure genitem_thumb2(list:TAsmList;t : pcaselabel);
           var
-            i : aint;
+            i : int64;
           begin
             if assigned(t^.less) then
               genitem_thumb2(list,t^.less);
             { fill possible hole }
-            for i:=last.svalue+1 to t^._low.svalue-1 do
-              list.concat(Tai_const.Create_rel_sym(aitconst_half16bit,tablelabel,elselabel));
-            for i:=t^._low.svalue to t^._high.svalue do
-              list.concat(Tai_const.Create_rel_sym(aitconst_half16bit,tablelabel,blocklabel(t^.blockid)));
+            i:=last.svalue+1;
+            while i<=t^._low.svalue-1 do
+              begin
+                list.concat(Tai_const.Create_rel_sym(aitconst_half16bit,tablelabel,elselabel));
+                i:=i+1;
+              end;
+            i:=t^._low.svalue;
+            while i<=t^._high.svalue do
+              begin
+                list.concat(Tai_const.Create_rel_sym(aitconst_half16bit,tablelabel,blocklabel(t^.blockid)));
+                i:=i+1;
+              end;
             last:=t^._high.svalue;
             if assigned(t^.greater) then
               genitem_thumb2(list,t^.greater);

compiler/arm/narmutil.pas

@@ -97,6 +97,7 @@ interface
         if (target_info.system in [system_arm_linux]) and (target_info.abi in [abi_eabihf,abi_eabi]) then
           begin
             case current_settings.cputype of
+              cpu_armv2,
               cpu_armv3:
                 begin
                   current_asmdata.asmlists[al_start].Concat(tai_eabi_attribute.create(Tag_CPU_arch,0));

compiler/arm/raarmgas.pas

@@ -151,6 +151,7 @@ Unit raarmgas;
     function tarmattreader.is_targetdirective(const s: string): boolean;
       begin
         case s of
+          '.force_thumb',
           '.thumb_func',
           '.code',
           '.thumb_set':
@@ -1464,6 +1465,11 @@ Unit raarmgas;
             begin
               consume(AS_TARGET_DIRECTIVE);
               curList.concat(tai_directive.create(asd_thumb_func,''));
+            end;
+          '.force_thumb':
+            begin
+              consume(AS_TARGET_DIRECTIVE);
+              curList.concat(tai_directive.create(asd_force_thumb,''));
             end
           else
             inherited HandleTargetDirective;

compiler/arm/rgcpu.pas

@@ -400,10 +400,11 @@ unit rgcpu;
         level := 0;
         while assigned(hp) do
           begin
-            if IsIT(taicpu(hp).opcode) then
-              break
-            else if hp.typ=ait_instruction then
-              inc(level);
+            if hp.typ=ait_instruction then
+              if IsIT(taicpu(hp).opcode) then
+                break
+              else
+                inc(level);
 
             hp:=tai(hp.Previous);
           end;

compiler/armgen/aoptarm.pas

@@ -26,7 +26,7 @@ Unit aoptarm;
 {$i fpcdefs.inc}
 
 { $define DEBUG_PREREGSCHEDULER}
-{ $define DEBUG_AOPTCPU}
+{$define DEBUG_AOPTCPU}
 
 Interface
 
@@ -41,12 +41,15 @@ Type
 
     function RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string): boolean;
     function RedundantMovProcess(var p: tai; var hp1: tai): boolean;
-    function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
+    function GetNextInstructionUsingReg(Current: tai; out Next: tai; const reg: TRegister): Boolean;
 
     function OptPass1UXTB(var p: tai): Boolean;
     function OptPass1UXTH(var p: tai): Boolean;
     function OptPass1SXTB(var p: tai): Boolean;
     function OptPass1SXTH(var p: tai): Boolean;
+
+    function OptPass1LDR(var p: tai): Boolean; virtual;
+    function OptPass1STR(var p: tai): Boolean; virtual;
     function OptPass1And(var p: tai): Boolean; virtual;
   End;
 
@@ -69,15 +72,23 @@ Implementation
     systems,
     cpuinfo,
     cgobj,procinfo,
-    aasmbase,aasmdata;
+    aasmbase,aasmdata,itcpugas;
 
 
 {$ifdef DEBUG_AOPTCPU}
+  const
+    SPeepholeOptimization: shortstring = 'Peephole Optimization: ';
+
   procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);
     begin
       asml.insertbefore(tai_comment.Create(strpnew(s)), p);
     end;
 {$else DEBUG_AOPTCPU}
+  { Empty strings help the optimizer to remove string concatenations that won't
+    ever appear to the user on release builds. [Kit] }
+  const
+    SPeepholeOptimization = '';
+
   procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);inline;
     begin
     end;
@@ -179,7 +190,7 @@ Implementation
 
 
   function TARMAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
-    Out Next: tai; reg: TRegister): Boolean;
+    Out Next: tai; const reg: TRegister): Boolean;
     var
       gniResult: Boolean;
     begin
@@ -395,7 +406,14 @@ Implementation
                   UpdateUsedRegs(TmpUsedRegs, tai(current_hp.Next));
                   LDRChange := False;
 
-                  if (taicpu(next_hp).opcode in [A_LDR,A_STR]) and (taicpu(next_hp).ops = 2) then
+                  if (taicpu(next_hp).opcode in [A_LDR,A_STR]) and (taicpu(next_hp).ops = 2)
+{$ifdef AARCH64}
+                    { If r0 is the zero register, then this sequence of instructions will cause
+                      an access violation, but that's better than an assembler error caused by
+                      changing r0 to xzr inside the reference (Where it's illegal). [Kit] }
+                    and (getsupreg(taicpu(p).oper[1]^.reg) <> RS_XZR)
+{$endif AARCH64}
+                    then
                     begin
 
                       { Change the registers from r1 to r0 }
@@ -1018,6 +1036,209 @@ Implementation
     end;
 
 
+  function TARMAsmOptimizer.OptPass1LDR(var p : tai) : Boolean;
+    var
+      hp1: tai;
+      Reference: TReference;
+      NewOp: TAsmOp;
+    begin
+      Result := False;
+      if (taicpu(p).ops <> 2) or (taicpu(p).condition <> C_None) then
+        Exit;
+
+      Reference := taicpu(p).oper[1]^.ref^;
+      if (Reference.addressmode = AM_OFFSET) and
+        not RegInRef(taicpu(p).oper[0]^.reg, Reference) and
+        { Delay calling GetNextInstruction for as long as possible }
+        GetNextInstruction(p, hp1) and
+        (hp1.typ = ait_instruction) and
+        (taicpu(hp1).condition = C_None) and
+        (taicpu(hp1).oppostfix = taicpu(p).oppostfix) then
+        begin
+          if (taicpu(hp1).opcode = A_STR) and
+            RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) and
+            (getregtype(taicpu(p).oper[0]^.reg) = getregtype(taicpu(hp1).oper[0]^.reg)) then
+            begin
+              { With:
+                  ldr reg1,[ref]
+                  str reg2,[ref]
+
+                If reg1 = reg2, Remove str
+              }
+              if taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg then
+                begin
+                  DebugMsg(SPeepholeOptimization + 'Removed redundant store instruction (load/store -> load/nop)', hp1);
+                  RemoveInstruction(hp1);
+                  Result := True;
+                  Exit;
+                end;
+            end
+          else if (taicpu(hp1).opcode = A_LDR) and
+            RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) then
+            begin
+              { With:
+                  ldr reg1,[ref]
+                  ldr reg2,[ref]
+
+                If reg1 = reg2, delete the second ldr
+                If reg1 <> reg2, changing the 2nd ldr to a mov might introduce
+                  a dependency, but it will likely open up new optimisations, so
+                  do it for now and handle any new dependencies later.
+              }
+              if taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg then
+                begin
+                  DebugMsg(SPeepholeOptimization + 'Removed duplicate load instruction (load/load -> load/nop)', hp1);
+                  RemoveInstruction(hp1);
+                  Result := True;
+                  Exit;
+                end
+              else if
+                (getregtype(taicpu(p).oper[0]^.reg) = R_INTREGISTER) and
+                (getregtype(taicpu(hp1).oper[0]^.reg) = R_INTREGISTER) and
+                (getsubreg(taicpu(p).oper[0]^.reg) = getsubreg(taicpu(hp1).oper[0]^.reg)) then
+                begin
+                  DebugMsg(SPeepholeOptimization + 'Changed second ldr' + oppostfix2str[taicpu(hp1).oppostfix] + ' to mov (load/load -> load/move)', hp1);
+                  taicpu(hp1).opcode := A_MOV;
+                  taicpu(hp1).oppostfix := PF_None;
+                  taicpu(hp1).loadreg(1, taicpu(p).oper[0]^.reg);
+                  AllocRegBetween(taicpu(p).oper[0]^.reg, p, hp1, UsedRegs);
+                  Result := True;
+                  Exit;
+                end;
+            end;
+        end;
+    end;
+
+
+    function TARMAsmOptimizer.OptPass1STR(var p : tai) : Boolean;
+      var
+        hp1: tai;
+        Reference: TReference;
+        SizeMismatch: Boolean;
+        SrcReg: TRegister;
+        NewOp: TAsmOp;
+      begin
+        Result := False;
+        if (taicpu(p).ops <> 2) or (taicpu(p).condition <> C_None) then
+          Exit;
+
+        Reference := taicpu(p).oper[1]^.ref^;
+        if (Reference.addressmode = AM_OFFSET) and
+          not RegInRef(taicpu(p).oper[0]^.reg, Reference) and
+          { Delay calling GetNextInstruction for as long as possible }
+          GetNextInstruction(p, hp1) and
+          (hp1.typ = ait_instruction) and
+          (taicpu(hp1).condition = C_None) and
+          (taicpu(hp1).oppostfix = taicpu(p).oppostfix) then
+
+        if GetNextInstruction(p, hp1) and
+          (hp1.typ = ait_instruction) and
+          (taicpu(hp1).condition = C_None) then
+          begin
+            { Saves constant dereferencing and makes it easier to change the size if necessary }
+            SrcReg := taicpu(p).oper[0]^.reg;
+
+            if (taicpu(hp1).opcode = A_LDR) and
+              RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) and
+              (
+                (taicpu(hp1).oppostfix = taicpu(p).oppostfix) or
+                ((taicpu(p).oppostfix = PF_B) and (taicpu(hp1).oppostfix = PF_SB)) or
+                ((taicpu(p).oppostfix = PF_H) and (taicpu(hp1).oppostfix = PF_SH))
+{$ifdef AARCH64}
+                or ((taicpu(p).oppostfix = PF_W) and (taicpu(hp1).oppostfix = PF_SW))
+{$endif AARCH64}
+              ) then
+              begin
+                { With:
+                    str reg1,[ref]
+                    ldr reg2,[ref]
+
+                  If reg1 = reg2, Remove ldr.
+                  If reg1 <> reg2, replace ldr with "mov reg2,reg1"
+                }
+
+                if (SrcReg = taicpu(hp1).oper[0]^.reg) and
+                  { e.g. the ldrb in strb/ldrb is not a null operation as it clears the upper 24 bits }
+                  (taicpu(p).oppostfix=PF_None) then
+                  begin
+                    DebugMsg(SPeepholeOptimization + 'Removed redundant load instruction (store/load -> store/nop)', hp1);
+                    RemoveInstruction(hp1);
+                    Result := True;
+                    Exit;
+                  end
+                else if (getregtype(taicpu(p).oper[0]^.reg) = R_INTREGISTER) and
+                  (getregtype(taicpu(hp1).oper[0]^.reg) = R_INTREGISTER) and
+                  (getsubreg(taicpu(p).oper[0]^.reg) = getsubreg(taicpu(hp1).oper[0]^.reg)) then
+                  begin
+                    NewOp:=A_NONE;
+                    if taicpu(hp1).oppostfix=PF_None then
+                      NewOp:=A_MOV
+                    else 
+{$ifndef AARCH64}
+                      if (current_settings.cputype >= cpu_armv6) then
+{$endif not AARCH64}
+                      case taicpu(hp1).oppostfix of
+                        PF_B:
+                          NewOp := A_UXTB;
+                        PF_SB:
+                          NewOp := A_SXTB;
+                        PF_H:
+                          NewOp := A_UXTH;
+                        PF_SH:
+                          NewOp := A_SXTH;
+{$ifdef AARCH64}
+                        PF_SW:
+                          NewOp := A_SXTW;
+                        PF_W:
+                          NewOp := A_MOV;
+{$endif AARCH64}
+                      else
+                        InternalError(2021043001);
+                      end;
+                    if (NewOp<>A_None) then
+                      begin
+                        DebugMsg(SPeepholeOptimization + 'Changed ldr' + oppostfix2str[taicpu(hp1).oppostfix] + ' to ' + gas_op2str[NewOp] + ' (store/load -> store/move)', hp1);
+
+                        taicpu(hp1).oppostfix := PF_None;
+                        taicpu(hp1).opcode := NewOp;
+                        taicpu(hp1).loadreg(1, taicpu(p).oper[0]^.reg);
+                        AllocRegBetween(taicpu(p).oper[0]^.reg, p, hp1, UsedRegs);
+                        Result := True;
+                        Exit;
+                      end;
+                end
+              end
+            else if (taicpu(hp1).opcode = A_STR) and
+              RefsEqual(taicpu(hp1).oper[1]^.ref^, Reference) then
+              begin
+                { With:
+                    str reg1,[ref]
+                    str reg2,[ref]
+
+                  If reg1 <> reg2, delete the first str
+                  IF reg1 = reg2, delete the second str
+                }
+                if SrcReg = taicpu(hp1).oper[0]^.reg then
+                  begin
+                    DebugMsg(SPeepholeOptimization + 'Removed duplicate store instruction (store/store -> store/nop)', hp1);
+                    RemoveInstruction(hp1);
+                    Result := True;
+                    Exit;
+                  end
+                else if
+                  { Registers same byte size? }
+                  (tcgsize2size[reg_cgsize(taicpu(p).oper[0]^.reg)] = tcgsize2size[reg_cgsize(taicpu(hp1).oper[0]^.reg)]) then
+                  begin
+                    DebugMsg(SPeepholeOptimization + 'Removed dominated store instruction (store/store -> nop/store)', p);
+                    RemoveCurrentP(p, hp1);
+                    Result := True;
+                    Exit;
+                  end;
+              end;
+          end;
+      end;
+
+
   function TARMAsmOptimizer.OptPass1And(var p : tai) : Boolean;
     var
       hp1, hp2: tai;
@@ -1140,10 +1361,10 @@ Implementation
             to
             and reg3,reg1,x
           }
-          else if ((taicpu(p).oper[2]^.val and $ffffff00)=0) and
-            MatchInstruction(p, A_AND, [C_None], [PF_None]) and
+          else if MatchInstruction(p, A_AND, [C_None], [PF_None]) and
             GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
-            MatchInstruction(hp1, [A_UXTB,A_UXTH], [C_None], [PF_None]) and
+            ((((taicpu(p).oper[2]^.val and $ffffff00)=0) and MatchInstruction(hp1, A_UXTB, [C_None], [PF_None])) or
+             (((taicpu(p).oper[2]^.val and $ffff0000)=0) and MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]))) and
             (taicpu(hp1).ops = 2) and
             RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
             MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and

compiler/assemble.pas

@@ -750,7 +750,7 @@ Implementation
 {$ifdef hasunix}
         DoPipe:=(cs_asm_pipe in current_settings.globalswitches) and
                 (([cs_asm_extern,cs_asm_leave,cs_assemble_on_target] * current_settings.globalswitches) = []) and
-                ((asminfo^.id in [as_gas,as_ggas,as_darwin,as_powerpc_xcoff,as_clang_gas,as_clang_llvm,as_solaris_as]));
+                ((asminfo^.id in [as_gas,as_ggas,as_darwin,as_powerpc_xcoff,as_clang_gas,as_clang_llvm,as_solaris_as,as_clang_asdarwin]));
 {$else hasunix}
         DoPipe:=false;
 {$endif}
@@ -1403,8 +1403,8 @@ Implementation
                   len:=p-pstart;
                   if len>255 then
                     internalerror(200509187);
-                  move(pstart^,hs[1],len);
                   hs[0]:=chr(len);
+                  move(pstart^,hs[1],len);
                   sym:=objdata.symbolref(hs);
                   { Second symbol? }
                   if assigned(relocsym) then
@@ -1719,6 +1719,11 @@ Implementation
 {$ifdef ARM}
                    asd_thumb_func:
                      ObjData.ThumbFunc:=true;
+                   asd_force_thumb:
+                     begin
+                       ObjData.ThumbFunc:=true;
+                       Code16:=true;
+                     end;
                    asd_code:
                      begin
                        { ai_directive(hp).name can be only 16 or 32, this is checked by the reader }
@@ -1786,7 +1791,10 @@ Implementation
                    eattrtype_dword:
                      eabi_section.alloc(LengthUleb128(tai_eabi_attribute(hp).value));
                    eattrtype_ntbs:
-                     eabi_section.alloc(Length(tai_eabi_attribute(hp).valuestr^)+1);
+                     if assigned(tai_eabi_attribute(hp).valuestr) then
+                       eabi_section.alloc(Length(tai_eabi_attribute(hp).valuestr^)+1)
+                     else
+                       eabi_section.alloc(1);
                    else
                      Internalerror(2019100701);
                  end;
@@ -1924,6 +1932,9 @@ Implementation
                    asd_thumb_func:
                      { ignore for now, but should be added}
                      ;
+                   asd_force_thumb:
+                     { ignore for now, but should be added}
+                     ;
                    asd_code:
                      { ignore for now, but should be added}
                      ;
@@ -1961,7 +1972,10 @@ Implementation
                    eattrtype_dword:
                      eabi_section.alloc(LengthUleb128(tai_eabi_attribute(hp).value));
                    eattrtype_ntbs:
-                     eabi_section.alloc(Length(tai_eabi_attribute(hp).valuestr^)+1);
+                     if assigned(tai_eabi_attribute(hp).valuestr) then
+                       eabi_section.alloc(Length(tai_eabi_attribute(hp).valuestr^)+1)
+                     else
+                       eabi_section.alloc(1);
                    else
                      Internalerror(2019100703);
                  end;
@@ -2328,7 +2342,10 @@ Implementation
                      end;
                    eattrtype_ntbs:
                      begin
-                       s:=tai_eabi_attribute(hp).valuestr^+#0;
+                       if assigned(tai_eabi_attribute(hp).valuestr) then
+                         s:=tai_eabi_attribute(hp).valuestr^+#0
+                       else
+                         s:=#0;
                        eabi_section.write(s[1],Length(s));
                      end
                    else

compiler/avr/agavrgas.pas

@@ -96,7 +96,7 @@ unit agavrgas;
                 internalerror(2011021707)
               else if base<>NR_NO then
                 begin
-                  if addressmode=AM_PREDRECEMENT then
+                  if addressmode=AM_PREDECREMENT then
                     s:='-';
 
                   case base of

compiler/avr/ccpuinnr.inc

@@ -18,5 +18,6 @@
   in_avr_sleep = in_cpu_first+3,
   in_avr_nop = in_cpu_first+4,
   in_avr_save = in_cpu_first+5,
-  in_avr_restore = in_cpu_first+6
+  in_avr_restore = in_cpu_first+6,
+  in_avr_des = in_cpu_first+7
 

compiler/avr/cgcpu.pas

@@ -120,6 +120,7 @@ unit cgcpu;
         procedure a_op_reg_reg_internal(list: TAsmList; Op: TOpCG; size: TCGSize; src, srchi, dst, dsthi: TRegister);
         procedure a_op_const_reg_internal(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg, reghi: TRegister);
         procedure maybegetcpuregister(list : tasmlist; reg : tregister);
+        function addr_is_io_register(const addr: integer): boolean;
       end;
 
       tcg64favr = class(tcg64f32)
@@ -1084,6 +1085,14 @@ unit cgcpu;
           getcpuregister(list,reg);
       end;
 
+    { Returns true if dataspace address falls in I/O register range }
+    function tcgavr.addr_is_io_register(const addr: integer): boolean;
+    begin
+      result := (not(current_settings.cputype in [cpu_avrxmega3,cpu_avrtiny]) and (addr>31)) or
+                ((current_settings.cputype in [cpu_avrxmega3,cpu_avrtiny]) and (addr>=0)) and
+                (addr<cpuinfo.embedded_controllers[current_settings.controllertype].srambase);
+    end;
+
 
     function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
       var
@@ -1365,15 +1374,13 @@ unit cgcpu;
            end;
          if not conv_done then
            begin
-             // CC
-             // Write to 16 bit ioreg, first high byte then low byte
-             // sequence required for 16 bit timer registers
-             // See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
-             // Avrxmega3: write low byte first then high byte
-             // See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers
+             { Write to 16 bit ioreg, first high byte then low byte
+               sequence required for 16 bit timer registers
+               See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
+               Avrxmega3: write low byte first then high byte
+               See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers }
              if (current_settings.cputype <> cpu_avrxmega3) and
-               (fromsize in [OS_16, OS_S16]) and QuickRef and (href.offset > 31) and
-               (href.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
+               (fromsize in [OS_16, OS_S16]) and QuickRef and addr_is_io_register(href.offset) then
                begin
                  tmpreg:=GetNextReg(reg);
                  href.addressmode:=AM_UNCHANGED;
@@ -2357,7 +2364,9 @@ unit cgcpu;
          if ref.addressmode<>AM_UNCHANGED then
            internalerror(2011021706);
 
-        if assigned(ref.symbol) or (ref.offset<>0) then
+         if assigned(ref.symbol) or (ref.offset<>0) or
+           { If no other reference information it must imply an absolute reference to address 0 }
+           ((ref.index=NR_NO) and (ref.base=NR_NO)) then
           begin
             reference_reset(tmpref,0,[]);
             tmpref.symbol:=ref.symbol;
@@ -2598,24 +2607,21 @@ unit cgcpu;
                 dstref:=dest;
               end;
 
-              // CC
-              // If dest is an ioreg (31 < offset < srambase) and size = 16 bit then
-              // write high byte first, then low byte
-              // but not for avrxmega3
-              if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
-                (dest.offset > 31) and
-                (dest.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
-                begin
-                  // If src is also a 16 bit ioreg then read low byte then high byte
-                  if SrcQuickRef and (srcref.offset > 31)
-                    and (srcref.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
-                    begin
-                      // First read source into temp registers
-                      tmpreg:=getintregister(list, OS_16);
-                      list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
-                      inc(srcref.offset);
-                      tmpreg2:=GetNextReg(tmpreg);
-                      list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
+            { If dest is an ioreg and size = 16 bit then
+              write high byte first, then low byte
+              but not for avrxmega3 }
+            if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
+                addr_is_io_register(dest.offset) then
+              begin
+                // If src is also a 16 bit ioreg then read low byte then high byte
+                if SrcQuickRef and addr_is_io_register(srcref.offset) then
+                  begin
+                    // First read source into temp registers
+                    tmpreg:=getintregister(list, OS_16);
+                    list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
+                    inc(srcref.offset);
+                    tmpreg2:=GetNextReg(tmpreg);
+                    list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
 
                     // then move temp registers to dest in reverse order
                     inc(dstref.offset);
@@ -2625,8 +2631,20 @@ unit cgcpu;
                   end
                 else
                   begin
-                    srcref.addressmode:=AM_UNCHANGED;
-                    inc(srcref.offset);
+                    { avrtiny doesn't have LDD instruction, so use
+                      predecrement version of LD with pre-incremented pointer  }
+                    if current_settings.cputype = cpu_avrtiny then
+                      begin
+                        srcref.addressmode:=AM_PREDECREMENT;
+                        list.concat(taicpu.op_reg_const(A_SUBI,srcref.base,-2));
+                        list.concat(taicpu.op_reg_const(A_SBCI,GetNextReg(srcref.base),$FF));
+                      end
+                    else
+                      begin
+                        srcref.addressmode:=AM_UNCHANGED;
+                        inc(srcref.offset);
+                      end;
+
                     dstref.addressmode:=AM_UNCHANGED;
                     inc(dstref.offset);
 
@@ -2635,12 +2653,15 @@ unit cgcpu;
                     list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,GetDefaultTmpReg));
                     cg.ungetcpuregister(list,GetDefaultTmpReg);
 
-                    if not(SrcQuickRef) then
+                    if not(SrcQuickRef) and (current_settings.cputype <> cpu_avrtiny) then
                       srcref.addressmode:=AM_POSTINCREMENT
+                    else if current_settings.cputype = cpu_avrtiny then
+                      srcref.addressmode:=AM_PREDECREMENT
                     else
                       srcref.addressmode:=AM_UNCHANGED;
 
-                    dec(srcref.offset);
+                    if current_settings.cputype <> cpu_avrtiny then
+                      dec(srcref.offset);
                     dec(dstref.offset);
 
                     cg.getcpuregister(list,GetDefaultTmpReg);
@@ -2672,17 +2693,18 @@ unit cgcpu;
                   if DestQuickRef then
                     inc(dstref.offset);
                 end;
-              if not(SrcQuickRef) then
-                begin
-                  ungetcpuregister(list,srcref.base);
-                  ungetcpuregister(list,TRegister(ord(srcref.base)+1));
-                end;
-              if not(DestQuickRef) then
-                begin
-                  ungetcpuregister(list,dstref.base);
-                  ungetcpuregister(list,TRegister(ord(dstref.base)+1));
-                end;
-            end;
+
+            if not(SrcQuickRef) then
+              begin
+                ungetcpuregister(list,srcref.base);
+                ungetcpuregister(list,TRegister(ord(srcref.base)+1));
+              end;
+            if not(DestQuickRef) then
+              begin
+                ungetcpuregister(list,dstref.base);
+                ungetcpuregister(list,TRegister(ord(dstref.base)+1));
+              end;
+          end;
         end;
 
 

compiler/avr/cpubase.pas

@@ -53,7 +53,8 @@ unit cpubase;
         A_LSL,A_LSR,A_ROL,A_ROR,A_ASR,A_SWAP,A_BSET,A_BCLR,A_SBI,A_CBI,
         A_SEC,A_SEH,A_SEI,A_SEN,A_SER,A_SES,A_SET,A_SEV,A_SEZ,
         A_CLC,A_CLH,A_CLI,A_CLN,A_CLR,A_CLS,A_CLT,A_CLV,A_CLZ,
-        A_BST,A_BLD,A_BREAK,A_NOP,A_SLEEP,A_WDR,A_XCH);
+        A_BST,A_BLD,A_BREAK,A_NOP,A_SLEEP,A_WDR,A_XCH,
+        A_DES);
 
 
       { This should define the array of instructions as string }
@@ -159,7 +160,7 @@ unit cpubase;
                                 Operands
 *****************************************************************************}
 
-      taddressmode = (AM_UNCHANGED,AM_POSTINCREMENT,AM_PREDRECEMENT);
+      taddressmode = (AM_UNCHANGED,AM_POSTINCREMENT,AM_PREDECREMENT);
 
 {*****************************************************************************
                                  Constants

compiler/avr/itcpugas.pas

@@ -44,7 +44,8 @@ interface
         'lsl','lsr','rol','ror','asr','swap','bset','bclr','sbi','cbi',
         'sec','seh','sei','sen','ser','ses','set','sev','sez',
         'clc','clh','cli','cln','clr','cls','clt','clv','clz',
-        'bst','bld','break','nop','sleep','wdr','xch');
+        'bst','bld','break','nop','sleep','wdr','xch',
+        'des');
 
     function gas_regnum_search(const s:string):Tregister;
     function gas_regname(r:Tregister):string;

compiler/avr/navrinl.pas

@@ -40,6 +40,8 @@ unit navrinl;
   implementation
 
     uses
+      verbose,
+      constexp,
       compinnr,
       aasmdata,
       aasmcpu,
@@ -48,6 +50,7 @@ unit navrinl;
       hlcgobj,
       pass_2,
       cgbase, cgobj, cgutils,
+      ncon,ncal,
       cpubase;
 
     procedure tavrinlinenode.second_abs_long;
@@ -72,6 +75,8 @@ unit navrinl;
 
 
     function tavrinlinenode.pass_typecheck_cpu : tnode;
+      var
+        para1,para2,para3,para4: tcallparanode;
       begin
         Result:=nil;
         case inlinenumber of
@@ -94,6 +99,22 @@ unit navrinl;
               CheckParameters(1);
               resultdef:=voidtype;
             end;
+          in_avr_des:
+            begin
+              CheckParameters(4);
+              resultdef:=voidtype;
+              para4:=tcallparanode(left);
+              para3:=tcallparanode(tcallparanode(para4).nextpara);
+              para2:=tcallparanode(tcallparanode(para3).nextpara);
+              para1:=tcallparanode(tcallparanode(para2).nextpara);
+              if not(is_constintnode(para4.paravalue)) then
+                MessagePos(para4.paravalue.fileinfo,type_e_constant_expr_expected);
+              if not(is_constboolnode(para3.paravalue)) then
+                MessagePos(para3.paravalue.fileinfo,type_e_constant_expr_expected);
+              if (tordconstnode(para4.paravalue).value<0) or
+                (tordconstnode(para4.paravalue).value>15) then
+                MessagePos(para4.paravalue.fileinfo,parser_e_range_check_error);
+            end;
           else
             Result:=inherited pass_typecheck_cpu;
         end;
@@ -109,7 +130,8 @@ unit navrinl;
           in_avr_sei,
           in_avr_wdr,
           in_avr_cli,
-          in_avr_restore:
+          in_avr_restore,
+          in_avr_des:
             begin
               expectloc:=LOC_VOID;
               resultdef:=voidtype;
@@ -126,6 +148,10 @@ unit navrinl;
 
 
     procedure tavrinlinenode.pass_generate_code_cpu;
+      var
+        para1,para2,para3,para4: tcallparanode;
+        ref: treference;
+        r: TRegister;
       begin
         case inlinenumber of
           in_avr_nop:
@@ -152,6 +178,54 @@ unit navrinl;
               hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
               current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_OUT, NIO_SREG, left.location.register));
             end;
+          in_avr_des:
+            begin
+              para4:=tcallparanode(left);
+              para3:=tcallparanode(tcallparanode(para4).nextpara);
+              para2:=tcallparanode(tcallparanode(para3).nextpara);
+              para1:=tcallparanode(tcallparanode(para2).nextpara);
+              secondpass(tcallparanode(para1).paravalue);
+              secondpass(tcallparanode(para2).paravalue);
+
+              cg.getcpuregister(current_asmdata.CurrAsmList,NR_R30);
+              cg.getcpuregister(current_asmdata.CurrAsmList,NR_R31);
+
+              cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,tcallparanode(para2).paravalue.location.reference,NR_R30);
+              reference_reset(ref,0,[]);
+              ref.base:=NR_R30;
+              for r:=NR_R8 to NR_R15 do
+                begin
+                  cg.getcpuregister(current_asmdata.CurrAsmList,r);
+                  cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_8,OS_8,ref,r);
+                  inc(ref.offset);
+                end;
+              cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,tcallparanode(para1).paravalue.location.reference,NR_R30);
+              reference_reset(ref,0,[]);
+              ref.base:=NR_R30;
+              for r:=NR_R0 to NR_R7 do
+                begin
+                  cg.getcpuregister(current_asmdata.CurrAsmList,r);
+                  cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_8,OS_8,ref,r);
+                  inc(ref.offset);
+                end;
+              if tordconstnode(para3.paravalue).value=0 then
+                current_asmdata.CurrAsmList.concat(taicpu.op_none(A_CLH))
+              else
+                current_asmdata.CurrAsmList.concat(taicpu.op_none(A_SEH));
+              current_asmdata.CurrAsmList.concat(taicpu.op_const(A_DES,int64(tordconstnode(para4.paravalue).value)));
+
+              for r:=NR_R8 to NR_R15 do
+                cg.ungetcpuregister(current_asmdata.CurrAsmList,r);
+
+              { save data }
+              ref.offset:=0;
+              for r:=NR_R0 to NR_R7 do
+                begin
+                  cg.a_load_reg_ref(current_asmdata.CurrAsmList,OS_8,OS_8,r,ref);
+                  cg.ungetcpuregister(current_asmdata.CurrAsmList,r);
+                  inc(ref.offset);
+                end;
+            end
           else
             inherited pass_generate_code_cpu;
         end;

compiler/avr/raavr.pas

@@ -164,13 +164,13 @@ unit raavr;
        // Perhaps handle separately with a check on sub-architecture? Range check only important if smaller instruction code selected on larger arch
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 65535; min: 0))),
        // A_LD
-       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDRECEMENT]))),
+       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]))),
        // A_LDD
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63))),
        // A_STS TODO: See LDS above
        (numOperands: (1 shl 2); Operands: ((typ: top_const; max: 65535; min: 0), (typ: top_reg; rt: rt_all))),
        // A_ST
-       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDRECEMENT]), (typ: top_reg; rt: rt_all))),
+       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]), (typ: top_reg; rt: rt_all))),
        // A_STD
        (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63), (typ: top_reg; rt: rt_all))),
        // A_LPM
@@ -256,7 +256,9 @@ unit raavr;
        // A_WDR
        (numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
        // A_XCH
-       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_Z), (typ: top_reg; rt: rt_all)))
+       (numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_Z), (typ: top_reg; rt: rt_all))),
+       // A_DES
+       (numOperands: (1 shl 1); Operands: ((typ: top_const; max: 15; min: 0), (typ: top_none)))
        );
 {$POP}
 
@@ -346,7 +348,7 @@ unit raavr;
 
                         if not (err) and not(AM_UNCHANGED in AVRInstrConstraint[opcode].Operands[i].am) and
                           ((AM_POSTINCREMENT in AVRInstrConstraint[opcode].Operands[i].am) or
-                           (AM_PREDRECEMENT in AVRInstrConstraint[opcode].Operands[i].am)) then
+                           (AM_PREDECREMENT in AVRInstrConstraint[opcode].Operands[i].am)) then
                           err := not opregasref;
 
                         if not(err) and opregasref then

compiler/avr/raavrgas.pas

@@ -349,7 +349,7 @@ Unit raavrgas;
                 begin
                   { Special handling of predecrement addressing }
                   oper.InitRef;
-                  oper.opr.ref.addressmode:=AM_PREDRECEMENT;
+                  oper.opr.ref.addressmode:=AM_PREDECREMENT;
 
                   consume(AS_MINUS);
 

compiler/cclasses.pas

@@ -23,9 +23,7 @@ unit cclasses;
 
 {$i fpcdefs.inc}
 
-{$ifndef VER2_0}
-  {$define CCLASSESINLINE}
-{$endif}
+{$define CCLASSESINLINE}
 
 interface
 
@@ -77,6 +75,7 @@ type
   TListCallback = procedure(data,arg:pointer) of object;
   TListStaticCallback = procedure(data,arg:pointer);
   TDynStringArray = Array Of String;
+  TDirection = (FromBeginning,FromEnd);
   TFPList = class(TObject)
   private
     FList: PPointerList;
@@ -87,18 +86,20 @@ type
     procedure Put(Index: Integer; Item: Pointer);
     procedure SetCapacity(NewCapacity: Integer);
     procedure SetCount(NewCount: Integer);
-    Procedure RaiseIndexError(Index : Integer);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+    Procedure RaiseIndexError(Index : Integer);noreturn;
+    property List: PPointerList read FList;
   public
     destructor Destroy; override;
     function Add(Item: Pointer): Integer;
     procedure Clear;
     procedure Delete(Index: Integer);
-    class procedure Error(const Msg: string; Data: PtrInt);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+    class procedure Error(const Msg: string; Data: PtrInt);noreturn;
     procedure Exchange(Index1, Index2: Integer);
     function Expand: TFPList;
     function Extract(item: Pointer): Pointer;
     function First: Pointer;
     function IndexOf(Item: Pointer): Integer;
+    function IndexOfItem(Item: Pointer; Direction: TDirection): Integer;
     procedure Insert(Index: Integer; Item: Pointer);
     function Last: Pointer;
     procedure Move(CurIndex, NewIndex: Integer);
@@ -111,7 +112,6 @@ type
     property Capacity: Integer read FCapacity write SetCapacity;
     property Count: Integer read FCount write SetCount;
     property Items[Index: Integer]: Pointer read Get write Put; default;
-    property List: PPointerList read FList;
   end;
 
 
@@ -145,6 +145,7 @@ type
     function Extract(Item: TObject): TObject; {$ifdef CCLASSESINLINE}inline;{$endif}
     function Remove(AObject: TObject): Integer;
     function IndexOf(AObject: TObject): Integer; {$ifdef CCLASSESINLINE}inline;{$endif}
+    function IndexOfItem(AObject: TObject; Direction: TDirection): Integer; {$ifdef CCLASSESINLINE}inline;{$endif}
     function FindInstanceOf(AClass: TClass; AExact: Boolean; AStartAt: Integer): Integer;
     procedure Insert(Index: Integer; AObject: TObject); {$ifdef CCLASSESINLINE}inline;{$endif}
     function First: TObject; {$ifdef CCLASSESINLINE}inline;{$endif}
@@ -224,7 +225,7 @@ type
     function HashOfIndex(Index: Integer): LongWord;
     function GetNextCollision(Index: Integer): Integer;
     procedure Delete(Index: Integer);
-    class procedure Error(const Msg: string; Data: PtrInt);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+    class procedure Error(const Msg: string; Data: PtrInt);noreturn;
     function Expand: TFPHashList;
     function Extract(item: Pointer): Pointer;
     function IndexOf(Item: Pointer): Integer;
@@ -715,7 +716,7 @@ implementation
                TFPObjectList (Copied from rtl/objpas/classes/lists.inc)
 *****************************************************************************}
 
-procedure TFPList.RaiseIndexError(Index : Integer);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+procedure TFPList.RaiseIndexError(Index : Integer);noreturn;
 begin
   Error(SListIndexError, Index);
 end;
@@ -811,7 +812,7 @@ begin
   end;
 end;
 
-class procedure TFPList.Error(const Msg: string; Data: PtrInt);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+class procedure TFPList.Error(const Msg: string; Data: PtrInt);noreturn;
 begin
   Raise EListError.CreateFmt(Msg,[Data]) at get_caller_addr(get_frame), get_caller_frame(get_frame);
 end;
@@ -872,6 +873,32 @@ begin
     end;
 end;
 
+function TFPList.IndexOfItem(Item: Pointer; Direction: TDirection): Integer;
+var
+  psrc  : PPointer;
+  Index : Integer;
+begin
+  if Direction=FromBeginning then
+    Result:=IndexOf(Item)
+  else
+    begin
+      Result:=-1;
+      if FCount>0 then
+        begin
+          psrc:=@FList^[FCount-1];
+          For Index:=FCount-1 downto 0 Do
+            begin
+              if psrc^=Item then
+                begin
+                  Result:=Index;
+                  exit;
+                end;
+              dec(psrc);
+            end;
+        end;
+    end;
+end;
+
 procedure TFPList.Insert(Index: Integer; Item: Pointer);
 begin
   if (Index < 0) or (Index > FCount )then
@@ -1058,6 +1085,11 @@ begin
   Result := FList.IndexOf(Pointer(AObject));
 end;
 
+function TFPObjectList.IndexOfItem(AObject: TObject; Direction: TDirection): Integer; {$ifdef CCLASSESINLINE}inline;{$endif}
+begin
+  Result := FList.IndexOfItem(Pointer(AObject),Direction);
+end;
+
 function TFPObjectList.GetCount: integer;
 begin
   Result := FList.Count;
@@ -1510,7 +1542,7 @@ begin
     Self.Delete(Result);
 end;
 
-class procedure TFPHashList.Error(const Msg: string; Data: PtrInt);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+class procedure TFPHashList.Error(const Msg: string; Data: PtrInt);noreturn;
 begin
   Raise EListError.CreateFmt(Msg,[Data])  at get_caller_addr(get_frame), get_caller_frame(get_frame);
 end;

compiler/cfidwarf.pas

@@ -301,6 +301,13 @@ implementation
         list.concat(tai_const.create_uleb128bit(dwarf_reg(NR_STACK_POINTER_REG)));
         list.concat(tai_const.create_uleb128bit(0));
       end;
+{$elseif defined(riscv)}
+    procedure TDwarfAsmCFILowLevel.generate_initial_instructions(list:TAsmList);
+      begin
+        list.concat(tai_const.create_8bit(DW_CFA_def_cfa));
+        list.concat(tai_const.create_uleb128bit(dwarf_reg(NR_STACK_POINTER_REG)));
+        list.concat(tai_const.create_uleb128bit(0));
+      end;
 {$else}
     { if more cpu dependend stuff is implemented, this needs more refactoring }
     procedure TDwarfAsmCFILowLevel.generate_initial_instructions(list:TAsmList);
@@ -663,6 +670,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_none.create(cfi_startproc));
       end;
 
@@ -674,6 +683,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_none.create(cfi_endproc));
       end;
 
@@ -685,6 +696,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_reg.create(cfi_undefined,NR_RETURN_ADDRESS_REG));
       end;
 
@@ -696,6 +709,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_reg_val.create(cfi_offset,reg,ofs));
       end;
 
@@ -707,6 +722,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_reg.create(cfi_restore,reg));
       end;
 
@@ -718,6 +735,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_reg.create(cfi_def_cfa_register,reg));
       end;
 
@@ -729,6 +748,8 @@ implementation
             inherited;
             exit;
           end;
+        if not(af_supports_hlcfi in target_asm.flags) then
+          exit;
         list.concat(tai_cfi_op_val.create(cfi_def_cfa_offset,ofs));
       end;
 

compiler/cgbase.pas

@@ -99,7 +99,9 @@ interface
          addr_lo12,
          addr_pcrel_hi20,
          addr_pcrel_lo12,
-         addr_pcrel
+         addr_pcrel,
+         addr_got_pcrel_hi,
+         addr_plt
          {$endif RISCV}
          {$IFDEF AVR}
          ,addr_lo8
@@ -320,10 +322,6 @@ interface
       end;
 {$endif cpu64bitalu}
 
-      Tregistermmxset = record
-        reg0,reg1,reg2,reg3:Tregister
-      end;
-
       { Set type definition for registers }
       tsuperregisterset = array[byte] of set of byte;
 

compiler/cgexcept.pas

@@ -129,12 +129,13 @@ unit cgexcept;
        be modified, all temps should be allocated on the heap instead of the
        stack. }
 
-
     class procedure tcgexceptionstatehandler.get_exception_temps(list:TAsmList;var t:texceptiontemps);
-     begin
+      begin
+        if not assigned(exceptionreasontype) then
+          exceptionreasontype:=search_system_proc('fpc_setjmp').returndef;
         tg.gethltemp(list,rec_exceptaddr,rec_exceptaddr.size,tt_persistent,t.envbuf);
         tg.gethltemp(list,rec_jmp_buf,rec_jmp_buf.size,tt_persistent,t.jmpbuf);
-        tg.gethltemp(list,ossinttype,ossinttype.size,tt_persistent,t.reasonbuf);
+        tg.gethltemp(list,exceptionreasontype,exceptionreasontype.size,tt_persistent,t.reasonbuf);
       end;
 
 
@@ -207,7 +208,7 @@ unit cgexcept;
         location_reset(tmpresloc,LOC_REGISTER,def_cgsize(setjmpres.def));
         tmpresloc.register:=hlcg.getintregister(list,setjmpres.def);
         hlcg.gen_load_cgpara_loc(list,setjmpres.def,setjmpres,tmpresloc,true);
-        hlcg.g_exception_reason_save(list,setjmpres.def,ossinttype,tmpresloc.register,t.reasonbuf);
+        hlcg.g_exception_reason_save(list,setjmpres.def,exceptionreasontype,tmpresloc.register,t.reasonbuf);
         { if we get 1 here in the function result register, it means that we
           longjmp'd back here }
         hlcg.a_cmp_const_reg_label(list,setjmpres.def,OC_NE,0,tmpresloc.register,exceptstate.exceptionlabel);
@@ -237,9 +238,9 @@ unit cgexcept;
          popaddrstack(list);
          if not onlyfree then
           begin
-            reasonreg:=hlcg.getintregister(list,osuinttype);
-            hlcg.g_exception_reason_load(list,osuinttype,osuinttype,t.reasonbuf,reasonreg);
-            hlcg.a_cmp_const_reg_label(list,osuinttype,OC_EQ,a,reasonreg,endexceptlabel);
+            reasonreg:=hlcg.getintregister(list,exceptionreasontype);
+            hlcg.g_exception_reason_load(list,exceptionreasontype,exceptionreasontype,t.reasonbuf,reasonreg);
+            hlcg.a_cmp_const_reg_label(list,exceptionreasontype,OC_EQ,a,reasonreg,endexceptlabel);
           end;
       end;
 

compiler/cgutils.pas

@@ -192,12 +192,12 @@ unit cgutils;
     {# Clear to zero a treference, and set is base address
        to base register.
     }
-    procedure reference_reset_base(var ref : treference;base : tregister;offset : longint; temppos : treftemppos; alignment : longint; volatility: tvolatilityset);
-    procedure reference_reset_symbol(var ref : treference;sym : tasmsymbol;offset, alignment : longint; volatility: tvolatilityset);
+    procedure reference_reset_base(var ref: treference; base: tregister; offset: asizeint; temppos: treftemppos; alignment: longint; volatility: tvolatilityset);
+    procedure reference_reset_symbol(var ref: treference;sym: tasmsymbol; offset: asizeint; alignment : longint; volatility: tvolatilityset);
     { This routine verifies if two references are the same, and
        if so, returns TRUE, otherwise returns false.
     }
-    function references_equal(const sref,dref : treference) : boolean;
+    function references_equal(const sref,dref : treference) : boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
 
     { tlocation handling }
 
@@ -244,7 +244,7 @@ uses
       end;
 
 
-    procedure reference_reset_base(var ref: treference; base: tregister; offset : longint; temppos : treftemppos ; alignment : longint; volatility: tvolatilityset);
+    procedure reference_reset_base(var ref: treference; base: tregister; offset: asizeint; temppos: treftemppos ; alignment: longint; volatility: tvolatilityset);
       begin
         reference_reset(ref,alignment,volatility);
         ref.base:=base;
@@ -253,7 +253,7 @@ uses
       end;
 
 
-    procedure reference_reset_symbol(var ref: treference; sym: tasmsymbol; offset, alignment: longint; volatility: tvolatilityset);
+    procedure reference_reset_symbol(var ref: treference; sym: tasmsymbol; offset: asizeint; alignment: longint; volatility: tvolatilityset);
       begin
         reference_reset(ref,alignment,volatility);
         ref.symbol:=sym;
@@ -262,7 +262,7 @@ uses
       end;
 
 
-    function references_equal(const sref,dref : treference):boolean;
+    function references_equal(const sref,dref : treference):boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
       begin
         references_equal:=CompareByte(sref,dref,sizeof(treference))=0;
       end;

compiler/compinnr.pas

@@ -202,6 +202,10 @@ type
 {$if defined(Z80)}
      ,
      {$i ccpuinnr.inc}
+{$endif}
+{$if defined(WASM32)}
+     ,
+     {$i ccpuinnr.inc}
 {$endif}
    );
 

compiler/comptty.pas

@@ -30,19 +30,19 @@ function IsATTY(var t : text) : Boolean;
 
 const
 (* This allows compile-time removal of the colouring functionality under not supported platforms *)
-{$if defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+{$if defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM) or defined(DARWIN)}
   TTYCheckSupported = true;
-{$else defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+{$else defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM) or defined(DARWIN)}
   TTYCheckSupported = false;
-{$endif defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM)}
+{$endif defined(linux) or defined(MSWINDOWS) or defined(OS2) or defined(GO32V2) or defined(WATCOM) or defined(DARWIN)}
 
 
 implementation
 
-{$ifdef linux}
+{$if defined(linux) or defined(darwin)}
   uses
    termio;
-{$endif linux}
+{$endif defined(linux) or defined(darwin)}
 {$ifdef mswindows}
   uses
    windows;
@@ -60,12 +60,12 @@ const
   CachedIsATTY : Boolean = false;
   IsATTYValue : Boolean = false;
 
-{$ifdef linux}
+{$if defined(linux) or defined(darwin)}
 function LinuxIsATTY(var t : text) : Boolean; inline;
 begin
   LinuxIsATTY:=termio.IsATTY(t)=1;
 end;
-{$endif linux}
+{$endif defined(linux) or defined(darwin)}
 
 {$ifdef MSWINDOWS}
 const
@@ -152,9 +152,9 @@ begin
   if not(CachedIsATTY) then
     begin
 (* If none of the supported values is defined, false is returned by default. *)
-{$ifdef linux}
+{$if defined(linux) or defined(darwin)}
       IsATTYValue:=LinuxIsATTY(t);
-{$endif linux}
+{$endif defined(linux) or defined(darwin)}
 {$ifdef MSWINDOWS}
       IsATTYValue:=WindowsIsATTY(t);
 {$endif MSWINDOWS}

compiler/constexp.pas

@@ -90,7 +90,7 @@ implementation
 { use a separate procedure here instead of calling internalerrorproc directly because
   - procedure variables cannot have a noreturn directive
   - having a procedure and a procedure variable with the same name in the interfaces of different units is confusing }
-procedure internalerror(i:longint);{$ifndef VER2_6}noreturn;{$endif VER2_6}
+procedure internalerror(i:longint);noreturn;
 
 begin
   internalerrorproc(i);
@@ -196,10 +196,6 @@ try_qword:
   result.overflow:=true;
 end;
 
-{ workaround for 2.6.x bug }
-{$ifdef VER2_6}
-    {$push} {$Q-}
-{$endif VER2_6}
 function sub_from(const a:Tconstexprint;b:qword):Tconstexprint;
 
 const abs_low_int64=qword(9223372036854775808);   {abs(low(int64)) -> overflow error}
@@ -244,10 +240,6 @@ try_qword:
 ov:
   result.overflow:=true;
 end;
-{ workaround for 2.6.x bug }
-{$ifdef VER2_6}
-    {$pop}
-{$endif VER2_6}
 
 operator + (const a,b:Tconstexprint):Tconstexprint;
 

compiler/cscript.pas

@@ -91,6 +91,7 @@ type
   TLinkRes = Class (TScript)
     section: string[30];
     fRealResponseFile: Boolean;
+    fForceUseForwardSlash: Boolean;
     constructor Create(const ScriptName : TCmdStr; RealResponseFile: Boolean);
     procedure Add(const s:TCmdStr);
     procedure AddFileName(const s:TCmdStr);
@@ -497,6 +498,7 @@ constructor TLinkRes.Create(const ScriptName: TCmdStr; RealResponseFile: Boolean
 begin
   inherited Create(ScriptName);
   fRealResponseFile:=RealResponseFile;
+  fForceUseForwardSlash:=false;
 end;
 
 procedure TLinkRes.Add(const s:TCmdStr);
@@ -506,6 +508,9 @@ begin
 end;
 
 procedure TLinkRes.AddFileName(const s:TCmdStr);
+var
+  ls: TCmdStr;
+  i: longint;
 begin
   if section<>'' then
    begin
@@ -514,23 +519,31 @@ begin
    end;
   if s<>'' then
    begin
+     ls:=s;
+     if fForceUseForwardSlash then
+       { Fix separator }
+       for i:=1 to length(ls) do
+         if (ls[i]=source_info.dirsep) then
+           ls[i]:='/';
      { GNU ld only supports double quotes in the response file. }
      if fRealResponseFile and
-        (s[1]='''') and
+        (ls[1]='''') and
         (((cs_link_on_target in current_settings.globalswitches) and
           (target_info.script=script_unix)) or
          (not(cs_link_on_target in current_settings.globalswitches) and
           (source_info.script=script_unix))) then
        inherited add(UnixRequoteWithDoubleQuotes(s))
-     else if not(s[1] in ['a'..'z','A'..'Z','/','\','.','"']) then
+     else if not(ls[1] in ['a'..'z','A'..'Z','/','\','.','"']) then
       begin
-        if cs_link_on_target in current_settings.globalswitches then
-          inherited Add('.'+target_info.DirSep+s)
+        if fForceUseForwardSlash then
+          inherited Add('./'+ls)
+        else if (cs_link_on_target in current_settings.globalswitches) then
+          inherited Add('.'+target_info.DirSep+ls)
         else
-          inherited Add('.'+source_info.DirSep+s);
+          inherited Add('.'+source_info.DirSep+ls);
       end
      else
-      inherited Add(s);
+      inherited Add(ls);
    end;
 end;
 

compiler/cutils.pas

@@ -117,12 +117,6 @@ interface
     }
     function isabspowerof2(const value : Tconstexprint;out power : longint) : boolean;
     function nextpowerof2(value : int64; out power: longint) : int64;
-{$ifdef VER2_6}  { only 2.7.1+ has a popcnt function in the system unit }
-    function PopCnt(AValue : Byte): Byte;
-    function PopCnt(AValue : Word): Word;
-    function PopCnt(AValue : DWord): DWord;
-    function PopCnt(Const AValue : QWord): QWord;
-{$endif VER2_6}
 
     function backspace_quote(const s:string;const qchars:Tcharset):string;
     function octal_quote(const s:string;const qchars:Tcharset):string;
@@ -1015,48 +1009,6 @@ implementation
           end;
       end;
 
-{$ifdef VER2_6}
-    const
-      PopCntData : array[0..15] of byte = (0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4);
-
-    function PopCnt(AValue : Byte): Byte;
-      begin
-        Result:=PopCntData[AValue and $f]+PopCntData[(AValue shr 4) and $f];
-      end;
-
-
-    function PopCnt(AValue : Word): Word;
-      var
-        i : SizeInt;
-      begin
-        Result:=0;
-        for i:=0 to 3 do
-          begin
-            inc(Result,PopCntData[AValue and $f]);
-            AValue:=AValue shr 4;
-          end;
-      end;
-
-
-    function PopCnt(AValue : DWord): DWord;
-      var
-        i : SizeInt;
-      begin
-        Result:=0;
-        for i:=0 to 7 do
-          begin
-            inc(Result,PopCntData[AValue and $f]);
-            AValue:=AValue shr 4;
-          end;
-      end;
-
-
-    function PopCnt(Const AValue : QWord): QWord;
-      begin
-        Result:=PopCnt(lo(AValue))+PopCnt(hi(AValue))
-      end;
- {$endif VER2_6}
-
 
     function backspace_quote(const s:string;const qchars:Tcharset):string;
 
@@ -1298,9 +1250,10 @@ implementation
           { if one of the two is at the end while the other isn't, add a '.0' }
           if (i1>length(s1)) and
              (i2<=length(s2)) then
-            s1:=s1+'.0'
-          else if i2>length(s2) then
-            s2:=s2+'.0';
+            s1:=s1+'.0';
+          if (i2>length(s2)) and
+             (i1<=length(s1)) then
+             s2:=s2+'.0';
           { compare non-numerical characters normally }
           while (i1<=length(s1)) and
                 not(s1[i1] in ['0'..'9']) and

compiler/dbgdwarf.pas

@@ -683,7 +683,10 @@ implementation
         DW_OP_HP_unknown := $e0,
         DW_OP_HP_is_value := $e1,DW_OP_HP_fltconst4 := $e2,
         DW_OP_HP_fltconst8 := $e3,DW_OP_HP_mod_range := $e4,
-        DW_OP_HP_unmod_range := $e5,DW_OP_HP_tls := $e6
+        DW_OP_HP_unmod_range := $e5,DW_OP_HP_tls := $e6,
+
+        { WebAssembly extensions. }
+        DW_OP_WASM_location = $ed
         );
 {$pop}
 
@@ -1055,12 +1058,14 @@ implementation
 
     function TDebugInfoDwarf.is_fbreg(reg: tregister): boolean;
       begin
-{$ifdef i8086}
+{$if defined(i8086)}
         result:=reg=NR_BP;
-{$else i8086}
+{$elseif defined(wasm)}
+        result:=reg=NR_LOCAL_FRAME_POINTER_REG;
+{$else}
         { always return false, because we don't emit DW_AT_frame_base attributes yet }
         result:=false;
-{$endif i8086}
+{$endif}
       end;
 
     function TDebugInfoDwarf.def_dwarf_lab(def: tdef): tasmsymbol;
@@ -2243,6 +2248,9 @@ implementation
       var
         labsym : tasmsymbol;
       begin
+        { end of the symbol }
+        labsym:=def_dwarf_lab(def);
+        current_asmdata.asmlists[al_dwarf_info].concat(tai_symbol_end.Create(labsym));
         { create a derived reference type for pass-by-reference parameters }
         { (gdb doesn't support DW_AT_variable_parameter yet)               }
         labsym:=def_dwarf_ref_lab(def);
@@ -3252,30 +3260,33 @@ implementation
         flist : TFPList;
         dbgname : String;
       begin
-        { insert DEBUGSTART and DEBUGEND labels }
-        dbgname:=make_mangledname('DEBUGSTART',current_module.localsymtable,'');
-        { Darwin's linker does not like two global labels both pointing to the
-          end of a section, which can happen in case of units without code ->
-          make them local; we don't need the debugtable stuff there either,
-          so it doesn't matter that they are not global.
-        }
-        if (target_info.system in systems_darwin) then
-          dbgname:='L'+dbgname;
-        new_section(current_asmdata.asmlists[al_start],sec_code,dbgname,0,secorder_begin);
-        if not(target_info.system in systems_darwin) then
-          current_asmdata.asmlists[al_start].concat(tai_symbol.Createname_global(dbgname,AT_METADATA,0,voidpointertype))
-        else
-          current_asmdata.asmlists[al_start].concat(tai_symbol.Createname(dbgname,AT_METADATA,0,voidpointertype));
+        if not (target_info.system in systems_wasm) then
+          begin
+            { insert DEBUGSTART and DEBUGEND labels }
+            dbgname:=make_mangledname('DEBUGSTART',current_module.localsymtable,'');
+            { Darwin's linker does not like two global labels both pointing to the
+              end of a section, which can happen in case of units without code ->
+              make them local; we don't need the debugtable stuff there either,
+              so it doesn't matter that they are not global.
+            }
+            if (target_info.system in systems_darwin) then
+              dbgname:='L'+dbgname;
+            new_section(current_asmdata.asmlists[al_start],sec_code,dbgname,0,secorder_begin);
+            if not(target_info.system in systems_darwin) then
+              current_asmdata.asmlists[al_start].concat(tai_symbol.Createname_global(dbgname,AT_METADATA,0,voidpointertype))
+            else
+              current_asmdata.asmlists[al_start].concat(tai_symbol.Createname(dbgname,AT_METADATA,0,voidpointertype));
 
-        dbgname:=make_mangledname('DEBUGEND',current_module.localsymtable,'');
-        { See above. }
-        if (target_info.system in systems_darwin) then
-          dbgname:='L'+dbgname;
-        new_section(current_asmdata.asmlists[al_end],sec_code,dbgname,0,secorder_end);
-        if not(target_info.system in systems_darwin) then
-          current_asmdata.asmlists[al_end].concat(tai_symbol.Createname_global(dbgname,AT_METADATA,0,voidpointertype))
-        else
-          current_asmdata.asmlists[al_end].concat(tai_symbol.Createname(dbgname,AT_METADATA,0,voidpointertype));
+            dbgname:=make_mangledname('DEBUGEND',current_module.localsymtable,'');
+            { See above. }
+            if (target_info.system in systems_darwin) then
+              dbgname:='L'+dbgname;
+            new_section(current_asmdata.asmlists[al_end],sec_code,dbgname,0,secorder_end);
+            if not(target_info.system in systems_darwin) then
+              current_asmdata.asmlists[al_end].concat(tai_symbol.Createname_global(dbgname,AT_METADATA,0,voidpointertype))
+            else
+              current_asmdata.asmlists[al_end].concat(tai_symbol.Createname(dbgname,AT_METADATA,0,voidpointertype));
+          end;
 
         { insert .Ldebug_abbrev0 label }
         templist:=TAsmList.create;
@@ -3570,19 +3581,27 @@ implementation
         if (m_objectivec1 in current_settings.modeswitches) then
           append_attribute(DW_AT_APPLE_major_runtime_vers,DW_FORM_data1,[1]);
 
-        dbgname:=make_mangledname('DEBUGSTART',current_module.localsymtable,'');
-        if (target_info.system in systems_darwin) then
+        if target_info.system in systems_wasm then
           begin
-            bind:=AB_LOCAL;
-            dbgname:='L'+dbgname;
+            append_attribute(DW_AT_low_pc,DW_FORM_data4,[0]);
+            { todo: append DW_AT_ranges }
           end
         else
-          bind:=AB_GLOBAL;
-        append_labelentry(DW_AT_low_pc,current_asmdata.DefineAsmSymbol(dbgname,bind,AT_METADATA,voidpointertype));
-        dbgname:=make_mangledname('DEBUGEND',current_module.localsymtable,'');
-        if (target_info.system in systems_darwin) then
-          dbgname:='L'+dbgname;
-        append_labelentry(DW_AT_high_pc,current_asmdata.DefineAsmSymbol(dbgname,bind,AT_METADATA,voidpointertype));
+          begin
+            dbgname:=make_mangledname('DEBUGSTART',current_module.localsymtable,'');
+            if (target_info.system in systems_darwin) then
+              begin
+                bind:=AB_LOCAL;
+                dbgname:='L'+dbgname;
+              end
+            else
+              bind:=AB_GLOBAL;
+            append_labelentry(DW_AT_low_pc,current_asmdata.DefineAsmSymbol(dbgname,bind,AT_METADATA,voidpointertype));
+            dbgname:=make_mangledname('DEBUGEND',current_module.localsymtable,'');
+            if (target_info.system in systems_darwin) then
+              dbgname:='L'+dbgname;
+            append_labelentry(DW_AT_high_pc,current_asmdata.DefineAsmSymbol(dbgname,bind,AT_METADATA,voidpointertype));
+          end;
 
         finish_entry;
 
@@ -3666,7 +3685,7 @@ implementation
       begin
         { Reference all DEBUGINFO sections from the main .fpc section }
         { to prevent eliminating them by smartlinking                 }
-        if (target_info.system in ([system_powerpc_macosclassic]+systems_darwin)) then
+        if (target_info.system in ([system_powerpc_macosclassic]+systems_darwin+systems_wasm)) then
           exit;
         new_section(list,sec_fpc,'links',0);
 
@@ -4521,6 +4540,12 @@ implementation
 
       begin
         case def.objecttype of
+          odt_objcclass,
+          odt_objcprotocol:
+            begin
+              inherited;
+              exit
+            end;
           odt_cppclass,
           odt_object:
             begin
@@ -4584,34 +4609,39 @@ implementation
 
     procedure TDebugInfoDwarf3.appenddef_variant(list:TAsmList;def: tvariantdef);
       const
-        VARIANTS: array[1..27] of record Value: Word; Name: String end = (
-          (value:0;     name:''),
-          (value:1;     name:''),
-          (value:2;     name:'VSMALLINT'),
-          (value:3;     name:'VINTEGER'),
-          (value:4;     name:'VSINGLE'),
-          (value:5;     name:'VDOUBLE'),
-          (value:6;     name:'VCURRENCY'),
-          (value:7;     name:'VDATE'),
-          (value:8;     name:'VOLESTR'),
-          (value:9;     name:'VDISPATCH'),
-          (value:10;    name:'VERROR'),
-          (value:11;    name:'VBOOLEAN'),
-          (value:12;    name:''),
-          (value:13;    name:'VUNKNOWN'),
-          (value:14;    name:''),
-          (value:16;    name:'VSHORTINT'),
-          (value:17;    name:'VBYTE'),
-          (value:18;    name:'VWORD'),
-          (value:19;    name:'VLONGWORD'),
-          (value:20;    name:'VINT64'),
-          (value:21;    name:'VQWORD'),
-          (value:36;    name:'VRECORD'),
-          (value:$48;   name:''),
-          (value:$100;  name:'VSTRING'),
-          (value:$101;  name:'VANY'),
-          (value:$2000; name:'VARRAY'),
-          (value:$4000; name:'VPOINTER')
+        VARIANTS: array[1..27] of record
+          Value: Word;
+          Name: String;
+          { some fields are only supported by some features }
+          features : tfeatures
+        end = (
+          (value:0;     name:'';features: []),
+          (value:1;     name:'';features: []),
+          (value:2;     name:'VSMALLINT';features: []),
+          (value:3;     name:'VINTEGER';features: []),
+          (value:4;     name:'VSINGLE';features: [f_softfpu]),
+          (value:5;     name:'VDOUBLE';features: [f_softfpu]),
+          (value:6;     name:'VCURRENCY';features: [f_softfpu]),
+          (value:7;     name:'VDATE';features: [f_softfpu]),
+          (value:8;     name:'VOLESTR';features: []),
+          (value:9;     name:'VDISPATCH';features: []),
+          (value:10;    name:'VERROR';features: []),
+          (value:11;    name:'VBOOLEAN';features: []),
+          (value:12;    name:'';features: []),
+          (value:13;    name:'VUNKNOWN';features: []),
+          (value:14;    name:'';features: []),
+          (value:16;    name:'VSHORTINT';features: []),
+          (value:17;    name:'VBYTE';features: []),
+          (value:18;    name:'VWORD';features: []),
+          (value:19;    name:'VLONGWORD';features: []),
+          (value:20;    name:'VINT64';features: []),
+          (value:21;    name:'VQWORD';features: []),
+          (value:36;    name:'VRECORD';features: []),
+          (value:$48;   name:'';features: []),
+          (value:$100;  name:'VSTRING';features: []),
+          (value:$101;  name:'VANY';features: []),
+          (value:$2000; name:'VARRAY';features: []),
+          (value:$4000; name:'VPOINTER';features: [])
         );
       var
         fs: tfieldvarsym;
@@ -4644,20 +4674,23 @@ implementation
         { variants }
         for idx := Low(VARIANTS) to High(VARIANTS) do
           begin
-            append_entry(DW_TAG_variant,true,[
-              DW_AT_discr_value,DW_FORM_udata,VARIANTS[idx].value
-              ]);
-            finish_entry;
-
-            if VARIANTS[idx].name <> '' then
+            if (features*VARIANTS[idx].features)=VARIANTS[idx].features then
               begin
-                fs := tfieldvarsym(vardatadef.symtable.Find(VARIANTS[idx].name));
-                if (fs = nil) or (fs.typ <> fieldvarsym) then
-                  internalerror(20060927200+idx);
-                appendsym_fieldvar(list,fs);
-              end;
+                append_entry(DW_TAG_variant,true,[
+                  DW_AT_discr_value,DW_FORM_udata,VARIANTS[idx].value
+                  ]);
+                finish_entry;
 
-            finish_children; { variant }
+                if VARIANTS[idx].name <> '' then
+                  begin
+                    fs := tfieldvarsym(vardatadef.symtable.Find(VARIANTS[idx].name));
+                    if (fs = nil) or (fs.typ <> fieldvarsym) then
+                      internalerror(2006092702+idx);
+                    appendsym_fieldvar(list,fs);
+                  end;
+
+                finish_children; { variant }
+              end;
           end;
 
 

compiler/defutil.pas

@@ -149,6 +149,9 @@ interface
     {# Returns true, if p points to an array of const }
     function is_array_of_const(p : tdef) : boolean;
 
+    {# Returns true if p is an arraydef that describes a constant string }
+    function is_conststring_array(p : tdef) : boolean;
+
     {# Returns true, if p points any kind of special array
 
        That is if the array is an open array, a variant
@@ -796,8 +799,7 @@ implementation
            range is also -1 ! (PFV) }
          result:=(p.typ=arraydef) and
                  (tarraydef(p).rangedef=sizesinttype) and
-                 (tarraydef(p).lowrange=0) and
-                 (tarraydef(p).highrange=-1) and
+                 (ado_OpenArray in tarraydef(p).arrayoptions) and
                  ((tarraydef(p).arrayoptions * [ado_IsVariant,ado_IsArrayOfConst,ado_IsConstructor,ado_IsDynamicArray])=[]);
       end;
 
@@ -822,6 +824,12 @@ implementation
                  (ado_IsArrayOfConst in tarraydef(p).arrayoptions);
       end;
 
+    function is_conststring_array(p: tdef): boolean;
+      begin
+        result:=(p.typ=arraydef) and
+                (ado_IsConstString in tarraydef(p).arrayoptions);
+      end;
+
     { true, if p points to a special array, bitpacked arrays aren't special in this regard though }
     function is_special_array(p : tdef) : boolean;
       begin

compiler/entfile.pas

@@ -156,7 +156,7 @@ const
     { 14 } 32 {'jvm'},
     { 15 } 16 {'i8086'},
     { 16 } 64 {'aarch64'},
-    { 17 } 32 {'wasm'},
+    { 17 } 32 {'wasm32'},
     { 18 } 64 {'sparc64'},
     { 19 } 32 {'riscv32'},
     { 20 } 64 {'riscv64'},
@@ -182,7 +182,7 @@ const
     { 14 } 64 {'jvm'},
     { 15 } 16 {'i8086'},
     { 16 } 64 {'aarch64'},
-    { 17 } 64 {'wasm'},
+    { 17 } 64 {'wasm32'},
     { 18 } 64 {'sparc64'},
     { 19 } 32 {'riscv32'},
     { 20 } 64 {'riscv64'},
@@ -380,6 +380,11 @@ end;
 destructor tentryfile.destroy;
 begin
   closefile;
+{$ifdef DEBUG_PPU}
+  if flog_open then
+    close(flog);
+  flog_open:=false;
+{$endif DEBUG_PPU}
   if assigned(buf) then
     freemem(buf,entryfilebufsize);
 end;
@@ -573,11 +578,6 @@ begin
        f.Free;
      mode:=0;
      closed:=true;
-{$ifdef DEBUG_PPU}
-     if flog_open then
-       close(flog);
-     flog_open:=false;
-{$endif DEBUG_PPU}
    end;
 end;
 
@@ -683,14 +683,6 @@ var
 begin
   p:=pchar(@b);
   pbuf:=@buf[bufidx];
-{$ifdef DEBUG_PPU}
-  if ppu_log_level <= 0 then
-    begin
-      ppu_log('writedata, length='+tostr(len)+' level='+tostr(ppu_log_level));
-      for i:=0 to len-1 do
-        ppu_log_val('p['+tostr(i)+']=$'+hexstr(byte(p[i]),2));
-    end;
-{$endif DEBUG_PPU}
   repeat
     left:=bufsize-bufidx;
     if len<left then
@@ -704,6 +696,14 @@ begin
       exit;
   until false;
   move(pbuf^,p^,len);
+{$ifdef DEBUG_PPU}
+  if ppu_log_level <= 0 then
+    begin
+      ppu_log('writedata, length='+tostr(len)+' level='+tostr(ppu_log_level));
+      for i:=0 to len-1 do
+        ppu_log_val('p['+tostr(i)+']=$'+hexstr(byte(p[i]),2));
+    end;
+{$endif DEBUG_PPU}
   inc(bufidx,len);
 end;
 

compiler/fmodule.pas

@@ -299,7 +299,7 @@ implementation
       SysUtils,globals,
       verbose,systems,
       scanner,ppu,dbgbase,
-      procinfo,symdef;
+      procinfo,symdef,symtype;
 
 {$ifdef MEMDEBUG}
     var
@@ -731,7 +731,14 @@ implementation
         memsymtable.start;
 {$endif}
         derefdata.free;
-        deflist.free;
+        if assigned(deflist) then
+          begin
+            for i:=0 to deflist.Count-1 do
+              if assigned(deflist[i]) and
+                 (tdef(deflist[i]).registered_in_module=self) then
+                tdef(deflist[i]).registered_in_module:=nil;
+            deflist.free;
+          end;
         symlist.free;
         ptrdefs.free;
         arraydefs.free;

compiler/fpcdefs.inc

@@ -224,6 +224,10 @@
   {$if defined(CPUARMHF) and not(defined(FPC_OARM)) and not(defined(FPC_ARMEL)) and not(defined(FPC_ARMEB))}
     {$define FPC_ARMHF}
   {$endif}
+  { inherit FPC_OARM? }
+  {$if defined(CPUARM) and not(defined(FPC_ARMHF)) and not(defined(FPC_ARMEL)) and not(defined(FPC_ARMEB))}
+    {$define FPC_ARMHF}
+  {$endif}
 {$endif arm}
 
 {$ifdef m68k}
@@ -313,6 +317,8 @@
   {$define cpurefshaveindexreg}
   {$define SUPPORT_GET_FRAME}
   {$define SUPPORT_SAFECALL}
+  {$define cpucapabilities}
+  {$define fpucapabilities}
 {$endif aarch64}
 
 {$ifdef riscv32}
@@ -398,3 +404,14 @@
   {$define cpucg64shiftsupport}
   {$define symansistr}
 {$endif}
+
+{$ifdef wasm32}
+  {$define wasm}
+  {$define cpu32bit}
+  {$define cpu64bitalu}
+  {$define cpu32bitaddr}
+  {$define cpuhighleveltarget}
+  {$define symansistr}
+  {$define SUPPORT_GET_FRAME}
+{$endif}
+

compiler/fppu.pas

@@ -538,7 +538,7 @@ var
 
        var
          fnd : boolean;
-         hs  : TPathStr;
+         hs : TPathStr;
          nsitem : TCmdStrListItem;
        begin
          if shortname then
@@ -1129,20 +1129,32 @@ var
                else
                 begin
                   { check the date of the source files:
-                     1 path of ppu
-                     2 path of main source
-                     3 current dir
-                     4 include/unit path }
-                  Source_Time:=GetNamedFileTime(path+hs);
+                     1 path of sourcefn
+                     2 path of ppu
+                     3 path of main source
+                     4 current dir
+                     5 include/unit path }
                   found:=false;
-                  if Source_Time<>-1 then
-                    hs:=path+hs
-                  else
-                   if not(is_main) then
+                  if sourcefn<>'' then
+                  begin
+                    temp_dir:=ExtractFilePath(SetDirSeparators(sourcefn));
+                    Source_Time:=GetNamedFileTime(temp_dir+hs);
+                    if Source_Time<>-1 then
+                      hs:=temp_dir+hs;
+                  end else
+                    Source_Time:=-1;
+                  if Source_Time=-1 then
                     begin
-                      Source_Time:=GetNamedFileTime(main_dir+hs);
+                      Source_Time:=GetNamedFileTime(path+hs);
                       if Source_Time<>-1 then
-                        hs:=main_dir+hs;
+                        hs:=path+hs
+                      else
+                       if not(is_main) then
+                        begin
+                          Source_Time:=GetNamedFileTime(main_dir+hs);
+                          if Source_Time<>-1 then
+                            hs:=main_dir+hs;
+                        end;
                     end;
                   if Source_Time=-1 then
                     Source_Time:=GetNamedFileTime(hs);

compiler/globals.pas

@@ -416,6 +416,7 @@ interface
 {$if defined(m68k)}
        { Sinclair QL specific }
        sinclairql_metadata_format: string[4] = 'QHDR';
+       sinclairql_vlink_experimental: boolean = true; { temporary }
 {$endif defined(m68k)}
 
        { default name of the C-style "main" procedure of the library/program }
@@ -589,6 +590,12 @@ interface
         asmcputype : cpu_none;
         fputype : fpu_soft;
   {$endif z80}
+  {$ifdef wasm}
+        cputype : cpu_none;
+        optimizecputype : cpu_none;
+        asmcputype : cpu_none;
+        fputype : fpu_standard;
+  {$endif wasm}
 {$endif not GENERIC_CPU}
         asmmode : asmmode_standard;
 {$ifndef jvm}

compiler/hlcgobj.pas

@@ -4677,7 +4677,7 @@ implementation
             they can be interpreted as all different starting symbols of
             subsections and be reordered }
           if (item<>firstitem) and
-             (target_info.system in systems_darwin) then
+             (target_info.system in (systems_darwin+systems_wasm)) then
             begin
               { the .set already defines the symbol, so can't emit a tai_symbol as that will redefine it }
               if global then
@@ -5414,29 +5414,36 @@ implementation
            (po_nostackframe in current_procinfo.procdef.procoptions)
           )
          ) then
-        exit;
-
-      { constructors return self }
-      if current_procinfo.procdef.generate_safecall_wrapper then
         begin
-          if not current_procinfo.procdef.get_safecall_funcretsym_info(ressym,retdef) then
-            internalerror(2019112402);
-          gen_load_loc_function_result(list,retdef,tabstractnormalvarsym(ressym).localloc);
+          ressym:=current_procinfo.procdef.funcretsym;
+          if not assigned(ressym) then
+            exit;
         end
       else
         begin
-          if not current_procinfo.procdef.get_funcretsym_info(ressym,retdef) then
-            internalerror(2018122501);
-          if (ressym.refs>0) or
-             is_managed_type(retdef) then
+          { constructors return self }
+          if current_procinfo.procdef.generate_safecall_wrapper then
             begin
-              { was: don't do anything if funcretloc.loc in [LOC_INVALID,LOC_REFERENCE] }
-              if not paramanager.ret_in_param(current_procinfo.procdef.returndef,current_procinfo.procdef) then
-                gen_load_loc_function_result(list,retdef,tabstractnormalvarsym(ressym).localloc);
+              if not current_procinfo.procdef.get_safecall_funcretsym_info(ressym,retdef) then
+                internalerror(2019112402);
+              gen_load_loc_function_result(list,retdef,tabstractnormalvarsym(ressym).localloc);
             end
           else
-            gen_load_uninitialized_function_result(list,current_procinfo.procdef,retdef,current_procinfo.procdef.funcretloc[calleeside]);
+            begin
+              if not current_procinfo.procdef.get_funcretsym_info(ressym,retdef) then
+                internalerror(2018122501);
+              if (ressym.refs>0) or
+                 is_managed_type(retdef) then
+                begin
+                  { was: don't do anything if funcretloc.loc in [LOC_INVALID,LOC_REFERENCE] }
+                  if not paramanager.ret_in_param(current_procinfo.procdef.returndef,current_procinfo.procdef) then
+                    gen_load_loc_function_result(list,retdef,tabstractnormalvarsym(ressym).localloc);
+                end
+              else
+                gen_load_uninitialized_function_result(list,current_procinfo.procdef,retdef,current_procinfo.procdef.funcretloc[calleeside]);
+            end;
         end;
+
       if tabstractnormalvarsym(ressym).localloc.loc=LOC_REFERENCE then
         tg.UnGetLocal(list,tabstractnormalvarsym(ressym).localloc.reference);
     end;

compiler/htypechk.pas

@@ -625,7 +625,8 @@ implementation
         pd : tprocdef;
         oldcount,
         count: longint;
-        parasym : tparavarsym;
+        sym : tsym;
+        parasym : tparavarsym absolute sym;
       begin
         result:=false;
         count := pf.parast.SymList.count;
@@ -633,8 +634,8 @@ implementation
         oldcount:=count;
         while count > 0 do
           begin
-            parasym:=tparavarsym(pf.parast.SymList[count-1]);
-            if parasym.typ<>paravarsym then
+            sym:=tsym(pf.parast.SymList[count-1]);
+            if sym.typ<>paravarsym then
               begin
                 dec(count);
               end

compiler/i386/aoptcpu.pas

@@ -100,6 +100,8 @@ unit aoptcpu;
                     Result:=PrePeepholeOptIMUL(p);
                   A_SAR,A_SHR:
                     Result:=PrePeepholeOptSxx(p);
+                  A_AND:
+                    Result:=PrePeepholeOptAND(p);
                   A_XOR:
                     begin
                       if (taicpu(p).oper[0]^.typ = top_reg) and
@@ -166,6 +168,8 @@ unit aoptcpu;
                 A_MOVSX,
                 A_MOVZX :
                   Result:=OptPass1Movx(p);
+                A_TEST:
+                  Result:=OptPass1Test(p);
                 A_PUSH:
                   begin
                     if (taicpu(p).opsize = S_W) and
@@ -187,6 +191,8 @@ unit aoptcpu;
                   Result:=OptPass1SHLSAL(p);
                 A_SUB:
                   Result:=OptPass1Sub(p);
+                A_Jcc:
+                  Result:=OptPass1Jcc(p);
                 A_MOVAPD,
                 A_MOVAPS,
                 A_MOVUPD,
@@ -219,8 +225,9 @@ unit aoptcpu;
                 A_MOVSD,
                 A_MOVSS:
                   Result:=OptPass1MOVXX(p);
-                A_SETcc:
-                  Result:=OptPass1SETcc(p);
+                A_SHRX,
+                A_SHLX:
+                  Result:=OptPass1SHXX(p);
                 else
                   ;
               end;
@@ -258,6 +265,8 @@ unit aoptcpu;
                   Result:=OptPass2Movx(p);
                 A_SUB:
                   Result:=OptPass2SUB(p);
+                A_SETcc:
+                  Result:=OptPass2SETcc(p);
                 else
                   ;
               end;

compiler/i386/cpuinfo.pas

@@ -169,13 +169,13 @@ type
        CPUX86_HAS_BMI2,
        CPUX86_HAS_POPCNT,
        CPUX86_HAS_LZCNT,
-       CPUX86_HAS_MOVBE,
-       CPUX86_HAS_FMA,
-       CPUX86_HAS_FMA4
+       CPUX86_HAS_MOVBE
       );
 
    tfpuflags =
       (FPUX86_HAS_AVXUNIT,
+       FPUX86_HAS_FMA,
+       FPUX86_HAS_FMA4,
        FPUX86_HAS_AVX512F,
        FPUX86_HAS_AVX512VL,
        FPUX86_HAS_AVX512DQ
@@ -193,7 +193,7 @@ type
      { cpu_PentiumM  } [CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
      { cpu_core_i    } [CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
      { cpu_core_avx  } [CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT],
-     { cpu_core_avx2 } [CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE,CPUX86_HAS_FMA]
+     { cpu_core_avx2 } [CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
    );
 
    fpu_capabilities : array[tfputype] of set of tfpuflags = (
@@ -206,8 +206,8 @@ type
       { fpu_sse41    } [],
       { fpu_sse42    } [],
       { fpu_avx      } [FPUX86_HAS_AVXUNIT],
-      { fpu_avx2     } [FPUX86_HAS_AVXUNIT],
-      { fpu_avx512   } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
+      { fpu_avx2     } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA],
+      { fpu_avx512   } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
    );
 
 Implementation

compiler/i386/i386prop.inc

@@ -223,7 +223,7 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -269,9 +269,9 @@
 (Ch: [Ch_RWESP, Ch_WFlags]),
 (Ch: [Ch_RWESP, Ch_WFlags]),
 (Ch: [Ch_RWESP, Ch_WFLAGS]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -389,7 +389,7 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_ROp1, Ch_RWOp2, Ch_RFLAGScc]),
+(Ch: [Ch_ROp1, Ch_WOp2, Ch_RFLAGScc]),
 (Ch: [Ch_RFLAGScc]),
 (Ch: [Ch_RFLAGScc, Ch_WOp1]),
 (Ch: [Ch_RWESI, Ch_WMemEDI, Ch_RWEDI, Ch_RDirFlag]),
@@ -463,10 +463,10 @@
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),

compiler/i386/n386add.pas

@@ -486,13 +486,13 @@ interface
         begin
           cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
           hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_EDX);
-          cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
           reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
           reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
           if use_ref then
             current_asmdata.CurrAsmList.concat(Taicpu.Op_ref_reg_reg(A_MULX,S_L,ref,reglo,reghi))
           else
             emit_reg_reg_reg(A_MULX,S_L,reg,reglo,reghi);
+          cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
 
           location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
           location.register64.reglo:=reglo;

compiler/i386/n386flw.pas

@@ -46,6 +46,7 @@ interface
       constructor create(l,r:TNode);override;
       constructor create_implicit(l,r:TNode);override;
       function pass_1: tnode;override;
+	  function dogetcopy : tnode;override;
       function simplify(forinline: boolean): tnode;override;
       procedure pass_generate_code;override;
     end;
@@ -59,7 +60,7 @@ implementation
     cgbase,cgobj,cgcpu,cgutils,tgobj,
     cpubase,htypechk,
     parabase,paramgr,pass_1,pass_2,ncgutil,cga,
-    aasmbase,aasmtai,aasmdata,aasmcpu,procinfo,cpupi;
+    aasmbase,aasmtai,aasmdata,aasmcpu,procinfo,cpupi,procdefutil;
 
   var
     endexceptlabel: tasmlabel;
@@ -215,6 +216,30 @@ function ti386tryfinallynode.pass_1: tnode;
       end;
   end;
 
+function ti386tryfinallynode.dogetcopy: tnode;
+  var
+    n: ti386tryfinallynode;
+  begin
+	n:=ti386tryfinallynode(inherited dogetcopy);
+	if target_info.system=system_i386_win32 then
+	  begin
+	    n.finalizepi:=tcgprocinfo(cprocinfo.create(finalizepi.parent));
+		n.finalizepi.force_nested;
+		n.finalizepi.procdef:=create_outline_procdef('$fin$',current_procinfo.procdef.struct,potype_exceptfilter,voidtype);
+		n.finalizepi.entrypos:=finalizepi.entrypos;
+		n.finalizepi.entryswitches:=finalizepi.entryswitches;
+		n.finalizepi.exitpos:=finalizepi.exitpos;
+		n.finalizepi.exitswitches:=finalizepi.exitswitches;
+		n.finalizepi.flags:=finalizepi.flags;
+		{ node already transformed? }
+		if assigned(finalizepi.code) then
+		  begin
+			n.finalizepi.code:=finalizepi.code.getcopy;
+			n.right:=ccallnode.create(nil,tprocsym(n.finalizepi.procdef.procsym),nil,nil,[],nil);
+		  end;
+	  end;
+	result:=n;
+  end;
 
 function ti386tryfinallynode.simplify(forinline: boolean): tnode;
   begin
@@ -222,7 +247,8 @@ function ti386tryfinallynode.simplify(forinline: boolean): tnode;
     if (target_info.system<>system_i386_win32) then
       exit;
 
-    if (result=nil) and assigned(finalizepi) then
+    { actually, this is not really the right place to do a node transformation like this }
+    if (result=nil) and assigned(finalizepi) and (not(assigned(finalizepi.code))) then
       begin
         finalizepi.code:=right;
         foreachnodestatic(right,@copy_parasize,finalizepi);

compiler/i8086/i8086prop.inc

@@ -223,7 +223,7 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_Mop2, Ch_Rop1]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -269,9 +269,9 @@
 (Ch: [Ch_RWESP, Ch_WFlags]),
 (Ch: [Ch_RWESP, Ch_WFlags]),
 (Ch: [Ch_RWESP, Ch_WFLAGS]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Mop2, Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
@@ -389,7 +389,7 @@
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_ROp1, Ch_RWOp2, Ch_RFLAGScc]),
+(Ch: [Ch_ROp1, Ch_WOp2, Ch_RFLAGScc]),
 (Ch: [Ch_RFLAGScc]),
 (Ch: [Ch_RFLAGScc, Ch_WOp1]),
 (Ch: [Ch_RWESI, Ch_WMemEDI, Ch_RWEDI, Ch_RDirFlag]),
@@ -463,10 +463,10 @@
 (Ch: [Ch_Mop2, Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
-(Ch: [Ch_All]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
+(Ch: [Ch_Rop1]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),
 (Ch: [Ch_All]),

compiler/i8086/n8086mem.pas

@@ -48,6 +48,7 @@ interface
        { tx86vecnode doesn't work for i8086, so we inherit tcgvecnode }
        ti8086vecnode = class(tcgvecnode)
         protected
+         function get_address_type: tdef;override;
          function first_arraydef: tnode;override;
          procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint);override;
        end;
@@ -186,6 +187,12 @@ implementation
                              TI8086VECNODE
 *****************************************************************************}
 
+    function ti8086vecnode.get_address_type: tdef;
+      begin
+        result:=tx86pointerdef(cpointerdef).getreusablex86(resultdef,x86pt_near);
+      end;
+
+
     function ti8086vecnode.first_arraydef: tnode;
       var
         arraydef: tcpuarraydef;

compiler/jvm/hlcgcpu.pas

@@ -2292,6 +2292,10 @@ implementation
       { a constructor doesn't actually return a value in the jvm }
       if (tabstractprocdef(pd).proctypeoption=potype_constructor) then
         totalremovesize:=paraheight
+      else if jvmimplicitpointertype(realresdef) then
+        totalremovesize:=paraheight-1
+      else if is_void(realresdef) then
+        totalremovesize:=paraheight
       else
         { even a byte takes up a full stackslot -> align size to multiple of 4 }
         totalremovesize:=paraheight-(align(realresdef.size,4) shr 2);

compiler/jvm/jvmdef.pas

@@ -517,7 +517,8 @@ implementation
             result:=(tarraydef(def).highrange>=tarraydef(def).lowrange) or
                 is_open_array(def) or
                 is_array_of_const(def) or
-                is_array_constructor(def);
+                is_array_constructor(def) or
+                is_conststring_array(def);
           filedef,
           recorddef,
           setdef:

compiler/link.pas

@@ -662,7 +662,7 @@ Implementation
         if (OrderedSymbols.Empty) or
            not(tf_supports_symbolorderfile in target_info.flags) then
           exit;
-        symfile:=TScript.Create(outputexedir+'symbol_order.fpc');
+        symfile:=TScript.Create(outputexedir+UniqueName('symbol_order')+'.fpc');
         item:=TCmdStrListItem(OrderedSymbols.First);
         while assigned(item) do
           begin

compiler/llvm/agllvm.pas

@@ -1601,6 +1601,11 @@ implementation
         if fputypestrllvm[current_settings.fputype]<>'' then
           optstr:=optstr+' -m'+fputypestrllvm[current_settings.fputype];
 
+        { restrict march to aarch64 for now to fix x86_64 compilation failure }
+        if (cputypestr[current_settings.cputype]<>'')
+           and (target_info.system in [system_aarch64_darwin, system_aarch64_linux]) then
+          optstr:=optstr+' -march='+cputypestr[current_settings.cputype];
+
         replace(result,'$OPT',optstr);
         inc(fnextpass);
       end;

compiler/llvm/llvmpi.pas

@@ -88,6 +88,8 @@ implementation
 
       class procedure tllvmexceptionstatehandler.get_exception_temps(list: TAsmList; var t: texceptiontemps);
         begin
+          if not assigned(exceptionreasontype) then
+            exceptionreasontype:=ossinttype;
           tg.gethltemp(list,ossinttype,ossinttype.size,tt_persistent,t.reasonbuf);
         end;
 

compiler/m68k/ag68kvasm.pas

@@ -96,12 +96,10 @@ unit ag68kvasm;
         result:=asminfo^.asmcmd;
 
         case target_info.system of
-          { a.out doesn't support named sections }
-          system_m68k_amiga: objtype:='-Felf';
-          { atari never had a standard object format, a.out is limited, vasm/vlink author recommends vobj }
+          { a.out doesn't support named sections, lets use ELF for interoperability }
+          system_m68k_amiga,
           system_m68k_atari,
-          { same with the QL }
-          system_m68k_sinclairql: objtype:='-Fvobj';
+          system_m68k_sinclairql: objtype:='-Felf';
         else
           internalerror(2016052601);
         end;

compiler/m68k/cpubase.pas

@@ -331,6 +331,10 @@ implementation
         {$i r68kstd.inc}
       );
 
+      std_regfullname_table : TRegNameTable = (
+        {$i r68kstdf.inc}
+      );
+
       regnumber_index : array[tregisterindex] of tregisterindex = (
         {$i r68krni.inc}
       );
@@ -484,6 +488,10 @@ implementation
     function std_regnum_search(const s:string):Tregister;
       begin
         result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
+        if result=NR_NO then
+          begin
+            result:=regnumber_table[findreg_by_name_table(s,std_regfullname_table,std_regname_index)];
+          end;
       end;
 
 

compiler/m68k/cpunode.pas

@@ -30,25 +30,21 @@ unit cpunode;
     uses
        { generic nodes }
        ncgbas,ncgld,ncgflw,ncgcnv,ncgmem,ncgcon,ncgcal,ncgset,ncginl,ncgmat,ncgadd,
+       { symtable }
+       symcpu,
+       aasmdef,
        { to be able to only parts of the generic code,
          the processor specific nodes must be included
          after the generic one (FK)
        }
-         n68kadd,
-         n68kcal,
-//       nppccon,
-//       nppcflw,
-         n68kmem,
-         n68kset,
-         n68kinl,
-//       nppcopt,
-       { this not really a node }
-//       nppcobj,
-         n68kmat,
-         n68kcnv,
-         { symtable }
-         symcpu,
-         aasmdef
-         ;
+       n68kadd,
+       n68kcal,
+       n68kmem,
+       n68kset,
+       n68kinl,
+       n68kmat,
+       n68kcnv,
+       n68kutil
+       ;
 
 end.

compiler/m68k/cpupara.pas

@@ -83,7 +83,7 @@ unit cpupara;
       begin
         { d0 and d1 are considered volatile }
         Result:=VOLATILE_INTREGISTERS;
-        if (target_info.system in [system_m68k_palmos]) or
+        if (target_info.system in [system_m68k_palmos,system_m68k_macosclassic]) or
            ((target_info.system in [system_m68k_atari]) and (calloption in [pocall_syscall])) then
           include(result,RS_D2);
       end;

compiler/m68k/n68kmem.pas

@@ -35,7 +35,6 @@ interface
        t68kvecnode = class(tcgvecnode)
           procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
           procedure update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l:aint); override;
-          function valid_index_size(size: tcgsize): boolean; override;
           //procedure pass_generate_code;override;
        end;
 
@@ -55,14 +54,6 @@ implementation
                              T68KVECNODE
 *****************************************************************************}
 
-     function t68kvecnode.valid_index_size(size: tcgsize): boolean;
-       begin
-         if (CPUM68K_HAS_INDEXWORD in cpu_capabilities[current_settings.cputype]) then
-           result:=tcgsize2signed[size] in [OS_S16,OS_S32]
-         else
-           result:=inherited;
-       end;
-
     { this routine must, like any other routine, not change the contents }
     { of base/index registers of references, as these may be regvars.    }
     { The register allocator can coalesce one LOC_REGISTER being moved   }

compiler/m68k/n68kutil.pas

@@ -0,0 +1,74 @@
+{
+    Copyright (c) 2021 by Karoly Balogh
+
+    m68k version of some node tree helper routines
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+ ****************************************************************************
+}
+unit n68kutil;
+
+{$i fpcdefs.inc}
+
+interface
+
+    uses
+      cclasses,ngenutil;
+
+    type
+      t68knodeutils = class(tnodeutils)
+        class procedure InsertObjectInfo; override;
+      end;
+
+implementation
+
+    uses
+      verbose,
+      systems,
+      globals,
+      fmodule,
+      aasmbase,aasmdata,aasmtai,aasmcpu,aasmcnst,
+      symdef,symtype;
+
+
+    class procedure t68knodeutils.InsertObjectInfo;
+      var
+        tcb: ttai_typedconstbuilder;
+        s: shortstring;
+        sym: tasmsymbol;
+        def: tdef;
+      begin
+        inherited InsertObjectInfo;
+        if (not current_module.is_unit) and (target_info.system in [system_m68k_sinclairql]) then 
+          begin
+            { insert the main program name into the object. this will be set as default job name by the system unit }
+            tcb:=ctai_typedconstbuilder.create([tcalo_new_section]);
+            s:=char(length(current_module.realmodulename^))+current_module.realmodulename^+#0;
+            def:=carraydef.getreusable(cansichartype,length(s));
+            tcb.maybe_begin_aggregate(def);
+            tcb.emit_tai(Tai_string.Create(s),def);
+            tcb.maybe_end_aggregate(def);
+            sym:=current_asmdata.DefineAsmSymbol('__fpc_program_name',AB_GLOBAL,AT_DATA,def);
+            current_asmdata.asmlists[al_globals].concatlist(
+              tcb.get_final_asmlist(sym,def,sec_rodata,'__fpc_program_name',const_align(current_settings.alignment.constalignmax))
+            );
+            tcb.free;
+          end;
+      end;
+
+begin
+  cnodeutils:=t68knodeutils;
+end.

compiler/m68k/r68kgri.inc

@@ -16,30 +16,30 @@
 56,
 57,
 34,
+3,
 1,
 2,
-3,
+6,
 4,
 5,
-6,
+9,
 7,
 8,
-9,
 12,
-11,
 10,
+11,
+15,
 13,
 14,
-15,
+18,
 16,
 17,
-18,
+21,
 19,
 20,
-21,
 24,
-23,
 22,
+23,
 38,
 25,
 26,

compiler/m68k/r68ksri.inc

@@ -1,46 +1,46 @@
 { don't edit, this file is generated from m68kreg.dat }
 0,
-43,
 42,
-45,
+43,
 44,
-47,
+45,
 46,
-49,
+47,
 48,
-51,
+49,
 50,
-53,
+51,
 52,
-55,
+53,
 54,
-57,
+55,
 56,
+57,
 34,
-1,
 3,
+1,
 2,
-5,
-4,
 6,
-7,
+4,
+5,
 9,
+7,
 8,
-11,
 12,
 10,
-13,
+11,
 15,
+13,
 14,
-17,
-16,
 18,
-19,
+16,
+17,
 21,
+19,
 20,
-23,
 24,
 22,
+23,
 38,
 25,
 26,

compiler/m68k/ra68kmot.pas

@@ -216,6 +216,11 @@ const
         actasmregister:=std_regnum_search(lower(s));
         if actasmregister<>NR_NO then
           begin
+            { this is a hack. if the reg is valid, and its string doesn't
+              contain a dot, we make sure it's a full size reg (KB) }
+            if (getregtype(actasmregister) in [R_ADDRESSREGISTER,R_INTREGISTER]) and
+               (Pos('.',s) = 0) then
+              setsubreg(actasmregister,R_SUBWHOLE);
             result:=true;
             actasmtoken:=AS_REGISTER;
           end;
@@ -1196,7 +1201,7 @@ const
                      while actasmtoken <> AS_SEPARATOR do
                         Consume(actasmtoken);
                    end;
-                   exit;
+                 exit;
                end;
               { // (reg,reg .. // }
               Consume(AS_COMMA);

compiler/mips/aoptcpu.pas

@@ -206,11 +206,11 @@ unit aoptcpu;
     var
       p: taicpu;
     begin
-      p:=taicpu(hp);
       result:=false;
       if not ((assigned(hp)) and (hp.typ=ait_instruction)) then
         exit;
 
+      p:=taicpu(hp);
       case p.opcode of
         { These instructions do not write into a register at all }
         A_NOP,

compiler/mips/ncpuadd.pas

@@ -36,7 +36,7 @@ type
   private
     procedure cmp64_lt(left_reg, right_reg: TRegister64;unsigned:boolean);
     procedure cmp64_le(left_reg, right_reg: TRegister64;unsigned:boolean);
-    procedure second_generic_cmp32(unsigned: boolean);
+    procedure second_generic_cmp32(unsigned,is_smallset: boolean);
     procedure second_mul64bit;
   protected
     procedure second_addfloat; override;
@@ -72,18 +72,31 @@ uses
                                tmipsaddnode
 *****************************************************************************}
 
-procedure tmipsaddnode.second_generic_cmp32(unsigned: boolean);
+procedure tmipsaddnode.second_generic_cmp32(unsigned,is_smallset: boolean);
 var
   cond: TOpCmp;
+  allow_constant : boolean;
+  dreg : tregister;
 begin
   pass_left_right;
-  force_reg_left_right(True, True);
+  allow_constant:=(not is_smallset) or not (nodetype in [lten,gten]);
+  force_reg_left_right(True, allow_constant);
   location_reset(location,LOC_FLAGS,OS_NO);
 
   cond:=cmpnode2topcmp(unsigned);
   if nf_swapped in flags then
     cond:=swap_opcmp(cond);
 
+  if is_smallset and (nodetype in [lten,gten]) then
+    begin
+      if ((nodetype=lten) and not (nf_swapped in flags)) or
+         ((nodetype=gten) and (nf_swapped in flags)) then
+        dreg:=right.location.register
+      else
+        dreg:=left.location.register;
+      current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_AND,dreg,right.location.register,left.location.register));
+      cond:=OC_EQ;
+    end;
   location.resflags.cond:=cond;
   location.resflags.reg1:=left.location.register;
   location.resflags.use_const:=(right.location.loc=LOC_CONSTANT);
@@ -304,13 +317,13 @@ end;
 
 procedure tmipsaddnode.second_cmpboolean;
 begin
-  second_generic_cmp32(true);
+  second_generic_cmp32(true,false);
 end;
 
 
 procedure tmipsaddnode.second_cmpsmallset;
 begin
-  second_generic_cmp32(true);
+  second_generic_cmp32(true,true);
 end;
 
 
@@ -319,7 +332,7 @@ var
   unsigned: boolean;
 begin
   unsigned := not (is_signed(left.resultdef)) or not (is_signed(right.resultdef));
-  second_generic_cmp32(unsigned);
+  second_generic_cmp32(unsigned,false);
 end;
 
 

compiler/msg/errore.msg

@@ -2930,7 +2930,7 @@ asmr_e_not_supported_combination_attsuffix_memrefsize_type=07146_E_Not supported
 #
 # Assembler/binary writers
 #
-# 08035 is the last used one
+# 08036 is the last used one
 #
 asmw_f_too_many_asm_files=08000_F_Too many assembler files
 % With smartlinking enabled, there are too many assembler
@@ -2987,6 +2987,7 @@ asmw_e_instruction_not_supported_by_cpu=08032_E_Instruction not supported by the
 asmw_e_brxx_out_of_range=08033_E_Asm: conditional branch destination is out of range
 asmw_e_illegal_use_of_rip=08034_E_Asm: RIP cannot be used as index register or with another register in a reference
 asmw_e_seh_invalid_data_size=08035_F_Illegal function size for SEH function
+asmw_e_illegal_use_of_sp=08036_E_Asm: ESP/RSP cannot be used as index register
 #
 # Executing linker/assembler
 #
@@ -3909,10 +3910,23 @@ F*0*_Only options valid for the default or selected platform are listed.
 6*2Amot_Standard Motorola assembler
 6*2Avasm_Use vasm to assemble
 A*2Aas_Assemble using GNU AS
+A*2Aas-darwin_Assemble using GNU AS for Darwin targets
+A*2Aclang_Assemble using clang
+A*2Aelf_Assemble using internal ELF writer
+a*2Aas_Assemble using GNU AS
+a*2Aclang_Assemble using clang for darwin/ios targets
+a*2Aas-clang_Assemble using clang for other targets 
 P*2Aas_Assemble using GNU AS
 S*2Aas_Assemble using GNU AS
+s*2Aas_Assemble using GNU AS
+v*2Aas_Assemble using GNU AS
+W*2Abinaryen_Assemble using GNU AS for wasm32 (wasm-as)
+W*2Allvm-mc_Assemble using llvm-mc
+W*2Awabt_Assemble using wasa
+x*2Aas_Assemble using GNU AS
 Z*2Asdcc-sdasz80_Assemble using SDCC-SDASZ80
 Z*2Az80asm_Assemble using z80asm
+Z*2Avasm_Assemble using Vasm
 # Used only internally by IDE
 **1b_Generate browser info
 **2bl_Generate local symbol info
@@ -4184,6 +4198,7 @@ A*2Twince_Windows CE
 # aarch64 targets
 a*2Tandroid_Android
 a*2Tdarwin_Darwin/Mac OS X
+a*2Tfreebsd_FreeBSD
 a*2Tios_iOS
 a*2Tlinux_Linux
 a*2Twin64_Windows 64
@@ -4234,6 +4249,9 @@ x*2Tlinux_Linux
 Z*2Tembedded_Embedded
 Z*2Tzxspectrum_ZX Spectrum
 Z*2Tmsxdos_MSX-DOS
+# wasm32 targets
+W*2Tembedded_Embedded
+W*2Twasi_The WebAssembly System Interface (WASI)
 # end of targets section
 **1u<x>_Undefines the symbol <x>
 **1U_Unit options:

compiler/msgidx.inc

@@ -896,6 +896,7 @@ const
   asmw_e_brxx_out_of_range=08033;
   asmw_e_illegal_use_of_rip=08034;
   asmw_e_seh_invalid_data_size=08035;
+  asmw_e_illegal_use_of_sp=08036;
   exec_w_source_os_redefined=09000;
   exec_i_assembling_pipe=09001;
   exec_d_cant_create_asmfile=09002;
@@ -1140,9 +1141,9 @@ const
   option_info=11024;
   option_help_pages=11025;
 
-  MsgTxtSize = 87309;
+  MsgTxtSize = 87955;
 
   MsgIdxMax : array[1..20] of longint=(
-    28,107,361,131,99,63,147,36,223,68,
+    28,107,361,131,99,63,147,37,223,68,
     64,20,30,1,1,1,1,1,1,1
   );

compiler/nadd.pas

@@ -489,6 +489,20 @@ implementation
         end;
 
 
+      function IsAndOrAndNot(n1,n2,n3,n4 : tnode): Boolean;
+        begin
+          result:=(n4.nodetype=notn) and
+            tnotnode(n4).left.isequal(n2);
+        end;
+
+
+      function TransformAndOrAndNot(n1,n2,n3,n4 : tnode): tnode;
+        begin
+          result:=caddnode.create_internal(xorn,n3.getcopy,
+            caddnode.create_internal(andn,caddnode.create_internal(xorn,n3.getcopy,n1.getcopy),n2.getcopy));
+        end;
+
+
       function SwapRightWithLeftRight : tnode;
         var
           hp : tnode;
@@ -576,7 +590,7 @@ implementation
 
       var
         t,vl,lefttarget,righttarget: tnode;
-        lt,rt   : tnodetype;
+        lt,rt,nt : tnodetype;
         hdef,
         rd,ld   , inttype: tdef;
         rv,lv,v : tconstexprint;
@@ -1689,6 +1703,78 @@ implementation
                    end;
               end;
 {$endif cpurox}
+            { optimize
+
+                (a and b) or (c and not(b))
+
+                into
+
+                c xor ((c xor a) and b)
+            }
+            if (nodetype=orn) and
+             (left.resultdef.typ=orddef) and
+             (left.nodetype=andn) and
+             (right.nodetype=andn) and
+             (not(is_boolean(resultdef)) or not(might_have_sideeffects(self,[mhs_exceptions])) or not(doshortbooleval(self))) and
+             { this test is not needed but it speeds up the test and allows to bail out early }
+             ((taddnode(left).left.nodetype=notn) or (taddnode(left).right.nodetype=notn) or
+              (taddnode(right).left.nodetype=notn) or (taddnode(right).right.nodetype=notn)
+             ) and
+             not(might_have_sideeffects(self)) then
+             begin
+               if MatchAndTransformNodesCommutative(taddnode(left).left,taddnode(left).right,taddnode(right).left,taddnode(right).right,
+                 @IsAndOrAndNot,@TransformAndOrAndNot,Result) then
+                 exit;
+             end;
+            { optimize tests for a single bit:
+              (a and one_bit_mask_const) = <> one_bit_mask_const
+
+              into
+
+              (a and one_bit_mask_const) <> = 0
+            }
+            if (nodetype in [equaln,unequaln]) then
+              begin
+                if (lt=andn) and (rt=ordconstn) then
+                  begin
+                    t:=left;
+                    cr:=tordconstnode(right).value;
+                  end
+                else
+                  if (rt=andn) and (lt=ordconstn) then
+                    begin
+                      t:=right;
+                      cr:=tordconstnode(left).value;
+                    end
+                  else
+                    begin
+                      t:=nil;
+                      cr:=0;
+                    end;
+                if (t<>nil) and (PopCnt(cr) = 1) then
+                  begin
+                    if is_constintnode(taddnode(t).left) then
+                      vl:=taddnode(t).left
+                    else
+                      if is_constintnode(taddnode(t).right) then
+                        vl:=taddnode(t).right
+                      else
+                        vl:=nil;
+                    if (vl<>nil) and (tordconstnode(vl).value=cr) then
+                      begin
+                        if nodetype=equaln then
+                          nt:=unequaln
+                        else
+                          nt:=equaln;
+                        result:=caddnode.create(nt,t,cordconstnode.create(0,vl.resultdef,false));
+                        if t=left then
+                          left:=nil
+                        else
+                          right:=nil;
+                        exit;
+                      end;
+                  end;
+              end;
           end;
       end;
 
@@ -1939,7 +2025,11 @@ implementation
               not(tfloatdef(left.resultdef).floattype in [s64comp,s64currency]) then
              begin
                if cs_excessprecision in current_settings.localswitches then
-                 resultrealdef:=pbestrealtype^
+                 begin
+                   resultrealdef:=pbestrealtype^;
+                   inserttypeconv(right,resultrealdef);
+                   inserttypeconv(left,resultrealdef);
+                 end
                else
                  resultrealdef:=left.resultdef
              end