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@@ -16346,7 +16346,11 @@ unit aoptx86;
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reference_reset(NewRef, 1, []);
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reference_reset(NewRef, 1, []);
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NewRef.base := taicpu(p).oper[1]^.reg;
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NewRef.base := taicpu(p).oper[1]^.reg;
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NewRef.scalefactor := 1;
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NewRef.scalefactor := 1;
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- NewRef.offset := asizeint(taicpu(p).oper[0]^.val);
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+ { if the destination reg is the same as the ADD register,
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+ and we keep the ADD instruction, do not add the offset
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+ to LEA instruction, otherwise the reg gets increased by 2 times the offset value }
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+ if DoAddMov2Lea or not MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^.reg) then
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+ NewRef.offset := asizeint(taicpu(p).oper[0]^.val);
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taicpu(hp1).opcode := A_LEA;
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taicpu(hp1).opcode := A_LEA;
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taicpu(hp1).loadref(0, NewRef);
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taicpu(hp1).loadref(0, NewRef);
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@@ -16620,7 +16624,11 @@ unit aoptx86;
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reference_reset(NewRef, 1, []);
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reference_reset(NewRef, 1, []);
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NewRef.base := taicpu(p).oper[1]^.reg;
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NewRef.base := taicpu(p).oper[1]^.reg;
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NewRef.scalefactor := 1;
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NewRef.scalefactor := 1;
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- NewRef.offset := -taicpu(p).oper[0]^.val;
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+ { if the destination reg is the same as the SUB register,
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+ and we keep the ADD instruction, do not substract the offset
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+ to LEA instruction, otherwise the reg gets decreased by 2 times the offset value }
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+ if DoSubMov2Lea or not MatchOperand(taicpu(hp1).oper[0]^,taicpu(hp1).oper[1]^.reg) then
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+ NewRef.offset := -taicpu(p).oper[0]^.val;
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taicpu(hp1).opcode := A_LEA;
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taicpu(hp1).opcode := A_LEA;
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taicpu(hp1).loadref(0, NewRef);
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taicpu(hp1).loadref(0, NewRef);
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