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@@ -109,7 +109,7 @@ implementation
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location.loc:=LOC_FPUREGISTER;
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load_fpu_location;
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_FMUL,location.register,
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- location.register,left.location.register));
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+ left.location.register,left.location.register));
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end;
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@@ -150,7 +150,10 @@ begin
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end.
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{
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$Log$
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- Revision 1.13 2004-02-03 22:32:54 peter
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+ Revision 1.14 2004-05-31 11:57:48 jonas
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+ * fixed second_sqr_real (mainly for regvars)
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+
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+ Revision 1.13 2004/02/03 22:32:54 peter
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* renamed xNNbittype to xNNinttype
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* renamed registers32 to registersint
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* replace some s32bit,u32bit with torddef([su]inttype).def.typ
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