somehow committing went wrong, second part of last commit:

+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers

git-svn-id: trunk@42917 -

compiler/aarch64/a64att.inc

@@ -187,5 +187,6 @@
 'fcsel',
 'umov',
 'ins',
-'movi'
+'movi',
+'veor'
 );

compiler/aarch64/a64atts.inc

@@ -187,5 +187,6 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/aarch64/a64ins.dat

@@ -376,3 +376,5 @@
 [INS]
 
 [MOVI]
+
+[VEOR]

compiler/aarch64/a64op.inc

@@ -187,5 +187,6 @@ A_FCMMPE,
 A_FCSEL,
 A_UMOV,
 A_INS,
-A_MOVI
+A_MOVI,
+A_VEOR
 );

compiler/aarch64/a64reg.dat

@@ -76,170 +76,235 @@ XZR,$01,$05,$1F,xzr,31,31
 WSP,$01,$04,$20,wsp,31,31
 SP,$01,$05,$20,sp,31,31
 
-
 ; vfp registers
+; generated by fpc/compiler/utils/gena64vfp.pp to avoid tedious typing
 B0,$04,$01,$00,b0,64,64
 H0,$04,$03,$00,h0,64,64
 S0,$04,$09,$00,s0,64,64
 D0,$04,$0a,$00,d0,64,64
 Q0,$04,$05,$00,q0,64,64
+V08B,$04,$17,$00,v0.8b,64,64
+V016B,$04,$18,$00,v0.16b,64,64
 B1,$04,$01,$01,b1,65,65
 H1,$04,$03,$01,h1,65,65
 S1,$04,$09,$01,s1,65,65
 D1,$04,$0a,$01,d1,65,65
 Q1,$04,$05,$01,q1,65,65
+V18B,$04,$17,$01,v1.8b,65,65
+V116B,$04,$18,$01,v1.16b,65,65
 B2,$04,$01,$02,b2,66,66
 H2,$04,$03,$02,h2,66,66
 S2,$04,$09,$02,s2,66,66
 D2,$04,$0a,$02,d2,66,66
 Q2,$04,$05,$02,q2,66,66
+V28B,$04,$17,$02,v2.8b,66,66
+V216B,$04,$18,$02,v2.16b,66,66
 B3,$04,$01,$03,b3,67,67
 H3,$04,$03,$03,h3,67,67
 S3,$04,$09,$03,s3,67,67
 D3,$04,$0a,$03,d3,67,67
 Q3,$04,$05,$03,q3,67,67
+V38B,$04,$17,$03,v3.8b,67,67
+V316B,$04,$18,$03,v3.16b,67,67
 B4,$04,$01,$04,b4,68,68
 H4,$04,$03,$04,h4,68,68
 S4,$04,$09,$04,s4,68,68
 D4,$04,$0a,$04,d4,68,68
 Q4,$04,$05,$04,q4,68,68
+V48B,$04,$17,$04,v4.8b,68,68
+V416B,$04,$18,$04,v4.16b,68,68
 B5,$04,$01,$05,b5,69,69
 H5,$04,$03,$05,h5,69,69
 S5,$04,$09,$05,s5,69,69
 D5,$04,$0a,$05,d5,69,69
 Q5,$04,$05,$05,q5,69,69
+V58B,$04,$17,$05,v5.8b,69,69
+V516B,$04,$18,$05,v5.16b,69,69
 B6,$04,$01,$06,b6,70,70
 H6,$04,$03,$06,h6,70,70
-S6,$04,$09,$06,s6,70,70
+S6,$04,$09,$06,s6,70,70                                                                     gena64vfp.pp
 D6,$04,$0a,$06,d6,70,70
 Q6,$04,$05,$06,q6,70,70
+V68B,$04,$17,$06,v6.8b,70,70
+V616B,$04,$18,$06,v6.16b,70,70
 B7,$04,$01,$07,b7,71,71
 H7,$04,$03,$07,h7,71,71
 S7,$04,$09,$07,s7,71,71
 D7,$04,$0a,$07,d7,71,71
 Q7,$04,$05,$07,q7,71,71
+V78B,$04,$17,$07,v7.8b,71,71
+V716B,$04,$18,$07,v7.16b,71,71
 B8,$04,$01,$08,b8,72,72
 H8,$04,$03,$08,h8,72,72
 S8,$04,$09,$08,s8,72,72
 D8,$04,$0a,$08,d8,72,72
 Q8,$04,$05,$08,q8,72,72
+V88B,$04,$17,$08,v8.8b,72,72
+V816B,$04,$18,$08,v8.16b,72,72
 B9,$04,$01,$09,b9,73,73
 H9,$04,$03,$09,h9,73,73
 S9,$04,$09,$09,s9,73,73
 D9,$04,$0a,$09,d9,73,73
 Q9,$04,$05,$09,q9,73,73
+V98B,$04,$17,$09,v9.8b,73,73
+V916B,$04,$18,$09,v9.16b,73,73
 B10,$04,$01,$0A,b10,74,74
 H10,$04,$03,$0A,h10,74,74
 S10,$04,$09,$0A,s10,74,74
 D10,$04,$0a,$0A,d10,74,74
 Q10,$04,$05,$0A,q10,74,74
+V108B,$04,$17,$0A,v10.8b,74,74
+V1016B,$04,$18,$0A,v10.16b,74,74
 B11,$04,$01,$0B,b11,75,75
 H11,$04,$03,$0B,h11,75,75
 S11,$04,$09,$0B,s11,75,75
 D11,$04,$0a,$0B,d11,75,75
 Q11,$04,$05,$0B,q11,75,75
+V118B,$04,$17,$0B,v11.8b,75,75
+V1116B,$04,$18,$0B,v11.16b,75,75
 B12,$04,$01,$0C,b12,76,76
 H12,$04,$03,$0C,h12,76,76
 S12,$04,$09,$0C,s12,76,76
 D12,$04,$0a,$0C,d12,76,76
 Q12,$04,$05,$0C,q12,76,76
+V128B,$04,$17,$0C,v12.8b,76,76
+V1216B,$04,$18,$0C,v12.16b,76,76
 B13,$04,$01,$0D,b13,77,77
 H13,$04,$03,$0D,h13,77,77
 S13,$04,$09,$0D,s13,77,77
 D13,$04,$0a,$0D,d13,77,77
 Q13,$04,$05,$0D,q13,77,77
+V138B,$04,$17,$0D,v13.8b,77,77
+V1316B,$04,$18,$0D,v13.16b,77,77
 B14,$04,$01,$0E,b14,78,78
 H14,$04,$03,$0E,h14,78,78
 S14,$04,$09,$0E,s14,78,78
 D14,$04,$0a,$0E,d14,78,78
 Q14,$04,$05,$0E,q14,78,78
+V148B,$04,$17,$0E,v14.8b,78,78
+V1416B,$04,$18,$0E,v14.16b,78,78
 B15,$04,$01,$0F,b15,79,79
 H15,$04,$03,$0F,h15,79,79
 S15,$04,$09,$0F,s15,79,79
 D15,$04,$0a,$0F,d15,79,79
 Q15,$04,$05,$0F,q15,79,79
+V158B,$04,$17,$0F,v15.8b,79,79
+V1516B,$04,$18,$0F,v15.16b,79,79
 B16,$04,$01,$10,b16,80,80
 H16,$04,$03,$10,h16,80,80
 S16,$04,$09,$10,s16,80,80
 D16,$04,$0a,$10,d16,80,80
 Q16,$04,$05,$10,q16,80,80
+V168B,$04,$17,$10,v16.8b,80,80
+V1616B,$04,$18,$10,v16.16b,80,80
 B17,$04,$01,$11,b17,81,81
 H17,$04,$03,$11,h17,81,81
 S17,$04,$09,$11,s17,81,81
 D17,$04,$0a,$11,d17,81,81
 Q17,$04,$05,$11,q17,81,81
+V178B,$04,$17,$11,v17.8b,81,81
+V1716B,$04,$18,$11,v17.16b,81,81
 B18,$04,$01,$12,b18,82,82
 H18,$04,$03,$12,h18,82,82
 S18,$04,$09,$12,s18,82,82
 D18,$04,$0a,$12,d18,82,82
 Q18,$04,$05,$12,q18,82,82
+V188B,$04,$17,$12,v18.8b,82,82
+V1816B,$04,$18,$12,v18.16b,82,82
 B19,$04,$01,$13,b19,83,83
 H19,$04,$03,$13,h19,83,83
 S19,$04,$09,$13,s19,83,83
 D19,$04,$0a,$13,d19,83,83
 Q19,$04,$05,$13,q19,83,83
+V198B,$04,$17,$13,v19.8b,83,83
+V1916B,$04,$18,$13,v19.16b,83,83
 B20,$04,$01,$14,b20,84,84
 H20,$04,$03,$14,h20,84,84
 S20,$04,$09,$14,s20,84,84
 D20,$04,$0a,$14,d20,84,84
 Q20,$04,$05,$14,q20,84,84
+V208B,$04,$17,$14,v20.8b,84,84
+V2016B,$04,$18,$14,v20.16b,84,84
 B21,$04,$01,$15,b21,85,85
 H21,$04,$03,$15,h21,85,85
 S21,$04,$09,$15,s21,85,85
 D21,$04,$0a,$15,d21,85,85
 Q21,$04,$05,$15,q21,85,85
+V218B,$04,$17,$15,v21.8b,85,85
+V2116B,$04,$18,$15,v21.16b,85,85
 B22,$04,$01,$16,b22,86,86
 H22,$04,$03,$16,h22,86,86
 S22,$04,$09,$16,s22,86,86
 D22,$04,$0a,$16,d22,86,86
 Q22,$04,$05,$16,q22,86,86
+V228B,$04,$17,$16,v22.8b,86,86
+V2216B,$04,$18,$16,v22.16b,86,86
 B23,$04,$01,$17,b23,87,87
 H23,$04,$03,$17,h23,87,87
 S23,$04,$09,$17,s23,87,87
 D23,$04,$0a,$17,d23,87,87
 Q23,$04,$05,$17,q23,87,87
+V238B,$04,$17,$17,v23.8b,87,87
+V2316B,$04,$18,$17,v23.16b,87,87
 B24,$04,$01,$18,b24,88,88
 H24,$04,$03,$18,h24,88,88
 S24,$04,$09,$18,s24,88,88
 D24,$04,$0a,$18,d24,88,88
 Q24,$04,$05,$18,q24,88,88
+V248B,$04,$17,$18,v24.8b,88,88
+V2416B,$04,$18,$18,v24.16b,88,88
 B25,$04,$01,$19,b25,89,89
 H25,$04,$03,$19,h25,89,89
 S25,$04,$09,$19,s25,89,89
 D25,$04,$0a,$19,d25,89,89
 Q25,$04,$05,$19,q25,89,89
+V258B,$04,$17,$19,v25.8b,89,89
+V2516B,$04,$18,$19,v25.16b,89,89
 B26,$04,$01,$1A,b26,90,90
 H26,$04,$03,$1A,h26,90,90
 S26,$04,$09,$1A,s26,90,90
 D26,$04,$0a,$1A,d26,90,90
 Q26,$04,$05,$1A,q26,90,90
+V268B,$04,$17,$1A,v26.8b,90,90
+V2616B,$04,$18,$1A,v26.16b,90,90
 B27,$04,$01,$1B,b27,91,91
 H27,$04,$03,$1B,h27,91,91
 S27,$04,$09,$1B,s27,91,91
 D27,$04,$0a,$1B,d27,91,91
 Q27,$04,$05,$1B,q27,91,91
+V278B,$04,$17,$1B,v27.8b,91,91
+V2716B,$04,$18,$1B,v27.16b,91,91
 B28,$04,$01,$1C,b28,92,92
 H28,$04,$03,$1C,h28,92,92
 S28,$04,$09,$1C,s28,92,92
 D28,$04,$0a,$1C,d28,92,92
 Q28,$04,$05,$1C,q28,92,92
+V288B,$04,$17,$1C,v28.8b,92,92
+V2816B,$04,$18,$1C,v28.16b,92,92
 B29,$04,$01,$1D,b29,93,93
 H29,$04,$03,$1D,h29,93,93
 S29,$04,$09,$1D,s29,93,93
 D29,$04,$0a,$1D,d29,93,93
 Q29,$04,$05,$1D,q29,93,93
+V298B,$04,$17,$1D,v29.8b,93,93
+V2916B,$04,$18,$1D,v29.16b,93,93
 B30,$04,$01,$1E,b30,94,94
 H30,$04,$03,$1E,h30,94,94
 S30,$04,$09,$1E,s30,94,94
 D30,$04,$0a,$1E,d30,94,94
 Q30,$04,$05,$1E,q30,94,94
+V308B,$04,$17,$1E,v30.8b,94,94
+V3016B,$04,$18,$1E,v30.16b,94,94
 B31,$04,$01,$1F,b31,95,95
 H31,$04,$03,$1F,h31,95,95
 S31,$04,$09,$1F,s31,95,95
 D31,$04,$0a,$1F,d31,95,95
 Q31,$04,$05,$1F,q31,95,95
+V318B,$04,$17,$1F,v31.8b,95,95
+V3116B,$04,$18,$1F,v31.16b,95,95
 
 NZCV,$05,$00,$00,nzcv,0,0
 FPCR,$05,$00,$01,fpcr,0,0
 FPSR,$05,$00,$02,fpsr,0,0
 TPIDR_EL0,$05,$00,$03,tpidr_el0,0,0
+

compiler/aarch64/aasmcpu.pas

@@ -157,6 +157,8 @@ uses
          oppostfix : TOpPostfix;
          procedure loadshifterop(opidx:longint;const so:tshifterop);
          procedure loadconditioncode(opidx: longint; const c: tasmcond);
+         procedure loadrealconst(opidx: longint; const _value: bestreal);
+
          constructor op_none(op : tasmop);
 
          constructor op_reg(op : tasmop;_op1 : tregister);
@@ -168,6 +170,7 @@ uses
          constructor op_reg_cond(op: tasmop; _op1: tregister; _op2: tasmcond);
          constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
          constructor op_reg_const_shifterop(op : tasmop;_op1: tregister; _op2: aint;_op3 : tshifterop);
+         constructor op_reg_realconst(op: tasmop; _op1: tregister; _op2: bestreal);
 
          constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
          constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
@@ -180,7 +183,6 @@ uses
          constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister; const _op4 : tshifterop);
          constructor op_reg_reg_reg_cond(op : tasmop;_op1,_op2,_op3 : tregister; const _op4: tasmcond);
 
-
          { this is for Jmp instructions }
          constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
 
@@ -280,6 +282,19 @@ implementation
       end;
 
 
+    procedure taicpu.loadrealconst(opidx:longint;const _value:bestreal);
+      begin
+        allocate_oper(opidx+1);
+        with oper[opidx]^ do
+          begin
+            if typ<>top_realconst then
+              clearop(opidx);
+            val_real:=_value;
+            typ:=top_realconst;
+          end;
+      end;
+
+
 {*****************************************************************************
                                  taicpu Constructors
 *****************************************************************************}
@@ -382,6 +397,15 @@ implementation
       end;
 
 
+    constructor taicpu.op_reg_realconst(op : tasmop; _op1 : tregister; _op2 : bestreal);
+      begin
+         inherited create(op);
+         ops:=2;
+         loadreg(0,_op1);
+         loadrealconst(1,_op2);
+      end;
+
+
      constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
        begin
          inherited create(op);
@@ -528,7 +552,7 @@ implementation
       const
         { invalid sizes for aarch64 are 0 }
         subreg2bytesize: array[TSubRegister] of byte =
-          (0,0,0,0,4,8,0,0,0,4,8,0,0,0,0,0,0,0,0,0,0,0,0);
+          (0,0,0,0,4,8,0,0,0,4,8,0,0,0,0,0,0,0,0,0,0,0,0,8,16);
       var
         scalefactor: byte;
       begin

compiler/aarch64/agcpugas.pas

@@ -236,6 +236,11 @@ unit agcpugas;
               end
             else
               getopstr:=getreferencestring(asminfo,o.ref^);
+          top_realconst:
+            begin
+              str(o.val_real,Result);
+              Result:='#'+Result;
+            end
           else
             internalerror(2014121507);
         end;

compiler/aarch64/cpubase.pas

@@ -106,7 +106,7 @@ unit cpubase;
       std_param_align = 8;
 
       { TODO: Calculate bsstart}
-      regnumber_count_bsstart = 128;
+      regnumber_count_bsstart = 256;
 
       regnumber_table : array[tregisterindex] of tregister = (
         {$i ra64num.inc}
@@ -123,9 +123,6 @@ unit cpubase;
       VOLATILE_INTREGISTERS = [RS_X0..RS_X18,RS_X30];
       VOLATILE_MMREGISTERS =  [RS_D0..RS_D7,RS_D16..RS_D31];
 
-    type
-      totherregisterset = set of tregisterindex;
-
 {*****************************************************************************
                           Instruction post fixes
 *****************************************************************************}
@@ -331,6 +328,7 @@ unit cpubase;
     function eh_return_data_regno(nr: longint): longint;
 
     function is_shifter_const(d: aint; size: tcgsize): boolean;
+    function IsFloatImmediate(ft : tfloattype;value : bestreal) : boolean;
 
 
   implementation
@@ -619,4 +617,34 @@ unit cpubase;
         result:=-1;
     end;
 
+
+  function IsFloatImmediate(ft : tfloattype;value : bestreal) : boolean;
+    var
+      singlerec : tcompsinglerec;
+      doublerec : tcompdoublerec;
+    begin
+      Result:=false;
+      case ft of
+        s32real:
+          begin
+            singlerec.value:=value;
+            singlerec:=tcompsinglerec(NtoLE(DWord(singlerec)));
+            Result:=(singlerec.bytes[0]=0) and (singlerec.bytes[1]=0) and ((singlerec.bytes[2] and 7)=0)  and
+              (((singlerec.bytes[3] and $7e)=$40) or ((singlerec.bytes[3] and $7e)=$3e));
+          end;
+        s64real:
+          begin
+            doublerec.value:=value;
+            doublerec:=tcompdoublerec(NtoLE(QWord(doublerec)));
+            Result:=(doublerec.bytes[0]=0) and (doublerec.bytes[1]=0) and (doublerec.bytes[2]=0) and
+                    (doublerec.bytes[3]=0) and (doublerec.bytes[4]=0) and (doublerec.bytes[5]=0) and
+                    ((((doublerec.bytes[6] and $c0)=$0) and ((doublerec.bytes[7] and $7f)=$40)) or
+                     (((doublerec.bytes[6] and $c0)=$c0) and ((doublerec.bytes[7] and $7f)=$3f)));
+          end;
+        else
+          ;
+      end;
+    end;
+
+
 end.

compiler/aarch64/cpunode.pas

@@ -35,7 +35,7 @@ implementation
     symcpu,
     aasmdef,
 {$ifndef llvm}
-    ncpuadd,ncpumat,ncpumem,ncpuinl,ncpucnv,ncpuset
+    ncpuadd,ncpumat,ncpumem,ncpuinl,ncpucnv,ncpuset,ncpucon
 {$else llvm}
     llvmnode
 {$endif llvm}

compiler/aarch64/ra64con.inc

@@ -71,161 +71,225 @@ NR_H0 = tregister($04030000);
 NR_S0 = tregister($04090000);
 NR_D0 = tregister($040a0000);
 NR_Q0 = tregister($04050000);
+NR_V08B = tregister($04170000);
+NR_V016B = tregister($04180000);
 NR_B1 = tregister($04010001);
 NR_H1 = tregister($04030001);
 NR_S1 = tregister($04090001);
 NR_D1 = tregister($040a0001);
 NR_Q1 = tregister($04050001);
+NR_V18B = tregister($04170001);
+NR_V116B = tregister($04180001);
 NR_B2 = tregister($04010002);
 NR_H2 = tregister($04030002);
 NR_S2 = tregister($04090002);
 NR_D2 = tregister($040a0002);
 NR_Q2 = tregister($04050002);
+NR_V28B = tregister($04170002);
+NR_V216B = tregister($04180002);
 NR_B3 = tregister($04010003);
 NR_H3 = tregister($04030003);
 NR_S3 = tregister($04090003);
 NR_D3 = tregister($040a0003);
 NR_Q3 = tregister($04050003);
+NR_V38B = tregister($04170003);
+NR_V316B = tregister($04180003);
 NR_B4 = tregister($04010004);
 NR_H4 = tregister($04030004);
 NR_S4 = tregister($04090004);
 NR_D4 = tregister($040a0004);
 NR_Q4 = tregister($04050004);
+NR_V48B = tregister($04170004);
+NR_V416B = tregister($04180004);
 NR_B5 = tregister($04010005);
 NR_H5 = tregister($04030005);
 NR_S5 = tregister($04090005);
 NR_D5 = tregister($040a0005);
 NR_Q5 = tregister($04050005);
+NR_V58B = tregister($04170005);
+NR_V516B = tregister($04180005);
 NR_B6 = tregister($04010006);
 NR_H6 = tregister($04030006);
 NR_S6 = tregister($04090006);
 NR_D6 = tregister($040a0006);
 NR_Q6 = tregister($04050006);
+NR_V68B = tregister($04170006);
+NR_V616B = tregister($04180006);
 NR_B7 = tregister($04010007);
 NR_H7 = tregister($04030007);
 NR_S7 = tregister($04090007);
 NR_D7 = tregister($040a0007);
 NR_Q7 = tregister($04050007);
+NR_V78B = tregister($04170007);
+NR_V716B = tregister($04180007);
 NR_B8 = tregister($04010008);
 NR_H8 = tregister($04030008);
 NR_S8 = tregister($04090008);
 NR_D8 = tregister($040a0008);
 NR_Q8 = tregister($04050008);
+NR_V88B = tregister($04170008);
+NR_V816B = tregister($04180008);
 NR_B9 = tregister($04010009);
 NR_H9 = tregister($04030009);
 NR_S9 = tregister($04090009);
 NR_D9 = tregister($040a0009);
 NR_Q9 = tregister($04050009);
+NR_V98B = tregister($04170009);
+NR_V916B = tregister($04180009);
 NR_B10 = tregister($0401000A);
 NR_H10 = tregister($0403000A);
 NR_S10 = tregister($0409000A);
 NR_D10 = tregister($040a000A);
 NR_Q10 = tregister($0405000A);
+NR_V108B = tregister($0417000A);
+NR_V1016B = tregister($0418000A);
 NR_B11 = tregister($0401000B);
 NR_H11 = tregister($0403000B);
 NR_S11 = tregister($0409000B);
 NR_D11 = tregister($040a000B);
 NR_Q11 = tregister($0405000B);
+NR_V118B = tregister($0417000B);
+NR_V1116B = tregister($0418000B);
 NR_B12 = tregister($0401000C);
 NR_H12 = tregister($0403000C);
 NR_S12 = tregister($0409000C);
 NR_D12 = tregister($040a000C);
 NR_Q12 = tregister($0405000C);
+NR_V128B = tregister($0417000C);
+NR_V1216B = tregister($0418000C);
 NR_B13 = tregister($0401000D);
 NR_H13 = tregister($0403000D);
 NR_S13 = tregister($0409000D);
 NR_D13 = tregister($040a000D);
 NR_Q13 = tregister($0405000D);
+NR_V138B = tregister($0417000D);
+NR_V1316B = tregister($0418000D);
 NR_B14 = tregister($0401000E);
 NR_H14 = tregister($0403000E);
 NR_S14 = tregister($0409000E);
 NR_D14 = tregister($040a000E);
 NR_Q14 = tregister($0405000E);
+NR_V148B = tregister($0417000E);
+NR_V1416B = tregister($0418000E);
 NR_B15 = tregister($0401000F);
 NR_H15 = tregister($0403000F);
 NR_S15 = tregister($0409000F);
 NR_D15 = tregister($040a000F);
 NR_Q15 = tregister($0405000F);
+NR_V158B = tregister($0417000F);
+NR_V1516B = tregister($0418000F);
 NR_B16 = tregister($04010010);
 NR_H16 = tregister($04030010);
 NR_S16 = tregister($04090010);
 NR_D16 = tregister($040a0010);
 NR_Q16 = tregister($04050010);
+NR_V168B = tregister($04170010);
+NR_V1616B = tregister($04180010);
 NR_B17 = tregister($04010011);
 NR_H17 = tregister($04030011);
 NR_S17 = tregister($04090011);
 NR_D17 = tregister($040a0011);
 NR_Q17 = tregister($04050011);
+NR_V178B = tregister($04170011);
+NR_V1716B = tregister($04180011);
 NR_B18 = tregister($04010012);
 NR_H18 = tregister($04030012);
 NR_S18 = tregister($04090012);
 NR_D18 = tregister($040a0012);
 NR_Q18 = tregister($04050012);
+NR_V188B = tregister($04170012);
+NR_V1816B = tregister($04180012);
 NR_B19 = tregister($04010013);
 NR_H19 = tregister($04030013);
 NR_S19 = tregister($04090013);
 NR_D19 = tregister($040a0013);
 NR_Q19 = tregister($04050013);
+NR_V198B = tregister($04170013);
+NR_V1916B = tregister($04180013);
 NR_B20 = tregister($04010014);
 NR_H20 = tregister($04030014);
 NR_S20 = tregister($04090014);
 NR_D20 = tregister($040a0014);
 NR_Q20 = tregister($04050014);
+NR_V208B = tregister($04170014);
+NR_V2016B = tregister($04180014);
 NR_B21 = tregister($04010015);
 NR_H21 = tregister($04030015);
 NR_S21 = tregister($04090015);
 NR_D21 = tregister($040a0015);
 NR_Q21 = tregister($04050015);
+NR_V218B = tregister($04170015);
+NR_V2116B = tregister($04180015);
 NR_B22 = tregister($04010016);
 NR_H22 = tregister($04030016);
 NR_S22 = tregister($04090016);
 NR_D22 = tregister($040a0016);
 NR_Q22 = tregister($04050016);
+NR_V228B = tregister($04170016);
+NR_V2216B = tregister($04180016);
 NR_B23 = tregister($04010017);
 NR_H23 = tregister($04030017);
 NR_S23 = tregister($04090017);
 NR_D23 = tregister($040a0017);
 NR_Q23 = tregister($04050017);
+NR_V238B = tregister($04170017);
+NR_V2316B = tregister($04180017);
 NR_B24 = tregister($04010018);
 NR_H24 = tregister($04030018);
 NR_S24 = tregister($04090018);
 NR_D24 = tregister($040a0018);
 NR_Q24 = tregister($04050018);
+NR_V248B = tregister($04170018);
+NR_V2416B = tregister($04180018);
 NR_B25 = tregister($04010019);
 NR_H25 = tregister($04030019);
 NR_S25 = tregister($04090019);
 NR_D25 = tregister($040a0019);
 NR_Q25 = tregister($04050019);
+NR_V258B = tregister($04170019);
+NR_V2516B = tregister($04180019);
 NR_B26 = tregister($0401001A);
 NR_H26 = tregister($0403001A);
 NR_S26 = tregister($0409001A);
 NR_D26 = tregister($040a001A);
 NR_Q26 = tregister($0405001A);
+NR_V268B = tregister($0417001A);
+NR_V2616B = tregister($0418001A);
 NR_B27 = tregister($0401001B);
 NR_H27 = tregister($0403001B);
 NR_S27 = tregister($0409001B);
 NR_D27 = tregister($040a001B);
 NR_Q27 = tregister($0405001B);
+NR_V278B = tregister($0417001B);
+NR_V2716B = tregister($0418001B);
 NR_B28 = tregister($0401001C);
 NR_H28 = tregister($0403001C);
 NR_S28 = tregister($0409001C);
 NR_D28 = tregister($040a001C);
 NR_Q28 = tregister($0405001C);
+NR_V288B = tregister($0417001C);
+NR_V2816B = tregister($0418001C);
 NR_B29 = tregister($0401001D);
 NR_H29 = tregister($0403001D);
 NR_S29 = tregister($0409001D);
 NR_D29 = tregister($040a001D);
 NR_Q29 = tregister($0405001D);
+NR_V298B = tregister($0417001D);
+NR_V2916B = tregister($0418001D);
 NR_B30 = tregister($0401001E);
 NR_H30 = tregister($0403001E);
 NR_S30 = tregister($0409001E);
 NR_D30 = tregister($040a001E);
 NR_Q30 = tregister($0405001E);
+NR_V308B = tregister($0417001E);
+NR_V3016B = tregister($0418001E);
 NR_B31 = tregister($0401001F);
 NR_H31 = tregister($0403001F);
 NR_S31 = tregister($0409001F);
 NR_D31 = tregister($040a001F);
 NR_Q31 = tregister($0405001F);
+NR_V318B = tregister($0417001F);
+NR_V3116B = tregister($0418001F);
 NR_NZCV = tregister($05000000);
 NR_FPCR = tregister($05000001);
 NR_FPSR = tregister($05000002);

compiler/aarch64/ra64dwa.inc

@@ -71,6 +71,10 @@
 64,
 64,
 64,
+64,
+64,
+65,
+65,
 65,
 65,
 65,
@@ -81,6 +85,10 @@
 66,
 66,
 66,
+66,
+66,
+67,
+67,
 67,
 67,
 67,
@@ -91,6 +99,10 @@
 68,
 68,
 68,
+68,
+68,
+69,
+69,
 69,
 69,
 69,
@@ -98,129 +110,181 @@
 69,
 70,
 70,
+70                                                             ,
 70,
 70,
 70,
+70,
+71,
 71,
 71,
 71,
 71,
 71,
+71,
+72,
 72,
 72,
 72,
 72,
 72,
+72,
+73,
 73,
 73,
 73,
 73,
 73,
+73,
+74,
 74,
 74,
 74,
 74,
 74,
+74,
+75,
 75,
 75,
 75,
 75,
 75,
+75,
+76,
 76,
 76,
 76,
 76,
 76,
+76,
+77,
 77,
 77,
 77,
 77,
 77,
+77,
+78,
 78,
 78,
 78,
 78,
 78,
+78,
+79,
 79,
 79,
 79,
 79,
 79,
+79,
+80,
 80,
 80,
 80,
 80,
 80,
+80,
+81,
 81,
 81,
 81,
 81,
 81,
+81,
+82,
 82,
 82,
 82,
 82,
 82,
+82,
+83,
 83,
 83,
 83,
 83,
 83,
+83,
+84,
 84,
 84,
 84,
 84,
 84,
+84,
+85,
 85,
 85,
 85,
 85,
 85,
+85,
+86,
 86,
 86,
 86,
 86,
 86,
+86,
+87,
 87,
 87,
 87,
 87,
 87,
+87,
+88,
 88,
 88,
 88,
 88,
 88,
+88,
+89,
 89,
 89,
 89,
 89,
 89,
+89,
+90,
 90,
 90,
 90,
 90,
 90,
+90,
+91,
 91,
 91,
 91,
 91,
 91,
+91,
+92,
 92,
 92,
 92,
 92,
 92,
+92,
+93,
 93,
 93,
 93,
 93,
 93,
+93,
+94,
 94,
 94,
 94,
 94,
 94,
+94,
+95,
+95,
 95,
 95,
 95,

compiler/aarch64/ra64nor.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from a64reg.dat }
-231
+295

compiler/aarch64/ra64num.inc

@@ -71,161 +71,225 @@ tregister($04030000),
 tregister($04090000),
 tregister($040a0000),
 tregister($04050000),
+tregister($04170000),
+tregister($04180000),
 tregister($04010001),
 tregister($04030001),
 tregister($04090001),
 tregister($040a0001),
 tregister($04050001),
+tregister($04170001),
+tregister($04180001),
 tregister($04010002),
 tregister($04030002),
 tregister($04090002),
 tregister($040a0002),
 tregister($04050002),
+tregister($04170002),
+tregister($04180002),
 tregister($04010003),
 tregister($04030003),
 tregister($04090003),
 tregister($040a0003),
 tregister($04050003),
+tregister($04170003),
+tregister($04180003),
 tregister($04010004),
 tregister($04030004),
 tregister($04090004),
 tregister($040a0004),
 tregister($04050004),
+tregister($04170004),
+tregister($04180004),
 tregister($04010005),
 tregister($04030005),
 tregister($04090005),
 tregister($040a0005),
 tregister($04050005),
+tregister($04170005),
+tregister($04180005),
 tregister($04010006),
 tregister($04030006),
 tregister($04090006),
 tregister($040a0006),
 tregister($04050006),
+tregister($04170006),
+tregister($04180006),
 tregister($04010007),
 tregister($04030007),
 tregister($04090007),
 tregister($040a0007),
 tregister($04050007),
+tregister($04170007),
+tregister($04180007),
 tregister($04010008),
 tregister($04030008),
 tregister($04090008),
 tregister($040a0008),
 tregister($04050008),
+tregister($04170008),
+tregister($04180008),
 tregister($04010009),
 tregister($04030009),
 tregister($04090009),
 tregister($040a0009),
 tregister($04050009),
+tregister($04170009),
+tregister($04180009),
 tregister($0401000A),
 tregister($0403000A),
 tregister($0409000A),
 tregister($040a000A),
 tregister($0405000A),
+tregister($0417000A),
+tregister($0418000A),
 tregister($0401000B),
 tregister($0403000B),
 tregister($0409000B),
 tregister($040a000B),
 tregister($0405000B),
+tregister($0417000B),
+tregister($0418000B),
 tregister($0401000C),
 tregister($0403000C),
 tregister($0409000C),
 tregister($040a000C),
 tregister($0405000C),
+tregister($0417000C),
+tregister($0418000C),
 tregister($0401000D),
 tregister($0403000D),
 tregister($0409000D),
 tregister($040a000D),
 tregister($0405000D),
+tregister($0417000D),
+tregister($0418000D),
 tregister($0401000E),
 tregister($0403000E),
 tregister($0409000E),
 tregister($040a000E),
 tregister($0405000E),
+tregister($0417000E),
+tregister($0418000E),
 tregister($0401000F),
 tregister($0403000F),
 tregister($0409000F),
 tregister($040a000F),
 tregister($0405000F),
+tregister($0417000F),
+tregister($0418000F),
 tregister($04010010),
 tregister($04030010),
 tregister($04090010),
 tregister($040a0010),
 tregister($04050010),
+tregister($04170010),
+tregister($04180010),
 tregister($04010011),
 tregister($04030011),
 tregister($04090011),
 tregister($040a0011),
 tregister($04050011),
+tregister($04170011),
+tregister($04180011),
 tregister($04010012),
 tregister($04030012),
 tregister($04090012),
 tregister($040a0012),
 tregister($04050012),
+tregister($04170012),
+tregister($04180012),
 tregister($04010013),
 tregister($04030013),
 tregister($04090013),
 tregister($040a0013),
 tregister($04050013),
+tregister($04170013),
+tregister($04180013),
 tregister($04010014),
 tregister($04030014),
 tregister($04090014),
 tregister($040a0014),
 tregister($04050014),
+tregister($04170014),
+tregister($04180014),
 tregister($04010015),
 tregister($04030015),
 tregister($04090015),
 tregister($040a0015),
 tregister($04050015),
+tregister($04170015),
+tregister($04180015),
 tregister($04010016),
 tregister($04030016),
 tregister($04090016),
 tregister($040a0016),
 tregister($04050016),
+tregister($04170016),
+tregister($04180016),
 tregister($04010017),
 tregister($04030017),
 tregister($04090017),
 tregister($040a0017),
 tregister($04050017),
+tregister($04170017),
+tregister($04180017),
 tregister($04010018),
 tregister($04030018),
 tregister($04090018),
 tregister($040a0018),
 tregister($04050018),
+tregister($04170018),
+tregister($04180018),
 tregister($04010019),
 tregister($04030019),
 tregister($04090019),
 tregister($040a0019),
 tregister($04050019),
+tregister($04170019),
+tregister($04180019),
 tregister($0401001A),
 tregister($0403001A),
 tregister($0409001A),
 tregister($040a001A),
 tregister($0405001A),
+tregister($0417001A),
+tregister($0418001A),
 tregister($0401001B),
 tregister($0403001B),
 tregister($0409001B),
 tregister($040a001B),
 tregister($0405001B),
+tregister($0417001B),
+tregister($0418001B),
 tregister($0401001C),
 tregister($0403001C),
 tregister($0409001C),
 tregister($040a001C),
 tregister($0405001C),
+tregister($0417001C),
+tregister($0418001C),
 tregister($0401001D),
 tregister($0403001D),
 tregister($0409001D),
 tregister($040a001D),
 tregister($0405001D),
+tregister($0417001D),
+tregister($0418001D),
 tregister($0401001E),
 tregister($0403001E),
 tregister($0409001E),
 tregister($040a001E),
 tregister($0405001E),
+tregister($0417001E),
+tregister($0418001E),
 tregister($0401001F),
 tregister($0403001F),
 tregister($0409001F),
 tregister($040a001F),
 tregister($0405001F),
+tregister($0417001F),
+tregister($0418001F),
 tregister($05000000),
 tregister($05000001),
 tregister($05000002),

compiler/aarch64/ra64rni.inc

@@ -67,166 +67,230 @@
 64,
 66,
 67,
-72,
-77,
-82,
-87,
-92,
-97,
+74,
+81,
+88,
+95,
 102,
-107,
-112,
-117,
-122,
-127,
-132,
+109,
+116,
+123,
+130,
 137,
-142,
-147,
-152,
-157,
-162,
-167,
+144,
+151,
+158,
+165,
 172,
-177,
-182,
-187,
-192,
-197,
-202,
+179,
+186,
+193,
+200,
 207,
-212,
-217,
-222,
+214,
+221,
+228,
+235,
+242,
+249,
+256,
+263,
+270,
+277,
+284,
 68,
-73,
-78,
-83,
-88,
-93,
-98,
+75,
+82,
+89,
+96,
 103,
-108,
-113,
-118,
-123,
-128,
-133,
+110,
+117,
+124,
+131,
 138,
-143,
-148,
-153,
-158,
-163,
-168,
+145,
+152,
+159,
+166,
 173,
-178,
-183,
-188,
-193,
-198,
-203,
+180,
+187,
+194,
+201,
 208,
-213,
-218,
-223,
+215,
+222,
+229,
+236,
+243,
+250,
+257,
+264,
+271,
+278,
+285,
 71,
-76,
-81,
-86,
-91,
-96,
-101,
+78,
+85,
+92,
+99,
 106,
-111,
-116,
-121,
-126,
-131,
-136,
+113,
+120,
+127,
+134,
 141,
-146,
-151,
-156,
-161,
-166,
-171,
+148,
+155,
+162,
+169,
 176,
-181,
-186,
-191,
-196,
-201,
-206,
+183,
+190,
+197,
+204,
 211,
-216,
-221,
-226,
+218,
+225,
+232,
+239,
+246,
+253,
+260,
+267,
+274,
+281,
+288,
 69,
-74,
-79,
-84,
-89,
-94,
-99,
+76,
+83,
+90,
+97,
 104,
-109,
-114,
-119,
-124,
-129,
-134,
+111,
+118,
+125,
+132,
 139,
-144,
-149,
-154,
-159,
-164,
-169,
+146,
+153,
+160,
+167,
 174,
-179,
-184,
-189,
-194,
-199,
-204,
+181,
+188,
+195,
+202,
 209,
-214,
-219,
-224,
+216,
+223,
+230,
+237,
+244,
+251,
+258,
+265,
+272,
+279,
+286,
 70,
-75,
-80,
-85,
-90,
-95,
-100,
+77,
+84,
+91,
+98,
 105,
-110,
-115,
-120,
-125,
-130,
-135,
+112,
+119,
+126,
+133,
 140,
-145,
-150,
-155,
-160,
-165,
-170,
+147,
+154,
+161,
+168,
 175,
-180,
-185,
-190,
-195,
-200,
-205,
+182,
+189,
+196,
+203,
 210,
-215,
+217,
+224,
+231,
+238,
+245,
+252,
+259,
+266,
+273,
+280,
+287,
+72,
+79,
+86,
+93,
+100,
+107,
+114,
+121,
+128,
+135,
+142,
+149,
+156,
+163,
+170,
+177,
+184,
+191,
+198,
+205,
+212,
+219,
+226,
+233,
+240,
+247,
+254,
+261,
+268,
+275,
+282,
+289,
+73,
+80,
+87,
+94,
+101,
+108,
+115,
+122,
+129,
+136,
+143,
+150,
+157,
+164,
+171,
+178,
+185,
+192,
+199,
+206,
+213,
 220,
-225,
 227,
-228,
-229,
-230
+234,
+241,
+248,
+255,
+262,
+269,
+276,
+283,
+290,
+291,
+292,
+293,
+294

compiler/aarch64/ra64sri.inc

@@ -1,170 +1,234 @@
 { don't edit, this file is generated from a64reg.dat }
 0,
 67,
-72,
-117,
-122,
-127,
-132,
+74,
 137,
-142,
-147,
-152,
-157,
-162,
-77,
-167,
+144,
+151,
+158,
+165,
 172,
-177,
-182,
-187,
-192,
-197,
-202,
+179,
+186,
+193,
+200,
+81,
 207,
-212,
-82,
-217,
-222,
-87,
-92,
-97,
+214,
+221,
+228,
+235,
+242,
+249,
+256,
+263,
+270,
+88,
+277,
+284,
+95,
 102,
-107,
-112,
-70,
-75,
-120,
-125,
+109,
+116,
+123,
 130,
-135,
+70,
+77,
 140,
-145,
-150,
-155,
-160,
-165,
-80,
-170,
+147,
+154,
+161,
+168,
 175,
-180,
-185,
-190,
-195,
-200,
-205,
+182,
+189,
+196,
+203,
+84,
 210,
-215,
-85,
-220,
-225,
-90,
-95,
-100,
+217,
+224,
+231,
+238,
+245,
+252,
+259,
+266,
+273,
+91,
+280,
+287,
+98,
 105,
-110,
-115,
-228,
-229,
-68,
-73,
-118,
-123,
-128,
+112,
+119,
+126,
 133,
+292,
+293,
+68,
+75,
 138,
-143,
-148,
-153,
-158,
-163,
-78,
-168,
+145,
+152,
+159,
+166,
 173,
-178,
-183,
-188,
-193,
-198,
-203,
+180,
+187,
+194,
+201,
+82,
 208,
-213,
-83,
-218,
-223,
-88,
-93,
-98,
+215,
+222,
+229,
+236,
+243,
+250,
+257,
+264,
+271,
+89,
+278,
+285,
+96,
 103,
-108,
-113,
-227,
-71,
-76,
-121,
-126,
+110,
+117,
+124,
 131,
-136,
+291,
+71,
+78,
 141,
-146,
-151,
-156,
-161,
-166,
-81,
-171,
+148,
+155,
+162,
+169,
 176,
-181,
-186,
-191,
-196,
-201,
-206,
+183,
+190,
+197,
+204,
+85,
 211,
-216,
-86,
-221,
-226,
-91,
-96,
-101,
+218,
+225,
+232,
+239,
+246,
+253,
+260,
+267,
+274,
+92,
+281,
+288,
+99,
 106,
-111,
-116,
-69,
-74,
-119,
-124,
-129,
+113,
+120,
+127,
 134,
+69,
+76,
 139,
-144,
+146,
+153,
+160,
+167,
+174,
+181,
+188,
+195,
+202,
+83,
+209,
+216,
+223,
+230,
+237,
+244,
+251,
+258,
+265,
+272,
+90,
+279,
+286,
+97,
+104,
+111,
+118,
+125,
+132,
+66,
+294,
+73,
+72,
+80,
+79,
+143,
+142,
+150,
 149,
-154,
-159,
+157,
+156,
 164,
-79,
-169,
-174,
-179,
+163,
+171,
+170,
+178,
+177,
+185,
 184,
-189,
-194,
+192,
+191,
 199,
-204,
-209,
-214,
-84,
+198,
+206,
+205,
+87,
+86,
+213,
+212,
+220,
 219,
-224,
-89,
+227,
+226,
+234,
+233,
+241,
+240,
+248,
+247,
+255,
+254,
+262,
+261,
+269,
+268,
+276,
+275,
 94,
-99,
-104,
-109,
+93,
+283,
+282,
+290,
+289,
+101,
+100,
+108,
+107,
+115,
 114,
-66,
-230,
+122,
+121,
+129,
+128,
+136,
+135,
 1,
 3,
 21,

compiler/aarch64/ra64sta.inc

@@ -71,6 +71,10 @@
 64,
 64,
 64,
+64,
+64,
+65,
+65,
 65,
 65,
 65,
@@ -81,6 +85,10 @@
 66,
 66,
 66,
+66,
+66,
+67,
+67,
 67,
 67,
 67,
@@ -91,6 +99,10 @@
 68,
 68,
 68,
+68,
+68,
+69,
+69,
 69,
 69,
 69,
@@ -101,6 +113,10 @@
 70,
 70,
 70,
+70,
+70,
+71,
+71,
 71,
 71,
 71,
@@ -111,6 +127,10 @@
 72,
 72,
 72,
+72,
+72,
+73,
+73,
 73,
 73,
 73,
@@ -121,6 +141,10 @@
 74,
 74,
 74,
+74,
+74,
+75,
+75,
 75,
 75,
 75,
@@ -131,6 +155,10 @@
 76,
 76,
 76,
+76,
+76,
+77,
+77,
 77,
 77,
 77,
@@ -141,6 +169,10 @@
 78,
 78,
 78,
+78,
+78,
+79,
+79,
 79,
 79,
 79,
@@ -151,6 +183,10 @@
 80,
 80,
 80,
+80,
+80,
+81,
+81,
 81,
 81,
 81,
@@ -161,6 +197,10 @@
 82,
 82,
 82,
+82,
+82,
+83,
+83,
 83,
 83,
 83,
@@ -171,6 +211,10 @@
 84,
 84,
 84,
+84,
+84,
+85,
+85,
 85,
 85,
 85,
@@ -181,6 +225,10 @@
 86,
 86,
 86,
+86,
+86,
+87,
+87,
 87,
 87,
 87,
@@ -191,6 +239,10 @@
 88,
 88,
 88,
+88,
+88,
+89,
+89,
 89,
 89,
 89,
@@ -201,6 +253,10 @@
 90,
 90,
 90,
+90,
+90,
+91,
+91,
 91,
 91,
 91,
@@ -211,6 +267,10 @@
 92,
 92,
 92,
+92,
+92,
+93,
+93,
 93,
 93,
 93,
@@ -221,6 +281,10 @@
 94,
 94,
 94,
+94,
+94,
+95,
+95,
 95,
 95,
 95,

compiler/aarch64/ra64std.inc

@@ -71,161 +71,225 @@
 's0',
 'd0',
 'q0',
+'v0.8b',
+'v0.16b',
 'b1',
 'h1',
 's1',
 'd1',
 'q1',
+'v1.8b',
+'v1.16b',
 'b2',
 'h2',
 's2',
 'd2',
 'q2',
+'v2.8b',
+'v2.16b',
 'b3',
 'h3',
 's3',
 'd3',
 'q3',
+'v3.8b',
+'v3.16b',
 'b4',
 'h4',
 's4',
 'd4',
 'q4',
+'v4.8b',
+'v4.16b',
 'b5',
 'h5',
 's5',
 'd5',
 'q5',
+'v5.8b',
+'v5.16b',
 'b6',
 'h6',
 's6',
 'd6',
 'q6',
+'v6.8b',
+'v6.16b',
 'b7',
 'h7',
 's7',
 'd7',
 'q7',
+'v7.8b',
+'v7.16b',
 'b8',
 'h8',
 's8',
 'd8',
 'q8',
+'v8.8b',
+'v8.16b',
 'b9',
 'h9',
 's9',
 'd9',
 'q9',
+'v9.8b',
+'v9.16b',
 'b10',
 'h10',
 's10',
 'd10',
 'q10',
+'v10.8b',
+'v10.16b',
 'b11',
 'h11',
 's11',
 'd11',
 'q11',
+'v11.8b',
+'v11.16b',
 'b12',
 'h12',
 's12',
 'd12',
 'q12',
+'v12.8b',
+'v12.16b',
 'b13',
 'h13',
 's13',
 'd13',
 'q13',
+'v13.8b',
+'v13.16b',
 'b14',
 'h14',
 's14',
 'd14',
 'q14',
+'v14.8b',
+'v14.16b',
 'b15',
 'h15',
 's15',
 'd15',
 'q15',
+'v15.8b',
+'v15.16b',
 'b16',
 'h16',
 's16',
 'd16',
 'q16',
+'v16.8b',
+'v16.16b',
 'b17',
 'h17',
 's17',
 'd17',
 'q17',
+'v17.8b',
+'v17.16b',
 'b18',
 'h18',
 's18',
 'd18',
 'q18',
+'v18.8b',
+'v18.16b',
 'b19',
 'h19',
 's19',
 'd19',
 'q19',
+'v19.8b',
+'v19.16b',
 'b20',
 'h20',
 's20',
 'd20',
 'q20',
+'v20.8b',
+'v20.16b',
 'b21',
 'h21',
 's21',
 'd21',
 'q21',
+'v21.8b',
+'v21.16b',
 'b22',
 'h22',
 's22',
 'd22',
 'q22',
+'v22.8b',
+'v22.16b',
 'b23',
 'h23',
 's23',
 'd23',
 'q23',
+'v23.8b',
+'v23.16b',
 'b24',
 'h24',
 's24',
 'd24',
 'q24',
+'v24.8b',
+'v24.16b',
 'b25',
 'h25',
 's25',
 'd25',
 'q25',
+'v25.8b',
+'v25.16b',
 'b26',
 'h26',
 's26',
 'd26',
 'q26',
+'v26.8b',
+'v26.16b',
 'b27',
 'h27',
 's27',
 'd27',
 'q27',
+'v27.8b',
+'v27.16b',
 'b28',
 'h28',
 's28',
 'd28',
 'q28',
+'v28.8b',
+'v28.16b',
 'b29',
 'h29',
 's29',
 'd29',
 'q29',
+'v29.8b',
+'v29.16b',
 'b30',
 'h30',
 's30',
 'd30',
 'q30',
+'v30.8b',
+'v30.16b',
 'b31',
 'h31',
 's31',
 'd31',
 'q31',
+'v31.8b',
+'v31.16b',
 'nzcv',
 'fpcr',
 'fpsr',

compiler/aarch64/ra64sup.inc

@@ -71,161 +71,225 @@ RS_H0 = $00;
 RS_S0 = $00;
 RS_D0 = $00;
 RS_Q0 = $00;
+RS_V08B = $00;
+RS_V016B = $00;
 RS_B1 = $01;
 RS_H1 = $01;
 RS_S1 = $01;
 RS_D1 = $01;
 RS_Q1 = $01;
+RS_V18B = $01;
+RS_V116B = $01;
 RS_B2 = $02;
 RS_H2 = $02;
 RS_S2 = $02;
 RS_D2 = $02;
 RS_Q2 = $02;
+RS_V28B = $02;
+RS_V216B = $02;
 RS_B3 = $03;
 RS_H3 = $03;
 RS_S3 = $03;
 RS_D3 = $03;
 RS_Q3 = $03;
+RS_V38B = $03;
+RS_V316B = $03;
 RS_B4 = $04;
 RS_H4 = $04;
 RS_S4 = $04;
 RS_D4 = $04;
 RS_Q4 = $04;
+RS_V48B = $04;
+RS_V416B = $04;
 RS_B5 = $05;
 RS_H5 = $05;
 RS_S5 = $05;
 RS_D5 = $05;
 RS_Q5 = $05;
+RS_V58B = $05;
+RS_V516B = $05;
 RS_B6 = $06;
 RS_H6 = $06;
 RS_S6 = $06;
 RS_D6 = $06;
 RS_Q6 = $06;
+RS_V68B = $06;
+RS_V616B = $06;
 RS_B7 = $07;
 RS_H7 = $07;
 RS_S7 = $07;
 RS_D7 = $07;
 RS_Q7 = $07;
+RS_V78B = $07;
+RS_V716B = $07;
 RS_B8 = $08;
 RS_H8 = $08;
 RS_S8 = $08;
 RS_D8 = $08;
 RS_Q8 = $08;
+RS_V88B = $08;
+RS_V816B = $08;
 RS_B9 = $09;
 RS_H9 = $09;
 RS_S9 = $09;
 RS_D9 = $09;
 RS_Q9 = $09;
+RS_V98B = $09;
+RS_V916B = $09;
 RS_B10 = $0A;
 RS_H10 = $0A;
 RS_S10 = $0A;
 RS_D10 = $0A;
 RS_Q10 = $0A;
+RS_V108B = $0A;
+RS_V1016B = $0A;
 RS_B11 = $0B;
 RS_H11 = $0B;
 RS_S11 = $0B;
 RS_D11 = $0B;
 RS_Q11 = $0B;
+RS_V118B = $0B;
+RS_V1116B = $0B;
 RS_B12 = $0C;
 RS_H12 = $0C;
 RS_S12 = $0C;
 RS_D12 = $0C;
 RS_Q12 = $0C;
+RS_V128B = $0C;
+RS_V1216B = $0C;
 RS_B13 = $0D;
 RS_H13 = $0D;
 RS_S13 = $0D;
 RS_D13 = $0D;
 RS_Q13 = $0D;
+RS_V138B = $0D;
+RS_V1316B = $0D;
 RS_B14 = $0E;
 RS_H14 = $0E;
 RS_S14 = $0E;
 RS_D14 = $0E;
 RS_Q14 = $0E;
+RS_V148B = $0E;
+RS_V1416B = $0E;
 RS_B15 = $0F;
 RS_H15 = $0F;
 RS_S15 = $0F;
 RS_D15 = $0F;
 RS_Q15 = $0F;
+RS_V158B = $0F;
+RS_V1516B = $0F;
 RS_B16 = $10;
 RS_H16 = $10;
 RS_S16 = $10;
 RS_D16 = $10;
 RS_Q16 = $10;
+RS_V168B = $10;
+RS_V1616B = $10;
 RS_B17 = $11;
 RS_H17 = $11;
 RS_S17 = $11;
 RS_D17 = $11;
 RS_Q17 = $11;
+RS_V178B = $11;
+RS_V1716B = $11;
 RS_B18 = $12;
 RS_H18 = $12;
 RS_S18 = $12;
 RS_D18 = $12;
 RS_Q18 = $12;
+RS_V188B = $12;
+RS_V1816B = $12;
 RS_B19 = $13;
 RS_H19 = $13;
 RS_S19 = $13;
 RS_D19 = $13;
 RS_Q19 = $13;
+RS_V198B = $13;
+RS_V1916B = $13;
 RS_B20 = $14;
 RS_H20 = $14;
 RS_S20 = $14;
 RS_D20 = $14;
 RS_Q20 = $14;
+RS_V208B = $14;
+RS_V2016B = $14;
 RS_B21 = $15;
 RS_H21 = $15;
 RS_S21 = $15;
 RS_D21 = $15;
 RS_Q21 = $15;
+RS_V218B = $15;
+RS_V2116B = $15;
 RS_B22 = $16;
 RS_H22 = $16;
 RS_S22 = $16;
 RS_D22 = $16;
 RS_Q22 = $16;
+RS_V228B = $16;
+RS_V2216B = $16;
 RS_B23 = $17;
 RS_H23 = $17;
 RS_S23 = $17;
 RS_D23 = $17;
 RS_Q23 = $17;
+RS_V238B = $17;
+RS_V2316B = $17;
 RS_B24 = $18;
 RS_H24 = $18;
 RS_S24 = $18;
 RS_D24 = $18;
 RS_Q24 = $18;
+RS_V248B = $18;
+RS_V2416B = $18;
 RS_B25 = $19;
 RS_H25 = $19;
 RS_S25 = $19;
 RS_D25 = $19;
 RS_Q25 = $19;
+RS_V258B = $19;
+RS_V2516B = $19;
 RS_B26 = $1A;
 RS_H26 = $1A;
 RS_S26 = $1A;
 RS_D26 = $1A;
 RS_Q26 = $1A;
+RS_V268B = $1A;
+RS_V2616B = $1A;
 RS_B27 = $1B;
 RS_H27 = $1B;
 RS_S27 = $1B;
 RS_D27 = $1B;
 RS_Q27 = $1B;
+RS_V278B = $1B;
+RS_V2716B = $1B;
 RS_B28 = $1C;
 RS_H28 = $1C;
 RS_S28 = $1C;
 RS_D28 = $1C;
 RS_Q28 = $1C;
+RS_V288B = $1C;
+RS_V2816B = $1C;
 RS_B29 = $1D;
 RS_H29 = $1D;
 RS_S29 = $1D;
 RS_D29 = $1D;
 RS_Q29 = $1D;
+RS_V298B = $1D;
+RS_V2916B = $1D;
 RS_B30 = $1E;
 RS_H30 = $1E;
 RS_S30 = $1E;
 RS_D30 = $1E;
 RS_Q30 = $1E;
+RS_V308B = $1E;
+RS_V3016B = $1E;
 RS_B31 = $1F;
 RS_H31 = $1F;
 RS_S31 = $1F;
 RS_D31 = $1F;
 RS_Q31 = $1F;
+RS_V318B = $1F;
+RS_V3116B = $1F;
 RS_NZCV = $00;
 RS_FPCR = $01;
 RS_FPSR = $02;

compiler/arm/cpubase.pas

@@ -113,9 +113,6 @@ unit cpubase;
 
       VOLATILE_INTREGISTERS_DARWIN = [RS_R0..RS_R3,RS_R9,RS_R12..RS_R14];
 
-    type
-      totherregisterset = set of tregisterindex;
-
 {*****************************************************************************
                           Instruction post fixes
 *****************************************************************************}

compiler/avr/cpubase.pas

@@ -128,9 +128,6 @@ unit cpubase;
       VOLATILE_INTREGISTERS = [RS_R0,RS_R1,RS_R18..RS_R27,RS_R30,RS_R31];
       VOLATILE_FPUREGISTERS = [];
 
-    type
-      totherregisterset = set of tregisterindex;
-
 {*****************************************************************************
                                 Conditions
 *****************************************************************************}

compiler/cgbase.pas

@@ -238,7 +238,9 @@ interface
         R_SUBFLAGSIGN,      { = 19; Sign flag }
         R_SUBFLAGOVERFLOW,  { = 20; Overflow flag }
         R_SUBFLAGINTERRUPT, { = 21; Interrupt enable flag }
-        R_SUBFLAGDIRECTION  { = 22; Direction flag }
+        R_SUBFLAGDIRECTION, { = 22; Direction flag }
+        R_SUBMM8B,  { = 23; for part of v regs on aarch64 }
+        R_SUBMM16B  { = 24; for part of v regs on aarch64 }
       );
       TSubRegisterSet = set of TSubRegister;
 
@@ -705,6 +707,8 @@ implementation
             result:=result+'my';
           R_SUBMMZ:
             result:=result+'mz';
+          R_SUBMM8B:
+            result:=result+'m8b';
           else
             internalerror(200308252);
         end;

compiler/jvm/cpubase.pas

@@ -119,7 +119,6 @@ uses
     type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rjvmnor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       { Available Superregisters }

compiler/m68k/cpubase.pas

@@ -158,10 +158,6 @@ unit cpubase;
       VOLATILE_FPUREGISTERS = [RS_FP0,RS_FP1];
       VOLATILE_ADDRESSREGISTERS = [RS_A0,RS_A1];
 
-    type
-      totherregisterset = set of tregisterindex;
-
-
 {*****************************************************************************
                                 Conditions
 *****************************************************************************}

compiler/mips/cpubase.pas

@@ -102,9 +102,6 @@ unit cpubase;
       VOLATILE_INTREGISTERS = [RS_R0..RS_R3,RS_R12..RS_R15];
       VOLATILE_FPUREGISTERS = [RS_F0..RS_F3];
 
-    type
-      totherregisterset = set of tregisterindex;
-
 {*****************************************************************************
                                 Conditions
 *****************************************************************************}

compiler/powerpc/cpubase.pas

@@ -105,7 +105,6 @@ uses
     type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rppcnor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       maxvarregs = 32-6; { 32 int registers - r0 - stackpointer - r2 - 3 scratch registers }

compiler/powerpc64/cpubase.pas

@@ -122,7 +122,6 @@ const
 type
   { Number of registers used for indexing in tables }
   tregisterindex = 0..{$I rppcnor.inc} - 1;
-  totherregisterset = set of tregisterindex;
 
 const
   maxvarregs = 32 - 6;

compiler/rgbase.pas

@@ -33,12 +33,12 @@ interface
       TRegisterIndexTable = array[tregisterindex] of tregisterindex;
 
     function findreg_by_number_table(r:Tregister;const regnumber_index:TRegisterIndexTable):tregisterindex;
-    function findreg_by_name_table(const s:string;const regname_table:TRegNameTable;const regname_index:TRegisterIndexTable):byte;
+    function findreg_by_name_table(const s:string;const regname_table:TRegNameTable;const regname_index:TRegisterIndexTable):tregisterindex;
 
 
 implementation
 
-    function findreg_by_name_table(const s:string;const regname_table:TRegNameTable;const regname_index:TRegisterIndexTable):byte;
+    function findreg_by_name_table(const s:string;const regname_table:TRegNameTable;const regname_index:TRegisterIndexTable):tregisterindex;
       var
         i,p,q : tregisterindex;
       begin

compiler/riscv32/cpubase.pas

@@ -108,7 +108,6 @@ uses
     type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rrv32nor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       maxvarregs = 32-6; { 32 int registers - r0 - stackpointer - r2 - 3 scratch registers }

compiler/riscv64/cpubase.pas

@@ -124,7 +124,6 @@ const
 type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rrv32nor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       maxvarregs = 32-6; { 32 int registers - r0 - stackpointer - r2 - 3 scratch registers }

compiler/sparcgen/cpubase.pas

@@ -59,7 +59,6 @@ uses
     type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rspnor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       { Available Superregisters }
@@ -102,7 +101,6 @@ uses
     type
       { Number of registers used for indexing in tables }
       tregisterindex=0..{$i rsp64nor.inc}-1;
-      totherregisterset = set of tregisterindex;
 
     const
       { Available Superregisters }

compiler/utils/mka64reg.pp

@@ -1,7 +1,7 @@
 {
     Copyright (c) 1998-2002 by Peter Vreman and Florian Klaempfl
 
-    Convert spreg.dat to several .inc files for usage with
+    Convert a64reg.dat to several .inc files for usage with
     the Free pascal compiler
 
     See the file COPYING.FPC, included in this distribution,
@@ -14,16 +14,16 @@
  **********************************************************************}
 {$mode objfpc}
 
-program mkspreg;
+program mka64reg;
 
 const Version = '1.00';
-      max_regcount = 254;
+      max_regcount = 1000;
 
 var s : string;
     i : longint;
     line : longint;
-    regcount:byte;
-    regcount_bsstart:byte;
+    regcount:word;
+    regcount_bsstart:word;
     names,
     regtypes,
     subtypes,
@@ -32,7 +32,7 @@ var s : string;
     stdnames,
     stabs,dwarf : array[0..max_regcount-1] of string[63];
     regnumber_index,
-    std_regname_index : array[0..max_regcount-1] of byte;
+    std_regname_index : array[0..max_regcount-1] of word;
 
 function tostr(l : longint) : string;
 
@@ -88,7 +88,7 @@ end;
 
 procedure build_regnum_index;
 
-var h,i,j,p,t:byte;
+var h,i,j,p,t:word;
 
 begin
   {Build the registernumber2regindex index.
@@ -119,7 +119,7 @@ end;
 
 procedure build_std_regname_index;
 
-var h,i,j,p,t:byte;
+var h,i,j,p,t:word;
 
 begin
   {Build the registernumber2regindex index.

compiler/x86/cpubase.pas

@@ -251,10 +251,6 @@ uses
       NR_DEFAULTFLAGS = NR_FLAGS;
 {$endif}
 
-   type
-      totherregisterset = set of tregisterindex;
-
-
 {*****************************************************************************
                                 Conditions
 *****************************************************************************}
@@ -482,7 +478,7 @@ implementation
 
     function reg_cgsize(const reg: tregister): tcgsize;
       const subreg2cgsize:array[Tsubregister] of Tcgsize =
-            (OS_NO,OS_8,OS_8,OS_16,OS_32,OS_64,OS_NO,OS_NO,OS_NO,OS_F32,OS_F64,OS_NO,OS_M128,OS_M256,OS_M512,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO);
+            (OS_NO,OS_8,OS_8,OS_16,OS_32,OS_64,OS_NO,OS_NO,OS_NO,OS_F32,OS_F64,OS_NO,OS_M128,OS_M256,OS_M512,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO,OS_NO);
       begin
         case getregtype(reg) of
           R_INTREGISTER :
@@ -518,7 +514,7 @@ implementation
     function reg2opsize(r:Tregister):topsize;
       const
         subreg2opsize : array[tsubregister] of topsize =
-          (S_NO,S_B,S_B,S_W,S_L,S_Q,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO);
+          (S_NO,S_B,S_B,S_W,S_L,S_Q,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO,S_NO);
       begin
         reg2opsize:=S_L;
         case getregtype(r) of